2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)

G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

Realization of an asymmetric Switched-Capacitor

Multilevel Inverter using Nearest Level Control
Anzar Ahmad MUAnas Adil Sarwer
Department of Electrical Engg Department of Electrical Engg Department of Electrical Engg
Aligarh Muslim University Aligarh MuslimUniversity Aligarh Muslim University
Aligarh,India Aligarh,India Aligarh, India
[email protected] [email protected] [email protected]

Mohammad Zaid Afroz Alam Zeeshan Sarwer

Department of Electrical Engg Department of Electrical Engg Department of Electrical Engg
Aligarh Muslim University Aligarh Muslim University Aligarh Muslim University
Aligarh,India Aligarh, India Aligarh, India
[email protected] [email protected] [email protected]

Abstract—In this paper, a thirty-one-level multilevel controllable frequency, phase, and amplitude [4]. It exhibits
inverter (MLI) with switched-capacitor (SC) is a better harmonic profile and thus filter requirement is
proposed. This topology consists of two asymmetric DC greatly reduced. The voltage stress on the semiconductor
voltage sources as input, four capacitors, sixteen switches is less, therefore, switches of smaller rating can be
semiconductor switches and two diodes. Each of these used in a MLI as compared to conventional two-level
units acts as DC-DC converter. Modified H Bridge inverter. Diode clamped, cascaded H Bridge and flying
which acts as a polarity generator is sandwiched capacitor are the conventional topologies of the MLI [5]-[6].
between two basic units. The left side of the circuit feeds However, as the voltage level is increased for these
three (V, 2Vand 3V) DC voltage levels while right side topologies the cost, and complexity increases. To avoid the
unit produces (4,8V and 12V) voltage levels. The problems new topologies with lower number of switches
proposed inverter naturally solves the problem of needs to be designed for higher efficiency and increased
capacitor voltage balancing by selecting proper values of reliability. These multilevel topologies are termed as
capacitance. Nearest- level control (NLC) technique is reduced device count MLI topology. In [7]-[8] authors have
used to reduce the distortion in output voltage. This proposed a MLI in which self-voltage boosting capability is
topology also eliminates the problem the having multiple absent for achieving higher number of voltage level from
DC sources and can also be connected to the grid. The low input voltage source and issues with capacitor voltage
proposed inverter is simulated in MATLAB®/Simulink balancing has been addressed. To mitigate voltage balancing
2016a.Significant reduction in total harmonic distortion issue, authors in [9]-[11] have introduced auxiliary circuitry
(THD) is observed in output voltage and current of the or complex control algorithm. These additional
inverter which is according to IEEE-519 standards for arrangements increase the overall cost of the system. In
harmonics. recent years, switched capacitor multilevel inverters
Keywords—Multilevel inverter, switched capacitor, nearest (SCMLIs) have become popular due to above mentioned
level control, total Harmonic distortion challenges with conventional MLIs. Mak, and Ioinovici
introduced the concept of switched-capacitor multilevel
I. INTRODUCTION
inverter in the year [12] 1998. Several other works on
Semiconductor devices working as a switch for the switched capacitor type MLI has been reported in [13]-[14].
conversion of DC to AC are typically known as an inverter Authors in [15] have presented a seven-level SC-MLI using
circuit. Inverters can be classified based on the nature of the two asymmetric voltage source and H bridge modules. With
output waveform such as square wave inverter, quasi square the help of boost converter, and a H Bridge authors in [16]
wave inverter, two-level PWM inverters and multilevel has generated a multilevel voltage. Authors in [17] have
inverter [1]. Due to large harmonic distortion in the proposed a novel basic unit, in this circuit, the H bridge
waveform at the output side of the conventional two-level inverter acts as a polarity generator, and it enhances the total
inverter, a pure AC sinusoid is not achieved [2]. Heating of standing voltage of the inverter. E. Zamiri and others in [18]
transformer core and EMI generation are also the have introduced a new SCMLI with reduced number of
consequences of high THD in line current in the case of switches. The high number of the level at the output had
conventional line commutated inverter [3]. The above been obtained by charging and discharging the capacitor in a
disadvantages are greatly reduced by the development of a binary asymmetrical pattern. In [19] authors have presented
multi-level inverter. MLIs compose of group power a novel structure of SCMLI. Output voltage with nine levels
semiconductors and capacitive voltage sources which can be has been produced with the help of one voltage source, one
controlled to generate voltage waveform with variable and diode, and ten semiconductor switches. Roy and others in

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 2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)
G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

[20] have developed a novel cross switched multilevel volt and 4V volt is taken. The left-side basic unit generates
inverter. Its basic unit produces three voltage levels with the V, 2V and 3V voltage levels while right side basic unit
help of two capacitors, five switches and one diode. produce 4V, 8V and 12V voltage levels. The maximum
Thirteen level and thirty-seven level voltage levels has been voltage across each capacitor in the left and right-side basic
obtained and verified by developing a prototype. units is V and 4V volt respectively. Pair of switches (S1, S2),
(S3, S4), (S5, S6), (S7, S8) in basic unit and (T1, T2), (T3, T4)
II. BASIC UNIT and (T5, T6) in modified H bridge are complementary to
Figure 1 shows the basic unit [20] of a switched-capacitor each other. The diode, D1 is connected in series with switch
multilevel inverter. This circuit consists of one voltage SCH1 on the left side of a basic unit and D2 on the right side
source, one diode, two capacitor and five IGBT of the basic unit is used to avoid the unwanted discharging
semiconductor switching devices.LI and L2 are two of C1, C2 or C3, C4 into the supply voltage.
capacitors legs while CH1 is termed as charging legs. S1, S2
in leg L1 and S3, S4 in leg L2 are bi-directional power C1 C4
switches. Charging leg CH1 is realized by an additional
T5
switch along with a power diode. The voltage source is S1 S2 S8 S7
connected at the midpoint of leg L1 and L2.
T1 T3
D1
S CH2
V LOAD _
C1 + 4V
S CH1 VO
D2
S1 S2 A
L1 + T2 T4

S3 S4 T6 S6 S5

D1
C2 C3
CH1 V
SCH1
Fig2. Thirty-one level SC-MLI with modified H bridge module
H

Table II Switching table of proposed scheme

S.NO S1 S3 SCH1 T1 T3 T5 S5 S7 SCH2 Level
1. 0 0 0 0 0 0 0 0 0 0V
L2 _
2. 0 0 0 1 0 0 0 0 0 V
S3 S4 N
3. 0 1 1 1 0 0 0 0 0 2V
C2
4. 1 1 0 1 0 0 0 0 0 3V
5. 0 0 0 0 1 0 0 0 0 4V
6. 0 0 0 1 1 0 0 0 0 5V
Fig. 1 Basic Unit of switched multilevel inverter
7. 1 0 1 1 1 0 0 0 0 6V
8. 1 1 0 1 1 0 0 0 0 7V
A. Working 9. 0 0 0 0 1 0 0 1 1 8V
. The output voltage is taken across point A and N. A 3V 10. 0 0 0 1 1 0 1 0 1 9V
voltage level is obtained by this basic unit. Switching and 11. 0 1 1 1 1 0 0 1 1 10V
capacitor states for the generation of all the three-level are 12. 1 1 0 1 1 0 1 0 1 11V
also shown in the Table1. Here 1 is for the on condition and 13. 0 0 0 0 1 0 1 1 0 12V
0 for the off condition. D, C, and NC stand for discharging, 14. 0 0 0 1 1 0 1 1 0 13V
charging and not connected states of capacitors. It is to be 15. 1 0 1 1 1 0 1 1 0 14V
noted that both the capacitors are charged up to DC supply 16. 1 1 0 1 1 0 1 1 0 15V
17. 0 0 0 1 1 1 0 0 0 0V
voltage level.
18. 0 0 0 0 1 1 0 0 0 -V
19. 0 1 1 0 1 1 0 0 0 -2V
Table I Switching and capacitor state of basic unit 20. 1 1 0 0 1 1 0 0 0 -3V
S1 S2 S3 S4 SCHI C1 C2 Level 21. 0 0 0 1 0 1 0 0 0 -4V
0 1 0 1 0 NC NC V 22. 0 0 0 0 0 1 0 0 0 -5V
23. 1 0 1 0 0 1 0 0 0 -6V
0 1 1 0 1 C D 2V 24. 1 1 0 0 0 1 0 0 0 -7V
1 0 0 1 1 D C 2V 25. 0 0 0 1 0 1 0 1 1 -8V
26. 0 0 0 0 0 1 1 0 1 -9V
1 0 1 0 0 D D 3V
27. 0 1 1 0 0 1 0 1 1 -10V
28. 1 1 0 0 0 1 1 0 1 -11V
29. 0 0 0 1 0 1 1 1 0 -12V
III. PROPOSED SCHEME 30. 0 0 0 0 0 1 1 1 0 -13V
31. 1 0 1 0 0 1 1 1 0 -14V
In this topology, a modified H bridge is connected with two
32. 1 1 0 0 0 1 1 1 0 -15V
basic units. Figure 3 represents the schematic diagram of
Note: S2, S4, S6, T2, T4. T6andT8 are complementary
this configuration. For asymmetric configuration dc voltage
switches, so states of these switches are opposite to: S1, S3,
source of each basic unit is different. Here, For the
S5, T1, T3.T5 and T7.
generation of thirty-one levels, rating of two DC supply is V

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 2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)
G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

A. Modes of operation
All the voltage levels are generated with the help of two
basic units and modified H bridge modules. Here basic unit
acts as
C1 C3 C1 C4
S1 S2 T5 S8 S7 S1 S2 T5 S8 S7

T1 T3 T1 T3
D1 D1
V LOAD _ SCH2 V LOAD SCH2
4V + _ 4V
SCH1 + VO CH1 VO
D2 D2
T2 T4 T2 T4
S3 S4 T6 S6 S5 S3 S4 S6 S5
T6
C2 C4 C2 C3
Mode 1
Mode 5
(a)
C1 (e) C4
C1 C3 T5
S1 S2 S8 S7
S1 S2 T5 S8 S7
T1 T3
T3 D1
T1 V SCH2
D1 LOAD _ 4V
V LOAD SCH2 SCH1 + VO
SCH1 + _ 4V D2
VO T2 T4
T4 D2
T2
S3 S4 T6 S6 S5
S3 S4 T6 S6 S5
C2 C3
C2 C4 Mode 6
Mode 2
(f)
(b)
C1 C3 C1 C4
T5 S1 S2 T5 S8 S7
S1 S2 S8 S7
T1 T3
T1 T3
D1 D1
SCH2 V SCH2
V LOAD _ LOAD _ 4V
+ 4V SCH1 + VO
SCH1 VO
D2 D2
T2 T4 T2 T4

S3 S4 S6 S5 S3 S4 T6 S6 S5
T6
C2 C4 C2 C3
Mode 3 Mode 7
(c) (g)
C1 C4 C1 C4
S1 S2 T5 S8 S7 T5 S8 S7
S1 S2
T1 T3 T1 T3
D1 D1
V SCH2 SCH2
LOAD _ 4V V LOAD _
SCH1 + + 4V
VO SCH1 VO
D2 D2
T2 T4 T2 T4
S3 S4 T6 S6 S5 S3 S4 S6 S5
T6
C2 C3 C2 C3
Mode 4
(d) Mode 8
(h)
C1 C4 C1 C4
S1 S2 T5 S8 S7 S1 S2 T5 S8 S7

T1 T3 T1 T3
D1 D1
V SCH2 SCH2
LOAD 4V V LOAD _ 4V
SCH1 _ SCH1 +
+ VO D2 VO D2
T2 T4 T2 T4
S3 S4 T6 S6 S5
S3 S4 T6 S6 S5
C2 C3
Mode 9 C2 C3
(i) Mode 13
(m)
C1 C4 C1 C4
S1 S2 T5 S8 S7 S1 S2 T5 S8 S7

T1 T3
T1 T3
D1 SCH2 D1
V LOAD V SCH2
SCH1 _ 4V LOAD _ 4V
+ VO SCH1 + VO
D2 D2
T2 T4
T2 T4
S3 S4 T6 S6 S5
S3 S4 T6 S6 S5
C2 C3
Mode 10 C2 C3
(j) Mode 14
C1 C4 (n)
C1 C4
S1 S2 T5 S8 S7
S1 S2 T5 S8 S7
T1 T3
D1 T1 T3
V SCH2 D1
+ LOAD _ 4V SCH2
SCH1 VO V LOAD _ 4V
D2 SCH1 +
T2 T4 VO
D2
T2 T4
S3 S4 T6 S6 S5
S3 S4 T6 S6 S5
C2 C3
Mode 11
C2 C3
(k) Mode 15
C1 C4 (o)
T5
C1 C4
S1 S2 S8 S7
S1 S2 T5 S8 S7
T1 T3
D1
V SCH2 T1 T3
LOAD _ 4V D1
SCH1 + VO SCH2
D2 V LOAD _ 4V
T2 T4 SCH1 + VO
D2
T2 T4
S3 S4 T6 S6 S5
C2 C3 S3 S4 S6 S5
Mode 12 T6
(l) C2 C3
Mode 16
(p)

Fig. 3 Equivalent circuit diagram of all positive modes including mode 0 (a) to (p).

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 2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)
G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

Table III. Design parameters and discharging state. Figures (m) to (p) represent these
Parameters Attributes
modes of operation.
Two DC voltage source 18 V &72 V IV. MODULATION STRATEGY
Capacitors (C1, C2, C3, 4600μF,2700μF,2000μF,1800 μF
The modulation techniques are used for the control and
C4 )
Switching frequency 50Hz regulate the output voltage in power electronic converters.
The figure 4 shows the classification of multilevel inverter
Resistive load Ÿ
modulation techniques. These classifications have been
Inductive load ŸP+
done based on switching frequency above which they
Switches IGBT operate.
a boost converter and modified H bridge act as a polarity
generator. There are 31 modes (15 positive modes, 15
negative modes and zero-mode).All the positive modes are
Multilevel
shown in figure 3. It is to be noted that sky colour represents modulation

the charging states of respective capacitor and red colour

shows the complete path of flow of current.these are low switching
High
switching
frequency
discussed as follows. frequency

Mode 1: In this mode output voltage level is 0V. This is to Nearest

Selective
Multicarrier
be obtained by switching ON T2, T4 T6 or T1,T3, Nearest level
vector
Harmonic
elimination
PWM
SVM

T5.Although S2, S4 in left basic unit and S6, S8 in the right

side of basic unit are ON, but these switches do not play any Phase Shifted Level Shifted 2D Algorithm 3DAlgorithm
role for the generation of zero voltage level.

Mode 2 to Mode 4: The output voltage levels of these modes PD PWM POD-PWM APOD-PWM

are V, 2V and 3V volt respectively. All the voltage levels

are obtained by switching ON the respective semiconductor
switches of left-hand side of basic unit. Although S6 and S8
in the right side of the basic unit are turned ON, these Fig. 4 Classification of multilevel inverter modulation techniques.
switches do not contribute for the generation voltage levels.
Capacitor states of these modes can be seen in Table 1. One of the major drawbacks of high switching frequency
Figure (b), (c) and (d) represent the equivalent circuit scheme is that it injects high switching loss in the
diagram of these modes. transistors. This drawback can be overcome by employing
fundamental switching scheme where devices are turned
Mode 5 to Mode 8: The output voltage levels of these modes ON/OFF only a few times per switching cycle. Selective
are 4V, 5V, 6V and 7V volt. In all these modes, 4V voltage harmonic elimination, space vector control and nearest level
level is achieved by right hand side of basic unit. While V, control are the examples of fundamental switching
2V and 3V voltage level is generated by left basic unit. In frequency modulation scheme [21]. These schemes are most
mode7, capacitor C2 is in charging state while C1 is in suitable for high power applications. Further, the nearest
discharging state. In mode 8, both the capacitor C1 and C2 control techniques are classified into two groups: (1)
are operated in discharged state. Fig (e),(f),(g) and (h) shows Nearest space vector control and (2) Nearest level control.
the equivalent circuit arrangement for these modes. The major limitation of selective harmonic elimination
technique (SHE) is that it takes more time for the solution of
Mode 9 to Mode 12: The output voltage levels of these the system of non-linear trigonometric transcendental
modes are 8V, 9V, 10V and 11V volt. In mode 9 and equations. Therefore, SHE technique is not feasible for
11capacitor C3 is in charging state and Capacitor C4 is in closed-loop real-time applications such as dynamic response
discharging state. While in mode 8 and 12, capacitor C4 is in systems. This disadvantage of SHE technique can be
charging state and Capacitor C3 is in discharging state. In all overcome by the use of nearest control techniques. Although
these modes 8V voltage level is generated by left basic unit nearest space vector control is complex and requires a lot
and 0V, V, 2V and 3V voltage level is produced by right- amount of time for numerical computation. The level
hand side of basic unit. In mode 11, capacitorC1 charges control technique is simpler where normalized value is
upto V voltage level and in mode 12 both the capacitor C1 evaluated using the round-off method (i.e., round{x} is the
and C2 are operated in discharged state. Fig (i) to (l) integer close to x).
represents these modes of operation.
A. Conventional nearest level control
Mode 13 to Mode 16: The output voltage level of these In the conventional scheme, a sinusoidal reference (Vref)
modes are12V, 13V, 14Vand 15V. Both the capacitors C3 signal is compared with various carrier signals (C1 to Cn).
and C4 are operated is in discharging state. Capacitors C1 The conventional method simply rounds {x}, where x is the
and C2 in mode 13 and 14 are operated in not connected reference value and the comparing value is half-integer
state. In mode 15 and 16 capacitor C1 is operated in value 0.5 (i.e. round (1.6) =2 and round (1.4) =1). The DC
discharging state while capacitor C2 is driven in charging loss error between two levels is always maintained to
0.5Vdc in this scheme. The comparison of Vref and carrier

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 2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)
G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

signals are shown in figure 5 and the block diagram of for the representation of the same graph. The waveform of
nearest level prediction is shown in figure 6. output voltage for both resistive and inductive load is same.
However due to inductor current is closed to sinusoidal.
Since ripple in capacitor voltage is taken as 10%, therefore
variation in capacitor voltage (VCI) is seen between 17 to
18V twice in one cycle. In other words, frequency of
capacitor voltage is 100Hz as is shown in figure9. From
FFT analysis, it can be observed that THD in output voltage
of proposed inverter for both R and RL load is 2.72% which
is comparable to other switched capacitor topologies.
Figures 10 and 11shows the THD in output voltage and
current. For inductive load THD in load current is observed
to be 0.90 as shown in figure12.
300
Fig. 5 level generation method of conventional nearest level control
Output Voltage (For R&RL load)
Output Current(For RL load)
200
Output Current (For R load)

Nearest voltage 100

level 0

Output Voltage(V) &Current(A)

Inverter
-100
Vref 1/Vdc round0.5 { } switching Gating pulses
logic -200

-300
Fig. 6 Block diagram of conventional NLC 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time (sec)

For Nlevel number of output voltage levels; Fig.7 Output voltage and current for R and RL load.
Each carrier signals (C1 to Cn) is expressed as follows;
C1C2 C3 C4………… Cn-1 Cn
0.5 1+0.5 2+0.5 3+0.5 (n-2) +0.5 (n-1) +0.5
Where n = (Nlevel -1)/2
The output voltage equation is given as follows;

Vout m *
 Nlevel  1 *Vdc * cos Zt  (1)
2
Where m = modulation index
Vref  max 
m (2)
nVdc
The switching angles for conventional NLC can be
calculated as follows;
݆െ0‫ڄ‬5
ߠ௝ = sinିଵ ൬ ൰
݊
where șj = switching angles Fig.8Output voltage and current for load changing condition.

j = 1,2,3……
 Nlevel  1
2
V. SIMULATION RESULTS
The proposed model is simulated in MATLAB/Simulink.
Rating of capacitance is calculated with the help of the
longest discharging time (LDT) which is based on switching
pattern of the switches. It is to be noted that during the LDT,
capacitor discharges the maximum amount of charge. Load
current and LDT duration decides the amount of discharging
that can take place. Table 3 represents the design parameters
that are used in simulation.
Figures 7 and 8 shows the waveform of output voltage and
Fig.9 Ripple voltage across Capacitor (C1)
output current for constant and variable R and RL load. In
both cases, the current is magnified with the gain of hundred

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 2019 2nd International Conference on Power Energy, Environment and Intelligent Control (PEEIC)
G. L. Bajaj Inst. of Technology and Management Greater Noida, U. P., India, Oct 18-19, 2019

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