8085 MCQs

1. Basic steps of execution of an instruction is

a) fetch → execute → decode b) decode → fetch → execute
b) execute → fetch → decode d) fetch → decode → execute

2. When RET instruction is executed by any subroutine then

a) the top of the stack will be popped out and assigned to the PC.
b) without any operation, the calling program would resume from instruction
immediately following the call instruction.
c) the PC will be incremented after the execution of the instruction.
d) without any operation, the calling program would resume from instruction
immediately following the call instruction and also the PC will be incremented
after the execution of the instruction.

3. Which of the following instruction is not possible in 8085?

a) POP PSW b) POP B c) POP D d) POP 30 H

4. How many T-states are required for execution of OUT 80H instruction?
10
13
16
7
5. How many machine cycles are required for execution of IN 30H instruction
3
4
5
6
6. Length of the instruction POP D is
1 byte
2 byte
3 byte
4 byte
7. While INX B instruction execute,
only carry flag will be affected
all flags will be affected
only carry and zero flags will be affected
no flags will be affected
8. While STC instruction execute,
only carry flag will be affected
all flags will be affected
only carry and zero flags will be affected
no flags will be affected
9. While CMP B instruction execute,
only carry flag will be affected
all flags will be affected
only carry and zero flags will be affected
no flags will be affected
10. Which instruction is required to rotate the content of accumulator one bit right along
with carry?
RLC
RAL
RRC
RAR

11. A microprocessor with a 12-bit address bus will be able to access

1 K bytes
4 K bytes
8 K bytes
10 K bytes
12. The frequency of the driving network connected between pins 1 and 2 of 8085
microprocessor is
twice the desired frequency
equal to the desired frequency
four times the desired frequency
none of the above
13. A high on RESET OUT signifies that
all the registers of the CPU are being reset
all the registers and counters are being reset
all the registers and counters are being reset and this signal can be used to reset external
support chip
processing can begin when this signal goes high
14. READY signal in 8085 is useful when the CPU communicates with
a slow peripheral device
a fast peripheral device
a DMA chip
a PPI
15. PSW stands for
accumulator contents
flag byte
accumulator and flag register contents
none
16. Temporary registers in 8085 are
B and C
D and E
H and L
W and Z

17. Register pair used to indicate memory

B and C
D and E
H and L
W and Z
18. Total numbers of output pins in 8085 microprocessor are
13
27
30
40
19. In a vector interrupt
 the branch address is assigned to a fixed location in memory
the interrupting source supplies the branch information to the processor through an interrupt
vector
the branch address is obtained from a register in the processor
none
20. A sequence of two registers that multiplies the content of DE register pair by two and
stores the result in HL register pair (in 8085 assembly language) is
XCHG & DAD B
XTHL & DAD H
PCHL & DAD D
XCHG & DAD H
21. The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port
address” instruction are
same as the content of A7-A0
irrelevant
all bits reset (i.e. 00H)
all bits set (i.e. FFH)

22. Which one of the following ICs is used to interface keyboard and display?
8251
8279
8259
8253
23. Which one of the following interrupt is only level triggering?
TRAP
RST 7.5
RST 6.5 and RST 5.5
RST 6.5
24. Which one of the following instruction may be used to clear the accumulator content
irrespective of its initial value?
CLR A
ORA A
SUB A
MOV A, 00H
25. The execution of RST n instruction causes the stack pointer to
increment by two
decrement by two
remain unaffected
none of the above
26. The stack is nothing but a set of
reserved ROM address space
reserved RAM address space
reserved I/O address space
none of the above
27. S0 and S1 pins are used for
serial communication
indicating the processor’s status
acknowledging the interrupt
none of the above
28. Pick out the matching pair
READY; RIM
HOLD; DMA
SID; SIM
S0;S1;wait status
29. In order to save accumulator value on the stack, which of the following instruction
may be used
PUSH PSW
PUSH A
PUSH SP
POP PSW
30. A single instruction to clear the lower nibble of accumulator in 8085 language
assembly is
XRI 0FH
ANI F0H
XRI FOH
ANI OFH
31. Maximum number of I/O that can be addressed by the INTEL 8085 is
65536
285
512
256

32. The microprocessor may be made to exit from HALT state by asserting
RESTART
any of the five interrupt lines
READY line
A or B or HOLD line
33. In order to complement the lower nibble of accumulator one can use
ANI 0FH
XRI 0FH
ORI 0FH
CMA
34. The 8085 microprocessor enters into bus idle machine cycle whenever
INTR interrupt is recognized
RST 7.5 is recognized
DAD RP instruction is executed
none of the above
35. During OPCODE fetch the state of S0 and S1 is
00
01
10
11
36. After RESET 8255 will be in
mode 0; all ports are input
mode 0; all ports are output
mode 2
unchanged condition
37. The microprocessor issues ALE during first T-state of
fetch cycle only
memory READ cycle only
 memory WRITE cycle only
every machine cycle
38. The data lines of 8085 microprocessor are multiplexed with
higher order address lines
lower order address lines
status lines
none of the above
39. RST 3 instruction will cause the processor to branch to the location
0000H
0018H
0024H
0028H
40. Which of the following instruction will never affect the zero flag?
DCR R
ORA R
DCX Rp
XRA R
41. Which of the following interrupt is only edge sensitive?
RST 7.5
TRAP
RST6.5
RST 5.5

42. What is the vector address of INTR?

0024H
003CH
0034H
No address is available
43. On receiving an interrupt from an I/O device, the CPU
halts for a predetermined times
hands over the control of address bus and data bus to the interrupting device
branches off to the interrupt service routine immediately
branches off to the interrupt serviceroutine after completion of the current instruction
44. The ALE line of 8085 microprocessor is used to
latch the output of an I/O instruction into an external latch
deactivate the chip-select signal from memory device
latch the 8-bit of address lines AD0-AD7 into an external latch
find the interrupt enable status of the TRAP interrupt
45. The first operation performed in INTEL 8085 microprocessor after RESET is
instruction fetch from 0000H
memory read from the location 0000H
instruction fetch from location 8000H
stack initialization
46. After the execution of CMP A instruction
ZF is set and CY is reset
ZF is set and CY is unchanged
ZF is reset and CY is set
ZF is reset and CY is unchanged
47. The 8085 microprocessor will enter into INA cycle after recognition of
any interrupt
TRAP only
INTR only
RST 7.5,RST 6.5 & RST 5.5 only
48. Which of the following lists the interrupt in decreasing order of priority?
TRAP, RST 5.5, RST 6.5, RST 7.5, INTR
INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
RST 7.5, RST 6.5, RST 5.5, TRAP, INTR
49. The interrupt vector address for TRAP is
0000H
0024H
0018H
002CH
50. In order to reset the carry without affecting the accumulator content one has to use,
SUB A
XRA A
ORA A
CMC
51. EPROMs are preferred for storing programs while developing new microprocessor
based system. Because of their
non-volatile characteristic
erasable and programmable characteristic
random access characteristic
all the above characteristic
52. When any data transfer instruction, for transfer the data from memory to
microprocessor, is executed the condition flags are
not affected
always set
always reset
affected indicating specific conditions
53. Let the content of accumulator and register B be 0000 0100 and 0100 0000
respectively before execution of instruction SUB B. The content of accumulator after
the execution of this instruction will be
00000100
01000000
11000100
010001000
54. Let the content of register C be 00000000 before the instruction DCR C is executed.
The content of register C after the after the execution of this instruction will be
00000000
11111111
00000001
None
55. In 8085 microprocessor based system maximum possible number of input/output
devices can be connected using I/O mapped I/O technique is
64
512
256
65536
 56. Cycle stealing mode of DMA operation involves
DMA controller taking over the address, data and control buses while a block of data is
transferred between memory and I/O device
While the microprocessor is executing a program an interface circuit takes over control of
address, data, control buses when not in use by microprocessor
Data transfer takes place between the I/O device and memory during every alternate clock
cycle
The DMA control waiting for the microprocessor to finish execution of the program and then
takes over the buses
57. Which of the following is not true during the execution of an interrupt service
routine, which does not contain any EI instructions
the microprocessor can be interrupted by a non-mask able interrupt
the microprocessor cannot be interrupted by any interrupt
the microprocessor cannot be interrupted by any mask able interrupt
all interrupts except non-maskable interrupt are disabled
58. The reason for the presence of ALE pin in 8085, but not in 6800 is that
8085 uses I/O mapped I/O, whereas 6800 uses memory mapped I/O
8085 has 5 interrupts lines, whereas 6800 has only two
8085 has multiplexed bus, whereas 6800 does not have
None
59. Which of the following interrupt is both level and edge sensitive?
RST 5.5
INTR
RST 7.5
TRAP
60. The addressing mode in instruction PUSH B is
direct
register
register indirect
immediate
Pg.no.1
61. What is mean by ALU
Arithmetic logic upgrade
Arithmetic logic unsigned
Arithmetic local unsigned
Arithmetic logic unit
62. Which one of the following is not a vectored interrupt?
TRAP.
INTR.
RST 7.5.
RST 3.
63. 8085 microprocessor has how many pins
30.
39.
40.
41.
64. In 8085 microprocessor, the RST6 instruction transfer programme execution to
following location
0030H.
0024H.
 0048H.
0060H.
65. HLT opcode means
load data to accumulator.
store result in memory.
load accumulator with contents of register.
end of program.
66. In 8085 name of the 16 bit registers is
stack pointer.
program counter.
both A and B.
none of these.
67. What is SIM?
Select interrupt mask.
Sorting interrupt mask.
Set interrupt mask.
None of these.
68. The ROM programmed during manufacturing process itself is called
MROM
PROM
EPROM
EEPROM
69. The length of bus cycle in 8086/8088 is four clock cycles, T 1, T2, T3, T4 and an
indeterminate number of wait state clock cycles denoted by T w. The wait states are
always inserted between
T1 & T 2
T2 & T 3
T3 & T 4
T4 & T 1
70. Which one of the following circuits transmits two messages simultaneously in one
direction
Duplex
Diplex
Simplex
Quadruplex
71. The number of output pins in 8085 microprocessors are
40
27
21
19
72. The program counter in a 8085 micro-processor is a 16-bit register, because
It counts 16-bits at a time
There are 16 address lines
It facilitates the user storing 16-bit data temporarily
It has to fetch two 8-bit data at a time
73.A microprocessor is ALU
and control unit on a single chip.
and memory on a single chip.
register unit and I/O device on a single chip.
register unit and control unit on a single chip.
 74.In intel 8085A microprocessor ALE signal is made high to
Enable the data bus to be used as low order address bus
To latch data D0-D7 from data bus
To disable data bus
To achieve all the functions listed above
75. Output of the assembler in machine codes is referred to as
Object program
Source program
Macroinstruction
Symbolic addressing
76. Which of the following statements for intel 8085 is correct?
Program Counter (PC) specifies the address of the instruction last executed
PC specifies the address of the instruction being executed
PC specifies the address of the instruction to be executed
PC specifies the number of instructions executed so far
77.A good assembly language programmer should use general purpose registers rather
than memory in maximum possible ways for data processing. This is because:
Data processing with registers is easier than with memory
Data processing with memory requires more instructions in the program than that with
registers
Of limited set of instructions for data processing with memory
Data processing with registers takes fewer cycles than that with memory
78. Which one of the following is not correct?
Bus is a group of wires
Bootstrap is a technique or device for loading first instruction
An instruction is a set of bits that defines a computer operation
An interrupt signal is required at the start of every program
79. I)A total of about one million bytes can be directly addressed by the 8086
microprocessor II)8086 has thirteen 16-bit registers III)8086 has eight flags IV)Compared to
8086, the 80286 provides a higher degree of memory protection Which one of the statements
given above are correct?
2,3&4
1,3 &4
1,2 & 4
1,2 & 3
80. Processor status word of 8085 microprocessor has five flags?
S, Z, AC, P, CY
S, OV, AC, P, CY
S, Z, OV, P, CY
S, Z, AC, P, OV
81.What are the sets of commands in a program which are not translated into machine
instructions during assembly process, called?
Mnemonics
Directives
Identifiers
Operands
82. The cycle required to fetch and execute an instruction in a 8085 microprocessor is
which one of the following?
Clock cycle
Memory cycle
 Machine cycle
Instruction cycle
83. In an intel 8085A, which is the first machine cycle of an instruction?
An op-code fetch cycle
A memory read cycle
A memory write cycle
An I/O read cycle
84.Both the ALU and control section of CPU employ which special purpose storage
location?
Buffers
Decoders
Accumulators
Registers
85. IN an intel 8085A microprocessor, why is READY signal used?
To indicate to user that the microprocessor is working and is ready for use.
To provide proper WAIT states when the microprocessor is communicating with a slow
peripheral device.
To slow down a fast peripheral device so as to communicate at the microprocessor’s device.
None of the above.
86. Assertion(A): Monostablemultivibrators (IC74121) are used in a microprocessor
based system for frequency measurement. Reason(R): Microprocessor counts the number of
interrupt signals/second or within a specified interval through ISR.
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A.
A is true but R is false.
A is false but R is true.
87. consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry
flag Which one of the above flags is/are present in 8085 microprocessor?
(I) only
(I) & (II)
(II) & (III)
(I) ,(III) & (IV)
88. Consider the following statements: In 8085 microprocessor, data-bus and address
bus are multiplexed in order to I)Increase the speed of microprocessor. II)Reduce the number
of pins. III)Connect more peripheral chips. Which of these statements is/are correct?
(I) only
(II) only
(II) & (III)
(I), (II) & (III)
89.Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional
Both A & R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
A is false but R is true
90. Assertion(A): The frequency of 8085 system is ½ of the crystal frequency.
Reason(R): Microprocessor (8085) requires a two phase clock.
Both A & R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
 A is false but R is true
91.ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
Accumulator, temporary register, arithmetic and logic circuits
Accumulator, arithmetic, logic circuits and five flags
Accumulator, arithmetic and logic circuits
Accumulator, temporary register, arithmetic, logic circuits and five flags
92. Which components are NOT found on chip in a microprocessor but may be found
on chip in a microcontroller?
SRAM & USART
EPROM & PORTS
EPROM, USART & PORTS
SRAM, EPROM & PORTS
93.For the purpose of data processing an efficient assembly language programmer
makes use of the general purpose registers rather than memory. The reason is
a) the set of instructions for data processing with memory is limited
b) data processing becomes easier when register are used
c) more memory related instructions are required
d) data processing with registers takes fewer cycles than that with memory
Pg.no.5
94.The first machine cycle of an instruction is always
A memory read cycle
A fetch cycle
An I/O read cycle
A memory write cycle
95.The output data lines of microprocessor and memories are usually tristated because
More than one device can transmit information over the data bus by enabling only one
device at a time
More than one device can transmit over the data bus at the same time
The data line can be multiplexed for both input and output
It increases the speed of data transfer over the data bus
96.The correct sequence of steps in the instruction cycle of a basic computer is
Fetch, Execute, Decode and Read effective address.
Read effective address, Decode, Fetch and Execute.
Fetch, Decode, Read effective address and, Execute.
Fetch, Read effective address, Decode and Execute.
97.Following is a 16-bit register for 8085 microprocessor
Stack pointer
Accumulator
Register
Register C
98. The register which holds the information about the nature of results of arithmetic
and logic operations is called as
Accumulator
Condition code register
Flag register
Process status register
99.When referring to instruction words, a mnemonic is
a short abbreviation for the operand address.
a short abbreviation for the operation to be performed.
a short abbreviation for the data word stored at the operand address.
 shorthand for machine language.
100. While using a frequency counter for measuring frequency, two modes of
measurement are possible. 1. Period time 2. Frequency mode There is a ‘cross-over
frequency’ below which the period mode is preferred. Assuming the crystal oscillator
frequency to be 4Mhz the crossover frequency is given by
8 Mhz
2 Mhz
2 Khz
1Khz
101.In 8085 microprocessor system with memory mapped I/O, which of the following
is true?
Devices have 8-bit address line
Devices are accessed using IN and OUT instructions
There can be maximum of 256 input devices and 256 output devices
Arithmetic and logic operations can be directly performed with the I/O data
102. Consider the following statements: Arithmetic Logic Unit (ALU) 1.Performs
arithmetic operations 2.Performs comparisons. 3.Communicates with I/O devices 4.Keeps
watch on the system Which of these statements are correct?
1, 2, 3 and 4
1, 2 and 3
1 and 2 only
3 and 4 only
ALU performs arithmetic and logical operations. Note: Comparison is a logical operation.
103. Ready pin of microprocessor is used
to indicate that microprocessor is ready to receive inputs
to indicate that microprocessor is ready to receive outputs
to introduce wait state
to provide direct memory access
Pg.no.6
104.A bus connected between the CPU and main memory that permits transfer of
information between main memory and the CPU is known as
DMA bus
Memory bus
Address bus
Control bus

105.The operations executed by two or more control units are referred as

Micro-operations
Macro-operations
Multi-operations
Bi control-operations
106.Consider the following registers: 1. Accumulator and flag register 2. B and C
register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085
microprocessor can be paired together to make a 16-bit register?
1, 3 and 4
2, 3 and 4
1, 2 and 3
1, 2 and 4
 107. In a microcomputer , the address of memory locations are binary numbers that
identify each memory circuit where a byte is stored. If a microcomputer uses 20-bit address,
then numbers of different memory locations are
20
220
220-1
220 - 1
108. Number of Hex digits needed to represent the 20-bit address of a memory
location are
20
16
5
4
109. Consider the following statements: In 8085 microprocessor, data-bus and address
bus are multiplexed in order to I) Increase the speed of microprocessor. II) Reduce the
number of pins. III) Connect more peripheral chips. Which of these statements is/are correct?
(I) only
(II) only
(II) & (III)
(I),(II) & (III)
110. The field, which is never present in an assembly language statement, is
Opcode
Operand
Continue
Comment
111. Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional
Both A &R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
A is false but R is true
112. Assertion(A): The frequency of 8085 system is ½ of the crystal frequency.
Reason(R): Microprocessor (8085) requires a two phase clock.
Both A &R are true and R is the correct explanation of A
Both A & R are true but R is not the correct explanation of A
A is true but R is false
A is false but R is true
113.ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of
Accumulator, temporary register, arithmetic and logic circuits
Accumulator, arithmetic, logic circuits and five flags
Accumulator, arithmetic and logic circuits
Accumulator, temporary register, arithmetic , logic circuits and five flags
Pg.no.8
114.Consider the following registers: 1. Accumulator and flag register 2. B and C
register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085
microprocessor can be paired together to make a 16-bit register?
1 ,3 and 4
2 ,3 and 4
1, 2 and 3
1, 2 and 4
 115. A bus connected between the CPU and main memory that permits transfer of
information between main memory and the CPU is known as
DMA bus
Memory bus
Address bus
Control bus
116.The operations executed by two or more control units are referred as
Micro-operations
Macro-operations
Multi-operations
Bi control-operations
117. The first microprocessor to include virtual memory in the intel microprocessor
family is
80286
80386
80486
Pentium
118. Assertion(A): Segment override prefix (SOP) is used when a default offset
register is not used with its default base segment register but with a different base register.
Reason(R): The offset registers IP and SP can never be associated with any other segment
registers apart from their respective default segments. Codes:
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A.
A is true but R is false.
A is false but R is true.
119. Assertion(A): Ready signal of microprocessor is used to detect whether a
peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data
transfer operations, the wait states are added by forcing the ready signal low.
Both A & R are true and R is the correct explanation of A.
Both A & R are true but R is not the correct explanation of A .
A is true but R is false.
A is false but R is true.
120. Program counter in a digital computer
Counts the numbers of programs run in the machine.
Counts the number of times a subroutine is called.
Counts the number of times the loops are executed.
Points the memory address of the next instruction to be fetched.
121. During which T-state, contents of OP code from memory are loaded into IR
(Instruction Register)?
T1 OP code fetch
T2 OP code fetch
T3 OP code fetch
T4 OP code fetch
122. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (Undefined) in flag register of an 8085 microprocessor?
1, 3, 5
2, 3, 5
1, 2, 5
1, 3, 4
123. At the beginning of a fetch cycle, the contents of the program counter are
incremented by one.
transferred to address bus.
transferred to memory address register .
transferred to memory data register.
Pg.no.9
124.The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute
Cycle) is
IC = FC - EC
IC = FC + EC
IC = FC + 2EC
EC = IC + FC

125.Each instruction in an assembly language program has the following fields 1.

Label field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct
sequence of these fields?
1, 2, 3 and 4
2, 1, 4 and 3
1, 3, 2 and 4
2, 4, 1 and 3
126. Total no. of instruction for 8085 microprocessor assembly language is
244
245
246
247
127. An 8-bit microprocessor signifies that
8-bit address bus
8-bit controller
8-interrupt lines
8-bit data bus
128. Which one of the following microprocessor is not an 8-bit microprocessor
8085
Z-80
68000
6502
129.Which one of the following microprocessor has 16-bit data bus?
8085
Z-80
68000
6502
130. A microcomputer consists of
a microprocessor
memory
I/O device
All of the above
131. The address bus of any microprocessor is always
Unidirectional
Bi-directional
Either unidirectional or bi-directional
None
132. The data bus of any microprocessor is always
Unidirectional
Bi-directional
Either unidirectional or bi-directional
None
133. The multiplexing of address bus and data buses is used in
all the microprocessors.
depends on the internal architecture.
never multiplexed.
none of these.
134.The multiplexing of address bus and data buses are used in microprocessor
to reduce speed of operation
to increase the no. of pins
to reduce the number of pins
to improve the operation

135. The multiplexing of address bus and data buses in microprocessor

reduces speed of operation
increases the speed of processor
speed of processor does not depend upon multiplexing
None of these
136. The address bus width of a microprocessor which is capable of addressing 64
Kbytes of the memory is
8
12
16
20
137.An 8-bit microprocessor can have ………….. address lines.
8
16
32
cannot be predicted
138. A number of 1-bit registers used in microprocessors to indicate certain
conditions are usually referred to as
shift registers
flags
latches
counters
139. The word size of 8085 microprocessor is
4-bit
8-bit
16-bit
20-bit
140. How many 16-bit special purpose registers are present in 8085 microprocessor?
16
2
8
6
 141. The stack pointer register in a microprocessor
counts the number of programs being executing on the microprocessor
counts the number of instructions being executing on the microprocessor
keeps the address of the next instruction to be fetched
holds the address of the top of the stack

142. Which one of the following statement is false?

A microprocessor has bi-directional address bus
A microprocessor has unidirectional address bus
A microprocessor has bi-directional data bus
A microprocessor has an ALU

143. Identify the non-maskable interrupt from the following

RST 7.5
RST 6.5
RST 5.5
RST 4.5
144. In microprocessor based system DMA refers to
direct memory access for microprocessor
direct memory access for the user
direct memory access for the I/O device
none of the above
145. The interrupt facility is provided in microprocessor to
change the sequence of the instructions being executed
stop the microprocessor when desired
stop the microprocessor when it starts malfunctioning
keep a control on the working of the microprocessor
146. A microprocessor differentiates between op code, data/address at any time by
the sequence in which memory contents are fetched by it
its internal registers
the stack pointer
the program counter
147. A microprocessor without the interrupt facility
is best suited for process control system
is not useful for process control system
cannot be used for DMA operation
cannot be interfaced with any I/O devices
148. In microprocessor based system I/O ports are used to interface
the I/O devices and memory chips
the I/P device only
the O/P devices only
all the I/O devices
149. The stack pointer
resides in RAM
resides in ROM
resides in microprocessor
may be in RAM or ROM
150. In a microprocessor based system the stack is always in
microprocessor
RAM
 ROM
EPROM
152. The instruction set of a microprocessor
is specified by the manufacturers
is specified by the user
cannot be changed by the user
is stored inside the microprocessor
153.The 8085 microprocessor uses a crystal of frequency 6.25 Mhz. The T-state value
is
320ns
640ns
960ns
1280ns

154.When an 8085 microprocessor is reset, the address bus contains

0000H
002CH
0043H
003CH
155. In an 8085 microprocessor based system, the contents of SP are 1000H, PUSH B
instruction will transfer the contents of registers B & C respectively for memory locations
0FFF H and 0FFE H
0FFE H and 0FFF H
1000 H and 0FFF H
1000 H and 1001 H
156. In an 8085 microprocessor based system, the contents of SP are 2000H. POP H
instruction will transfer the contents of memory location
2001H and 2002H to H and L registers respectively
2001H and 2000H to H and L registers respectively
2000H and 1FFFH to H and L registers respectively
2000H and 1999H to H and L registers respectively
157. PUSH B instruction in 8085 microprocessor causes
the contents of register B only to be copied in the stack
the contents of register B & C to be copied in the stack
the contents of registers B & C to be transferred in the stack and and the registers get cleared
registers B & C to be cleared
158. SUB A instruction in 8085
reset carry and sign flags
reset zero and parity flags
sets zero and sign flags
sets zero and carry flags
159. In 8085 microprocessor , let the accumulator contains the value 0AH and register
C contains the value 05H. After CMP C instruction is executed, the
zero and carry flags will be set
zero and carry flags will be reset
zero flag will be set and carry flag will be reset
zero flag will be reset and carry flag will be set
160. Which of the data transfer is not possible in microprocessor
memory to accumulator
accumulator to memory
 memory to memory
I/O device to accumulator
161. In 8085 microprocessor , in response to RST 7.5 interrupts the execution is
transferred to memory location
0000H
002CH
0034H
003CH
162. In 8085 microprocessor which one of the following statement is wrong
there is a pin available for serial input
there is a pin available for serial output
serial I/O is possible through SIM and RIM instruction
serial I/O is not possible
163.In which T-state does the CPU sends the address to memory or I/O and the
ALE signal for demultiplexing
(A) T1. (B) T2.

(C) T3. (D) T4.

164.Number of the times the instruction sequence below will loop before
coming out of loop is
MOV AL,
00h A1: INC
AL JNZ A1
(A) 00 (B) 01
(C) 255 (D) 256

165.What will be the contents of register AL after the following has

been executed MOV BL, 8C
MOV AL,
7E ADD AL,
BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset

166.These are two ways in which a microprocessor can come out of Halt state.
(A)When hold line is a logical 1.
(B)When interrupt occurs and the interrupt system has been enabled.
(C)When both (A) and (B) are true.
(D)When either (A) or (B) are true.

167.Which of the following statement is true?

(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine
cycle is made up of number of states.
(D)None of the above
168.The no. of address lines required to address a memory of size 32 K is
(A) 15 lines (B) 16 lines
(C) 18 lines (D) 14 lines