18-Bit, 2 Msps, Μmodule Data Acquisition Solution: Adaq4003
18-Bit, 2 Msps, Μmodule Data Acquisition Solution: Adaq4003
18-Bit, 2 Msps, Μmodule Data Acquisition Solution: Adaq4003
Figure 1.
TABLE OF CONTENTS
Features .............................................................................................. 1 Analog Inputs ............................................................................. 21
Applications ...................................................................................... 1 Ease of Drive Features ............................................................... 21
Functional Block Diagram .............................................................. 1 Voltage Reference Input............................................................ 23
General Description ......................................................................... 1 Power Supply (Power Tree) ...................................................... 23
Revision History ............................................................................... 2 Digital Interface .......................................................................... 23
Specifications .................................................................................... 3 Register Read and Write Functionality ................................... 24
Timing Specifications .................................................................. 6 Status Word ................................................................................ 26
Absolute Maximum Ratings ........................................................... 8 CS Mode, 3-Wire Turbo Mode ................................................ 27
Thermal Resistance ...................................................................... 8 CS Mode, 3-Wire Without Busy Indicator............................. 28
Electrostatic Discharge (ESD) Ratings ...................................... 8 CS Mode, 3-Wire with Busy Indicator .................................... 29
ESD Caution.................................................................................. 8 CS Mode, 4-Wire Turbo Mode ................................................ 30
Pin Configuration and Function Descriptions ............................ 9 CS Mode, 4-Wire Without Busy Indicator............................. 31
Typical Performance Characteristics ........................................... 11
CS Mode, 4-Wire with Busy Indicator .................................... 32
Terminology .................................................................................... 17
Daisy-Chain Mode ..................................................................... 33
Theory of Operation ...................................................................... 18
Layout Guidelines ...................................................................... 34
Circuit Information ................................................................... 18
Outline Dimensions ....................................................................... 35
Transfer Functions ..................................................................... 18
Ordering Guide .......................................................................... 35
Applications Information.............................................................. 19
Typical Application Diagrams.................................................. 19
REVISION HISTORY
9/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 35
Data Sheet ADAQ4003
SPECIFICATIONS
VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.7 V to 5.5 V, reference voltage (VREF) = 5 V, sampling frequency (fS) =
2 MSPS, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, and turbo mode enabled, unless otherwise
noted. ADC driver configured in single-ended to differential configuration and fast mode, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 18 Bit
ANALOG INPUTS IN+, IN−, R1K1+, R1K1−, R1K+, and R1K−
Input Impedance (ZIN) Single-ended to differential configuration
G = 0.454, input voltage (VIN) = 22 V p-p 1.3 kΩ
G = 0.909, VIN = 11 V p-p 1.44 kΩ
G = 1, VIN = 10 V p-p 1.33 kΩ
G = 1.9, VIN = 5.2 V p-p 778 Ω
Fully differential configuration
G = 0.454 and G = 0.909, 1.1 kΩ
VIN = 22 V p-p and 11 V p-p
G = 1, VIN = 10 V p-p 1 kΩ
G = 1.9, VIN = 5.2 V p-p 523 Ω
Differential Input Voltage Ranges1 G = 0.454, VIN = 22 V p-p −2.2 × VREF +2.2 × VREF V
G = 0.909, VIN = 11 V p-p −1.1 × VREF +1.1 × VREF V
G = 1, VIN = 10 V p-p −VREF +VREF V
G = 1.9, VIN = 5.2 V p-p −0.526 × VREF +0.526 × VREF V
Input Capacitance IN+ and IN− 12 pF
THROUGHPUT
Complete Cycle 500 ns
Conversion Time 290 320 ns
Acquisition Phase2 290 ns
Throughput Rate3 0 2 MSPS
Transient Response4 40 μs
DC ACCURACY Single-ended to differential configuration
No Missing Codes 18 Bits
Integral Linearity Error (INL) All gains, VS− = −1 V −8 ±3 +8 ppm
−2.1 ±0.8 +2.1 LSB5
Differential Linearity Error (DNL) All gains, VS− = −1 V −1 ±0.4 +1 LSB5
−3.8 ±2.66 +3.8 ppm
Transition Noise All gains 0.93 LSB
Gain Error All gains −0.05 ±0.005 +0.05 %FS
Gain Error Drift All gains −3 ±0.5 +3 ppm/°C
Offset Error G = 0.454 −1 ±0.1 +1 mV
G = 0.909, G = 1 −0.9 ±0.06 +0.9 mV
G = 1.9 −1.5 ±0.01 +1.5 mV
Offset Error Drift G = 0.454 −8 +0.7 +8 ppm/°C
G = 0.909 and G = 1 −10 +1.6 +10 ppm/°C
G = 1.9 −15 +2.6 +15 ppm/°C
Common-Mode Rejection Ratio (CMRR) Fully differential configuration, all gains 90 dB
Power Supply Rejection Ratio (PSRR)
Positive VDD = 1.71 V to 1.89 V 72 dB
VS+ = 5.225 V to 5.775 V, VS− = 0 V 110 dB
Negative VS+ = +5.5 V, VS− = 0 V to −0.5 V 107 dB
1/f Noise6 Bandwidth = 0.1 Hz to 10 Hz 38 μV p-p
Input Current Noise Input frequency (fIN) = 100 kHz 1 pA/√Hz
Rev. 0 | Page 3 of 35
ADAQ4003 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
AC ACCURACY Single-ended to differential and fully
differential configuration
Dynamic Range All gains, −60 dBFS 94.5 dB
G = 0.454 100 dB
G = 0.909 and G = 1 97.5 dB
G = 1.9 98.5 dB
Oversampled Dynamic Range Oversampling ratio (OSR) = 2, all gains 103 dB
OSR = 256, all gains 122 dB
Total RMS Noise All gains 35.35 µV rms
Signal-to-Noise Ratio (SNR) fIN = 1 kHz, −0.5 dBFS 94.2 dB
G = 0.454 99.5 dB
G = 0.909 and G =1 97 dB
G = 1.9 98 dB
fIN = 100 kHz, G = 0.909 98 dB
fIN = 400 kHz, G = 0.909 92 dB
Low power mode enabled, G = 0.909 96 dB
VS+ = 3.3 V, VS− = 0 V, 92 dB
VREF = 2.5 V, G = 0.909
Signal-to-Noise + Distortion (SINAD) fIN = 1 kHz, −0.5 dBFS 94 dB
G = 0.454 99 dB
G = 0.909 and G =1 96.5 dB
G = 1.9 97.5 dB
fIN = 100 kHz, G = 0.909 97.5 dB
fIN = 400 kHz, G = 0.909 91.5 dB
Low power mode enabled, G = 0.909 95.5 dB
VS+ = 3.3 V, VS− = 0 V, 91.5 dB
VREF = 2.5 V, G = 0.909
Total Harmonic Distortion (THD) fIN = 1 kHz, −0.5 dBFS, all gains −120 dB
fIN = 100 kHz, G = 0.909 −100 dB
fIN = 400 kHz, G = 0.909 −95 dB
Low power mode enabled, G = 0.909 −110 dB
VS+ = 3.3 V, VS− = 0 V, −118 dB
VREF = 2.5 V, G = 0.909
Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz, −0.5 dBFS, all gains 122 dB
fIN = 100 kHz, G = 0.909 101 dB
fIN = 400 kHz, G = 0.909 95 dB
Low power mode enabled, G = 0.909 110 dB
VS+ = 3.3 V, VS− = 0 V, 118 dB
VREF = 2.5 V, G = 0.909
−3 dB Input Bandwidth 4.4 MHz
Recovery Time
Input Overdrive All gains 280 ns
Output Overdrive All gains 120 ns
Clamp All gains 100 ns
Aperture Delay 1 ns
Aperture Jitter 1 ps rms
REFERENCE
VREF Range Buffer enabled 2.4 5.1 or VS+ − 0.08 V
Input Current (IREF) Buffer enabled 60 µA
REF_OUT Current (IREF_OUT) Buffer disabled, 2 MSPS, VREF = 5 V 1.27 mA
Rev. 0 | Page 4 of 35
Data Sheet ADAQ4003
Parameter Test Conditions/Comments Min Typ Max Unit
VCMO
VCMO Voltage (VVCMO) 7 VREF/2 − 0.003 VREF/2 VREF/2 + 0.003 V
Output Impedance 5 kΩ
DIGITAL INPUTS SDI, SCK, and CNV
Logic Levels
Input Low Voltage (VIL) VIO > 2.7 V −0.3 +0.3 × VIO V
VIO ≤ 2.7 V −0.3 +0.2 × VIO V
Input High Voltage (VIH) VIO > 2.7 V 0.7 × VIO VIO + 0.3 V
VIO ≤ 2.7 V 0.8 × VIO VIO + 0.3 V
Input Low Current (IIL) −1 +1 µA
Input High Current (IIH) −1 +1 µA
Input Pin Capacitance 6 pF
DIGITAL OUTPUTS 8
Data Format Twos complement
Output Low Voltage (VOL) Sink current (ISINK) = +500 µA 0.4 V
Output High Voltage (VOH) Source current (ISOURCE) = −500 µA VIO − 0.3 V
POWER-DOWN AND MODE SIGNALING
ADC Driver and Reference Buffer
PD_AMP, PD_REF, and MODE Voltage
Low Powered down, low power mode <1 V
High Enabled, fast mode >1.7 V
POWER REQUIREMENTS
VDD 1.71 1.8 1.89 V
VS+ 3 5.5 VS− + 10 V
VS− VS+ − 10 0 0.1 V
VIO 1.7 5.5 V
Total Standby Current 9, 10 Static, all devices enabled 11 14 mA
Power-Down Current ADC driver, reference buffer disabled 100 250 nA
Power Dissipation VDD = VIO = 1.8 V, VS+ = 5.5 V, VS− = 0 V
VS+ 41.5 51.5 mW
VDD 9.5 12 mW
VIO 0.6 0.7 mW
Total 51.6 64.2 mW
VDD = VIO = 1.8 V, VS+ = 5 V, VS− = 0 V,
high-Z mode enabled
VS+ 44 53 mW
VDD 12.8 16.5 mW
VIO 0.6 0.7 mW
Total 57.4 70.2 mW
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +125 °C
1
VIN must be within the allowed input common-mode range as per Figure 35, Figure 36, and Figure 37 and is dependent on the VS+ and VS− supply rails used.
2
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
3
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 5 for the maximum achievable
throughput for different modes of operation.
4
Transient response is the time required for the ADAQ4003 to acquire a full-scale input step to ±1 LSB accuracy.
5
The weight of the LSB, referred to input, changes depending on the input voltage range. See Table 10 for the LSB size.
6
See the 1/f noise plot in Figure 28.
7
The VCMO voltage can be used for other circuitry, but it should be driven with a buffer to ensure the VCMO voltage remains stable as per the specified range.
8
There is no pipeline delay. Conversion results are available immediately after a conversion is completed.
9
With all digital inputs forced to VIO or GND as required.
10
The total standby current during the acquisition phase.
Rev. 0 | Page 5 of 35
ADAQ4003 Data Sheet
TIMING SPECIFICATIONS
VDD = 1.8 V ± 5%, VS+ = 5.5 V ± 5%, VS− = 0 V, VIO = 1.71 V to 5.5V, VREF = 5 V, fS = 2 MSPS, all specifications TMIN to TMAX, high-Z
mode disabled, span compression disabled, and turbo mode enabled, unless otherwise noted.
Rev. 0 | Page 6 of 35
Data Sheet ADAQ4003
Table 4. Register Read and Write Timing
Parameter Symbol Min Typ Max Unit
READ AND WRITE OPERATION
CNV Pulse Width 1 tCNVH 10 ns
SCK Period tSCK
VIO > 2.7 V 9.8 ns
VIO > 1.7 V 12.3 ns
SCK Low Time tSCKL 3 ns
SCK High Time tSCKH 3 ns
READ OPERATION
CNV Low to SDO D17 MSB Valid Delay tEN
VIO > 2.7 V 10 ns
VIO > 1.7 V 13 ns
SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO > 2.7 V 7.5 ns
VIO > 1.7 V 10.5 ns
CNV Rising Edge to SDO High Impedance tDIS 20 ns
WRITE OPERATION
SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns
SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns
CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns
CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns
1
For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1
X% VIO1
tDELAY tDELAY
VIH2 VIH2
VIL2 VIL2
1FORVIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
21657-002
Rev. 0 | Page 7 of 35
ADAQ4003 Data Sheet
Rev. 0 | Page 8 of 35
Data Sheet ADAQ4003
A1 BALL
CORNER D IN− IN+ DNC DNC DNC PD_REF SCK
1 2 3 4 5 6 7
A
E R1K1+ R1K1+ MODE VS+ ADCIN+ GND SDO
B
C
D F R1K+ R1K+ OUT– VS+ DNC DNC CNV
F
OUT− ADCIN−
21657-004
G GND VCMO VS+ VS+ GND
21657-003
Rev. 0 | Page 9 of 35
ADAQ4003 Data Sheet
Ball No. Mnemonic Type 1 Description
D1 IN− AI Negative Input of the Fully Differential ADC Driver.
D2 IN+ AI Positive Input of the Fully Differential ADC Driver.
D6 PD_REF DI Power-Down Reference Buffer. Active low. Connect the PD_REF pin to GND to power down
the reference buffer. Otherwise, connect the PD_REF pin to logic high.
D7 SCK DI Serial Data Clock Input. When the device is selected, the conversion result is shifted out by
this clock.
E1, E2 R1K1+ AI 1.1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver.
E3 MODE DI Power Mode for the Fully Differential ADC Driver. Full performance when the MODE pin is
high, and low power mode when the MODE pin is low.
E4, F4, G4, G5 VS+ P Fully Differential ADC Driver and Reference Buffer Positive Supply.
E5 ADCIN+ AO Positive Input to the ADC. Extra capacitance can be added on the ADCIN+ pin to reduce the
RC filter bandwidth.
E7 SDO DO Serial Data Output. The conversion result is output on the SDO pin. SDO synchronizes to SCK.
F1, F2 R1K+ AI 1 kΩ Resistor Input to Positive Input of the Fully Differential ADC Driver.
F3, G3 OUT− AO Negative Output of the Fully Differential ADC Driver.
F7 CNV DI Convert Input. This input has multiple functions. On its leading edge, CNV initiates the
conversions and selects the interface mode of the device: daisy-chain mode or CS mode.
In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read
when CNV is high.
G2 VCMO AO Fully Differential ADC Driver Output Common-Mode Voltage. Nominally, VREF/2.
G6 ADCIN− AO Negative Input to the ADC. Extra capacitance can be added on the ADCIN− pin to reduce
the RC filter bandwidth.
1
P is power, AO is analog output, AI is analog input, N/A is not applicable, DI is digital input, and DO is digital output.
Rev. 0 | Page 10 of 35
Data Sheet ADAQ4003
0.4 0.2
0.2 0.1
DNL (LSB)
INL (LSB)
0 0
–0.2 –0.1
–0.4 –0.2
–0.6 –0.3
–0.8 –0.4
–1.0 –0.5
21657-108
21657-105
0 32768 65536 98304 131072 163840 196608 229376 262144 0 32768 65536 98304 131072 163840 196608 229376 262144
CODE CODE
Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V, G = 0.454
160 0 400000
VREF = 5V
VREF = 2.5V
140 350000
–50
120
300000
OPEN-LOOP GAIN (dB)
100
–100
PHASE (Degrees)
250000
80
COUNTS
60 –150 200000
40 150000
–200
20
100000
0
–250
50000
–20
–300 0
21657-005
–40
21657-007
1 10 100 1k 10k 100k 1M 10M 100M 1G –23 –21 –19 –17 –15 –13 –11 –9 –7 –5 –3
FREQUENCY (Hz) CODES
Figure 6. ADC Driver Open-Loop Gain and Phase vs. Frequency Figure 9. Histogram of a DC Input at the Code Center, VREF = 2.5 V and VREF = 5 V
2.9 400000
VREF = 5V
2.7 VREF = 2.5V
350000
2.5
2.3
TRANSITION NOISE (LSB)
300000
G = 0.454, VREF = 5V
2.1 G = 0.454, VREF = 2.5V
G = 0.909, VREF = 5V 250000
1.9
COUNTS
21657-006
–40 –20 0 20 40 60 80 100 120 –23 –21 –19 –17 –15 –13 –11 –9 –7 –5 –3
TEMPERATURE (°C) CODES
Figure 7. Transition Noise vs. Temperature for G = 0.454, G = 0.909, G = 1, and Figure 10. Histogram of a DC Input at the Code Transition, VREF = 2.5 V and
G = 1.9 and VREF = 5 V and VREF = 2.5 V VREF = 5 V
Rev. 0 | Page 11 of 35
ADAQ4003 Data Sheet
0 0
VREF = 5V VREF = 2.5V
SNR = 98.2dB SNR = 93.1dB
–20 THD = –123.1dB –20 THD = –112.1dB
SINAD = 98.1dB SINAD = 92.9dB
–40 –40
AMPLITUDE (dB)
–60 –60
AMPLITUDE (dB)
–80 –80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
21657-116
21657-112
100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 11. 1 kHz, −0.5 dBFS Input Tone Fast Fourier Transform (FFT), Figure 14. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1,
Wide View, G = 1,VREF = 5 V, Differential VREF = 2.5 V, Single-Ended
0 0
VREF = 5V VREF = 5V
SNR = 98.1dB SNR = 97.5dB
–20 –20 THD = –117.9dB
THD = –117.9dB
SINAD = 98.0dB SINAD= 97.4dB
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
21657-117
21657-113
Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential,
VREF = 5 V, Single-Ended G = 0.909, VREF = 5 V, Low Power Mode
0 0
VREF = 2.5V VREF = 5V
SNR = 93.3dB SNR = 95.3dB
–20 –20 THD = –105.3dB
THD = –117.8dB
SINAD = 93.1dB SINAD = 94.9dB
–40 –40
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–80 –80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
21657-118
21657-115
Figure 13. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 2.5 V, Figure 16. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View, G = 1, VREF = 5 V
Differential
Rev. 0 | Page 12 of 35
Data Sheet ADAQ4003
0 0
VREF = 2.5V VREF = 5V
SNR = 92.4dB SNR = 88.3dB
–20 –20
THD = –113.7dB THD = –87.6dB
SINAD = 92.2dB SINAD = 85.7dB
–40 –40
AMPLITUDE (dB)
–60 –60
AMPLITUDE (dB)
–80 –80
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
21657-150
21657-120
100 1k 10k 100k 1M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 17. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, Differential, Figure 20. 400 kHz, −0.5 dBFS Input Tone FFT, G = 1, Wide View, VREF = 5 V
G = 0.909, VREF = 2.5 V, Low Power Mode
98 98
15.95 16.0
96
97
15.75 15.5
SNR, SINAD (dB)
94
ENOB (Bits)
96
15.55 92 15.0
95
G = 0.454 SNR 90
G = 0.454 SINAD 15.35 14.5
94 G = 0.454 ENOB
G = 0.909 SNR G = 1.9 SNR
88 G = 1.9 SINAD
G = 0.909 SINAD
G = 0.909 ENOB 15.15 G = 1.9 ENOB 14.0
93 G = 1.9 SNR G = 0.909 SNR
86
G = 1.9 SINAD G = 0.909 SINAD
G = 1.9 ENOB G = 0.909 ENOB
92 14.95 84 13.5
21657-039
21657-123
2.5 3.0 3.5 4.0 4.5 5.0 1k 10k 100k 1M
REFERENCE VOLTAGE (V) FREQUENCY (Hz)
Figure 18. SNR, SINAD, and Effective Number of Bits (ENOB) vs. Reference Figure 21. SNR, SINAD, and ENOB vs. Frequency for G = 1.9 and G = 0.909,
Voltage for G = 0.454, G = 0.909, and G = 1.9, fIN = 1 kHz VREF = 5 V
ENOB (Bits)
98.2
THD (dB)
16.00 –118
98.0
15.95 –120
97.8
97.4
15.85 –124
97.2 G = 1.9 SNR G = 0.909 SNR G = 0.454 SNR
G = 1.9 SINAD G = 0.909 SINAD G = 0.454 SINAD
G = 1.9 ENOB G = 0.909 ENOB G = 0.454 ENOB –126
15.80
21657-043
97.0
21657-040
–40 –20 0 20 40 60 80 100 120 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C) REFERENCE VOLTAGE (V)
Figure 19. SNR, SINAD, and ENOB vs. Temperature, Figure 22. THD vs. Reference Voltage, G = 0.454, G = 0.909, and G = 1.9,
G =1.9, G = 0.909, and G = 0.454, fIN = 1 kHz fIN = 1 kHz
Rev. 0 | Page 13 of 35
ADAQ4003 Data Sheet
–112 126
G = 0.454 G = 0.454
G = 0.909 G = 0.909
G = 1.9 G = 1.9
–114
124
–116
122
SFDR (dB)
THD (dB)
–118
120
–120
118
–122
116
–124
–126 114
21657-045
21657-041
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 23. THD vs. Temperature for G = 0.454, G = 0.909, and G = 1.9, Figure 26. SFDR vs. Temperature for G = 0.454, G = 0.909, and G = 1.9,
fIN = 1 kHz fIN = 1kHz
G = 1.9 SFDR 0
–110 G = 1.9 THD 105
G = 0.909 THD –0.05
–115 100
–0.10
–120 95
–0.15
–125 90 –0.20
–130 85 –0.25
21657-130
21657-126
Figure 24. THD and SFDR vs. Frequency for G = 0.909 and G = 1.9, VREF = 5 V Figure 27. Offset Error vs. Temperature for G = 0.454, G = 0.909, G = 1, and
G = 1.9
126 39.5
124
39.0
ADC OUTPUT VOLTAGE (µV)
122
38.5
SFDR (dB)
120
38.0
118
37.5
116
G = 0.454
G = 0.909
G = 1.9
114 37.0
21657-044
21657-048
Figure 25. SFDR vs. Reference Voltage for G = 0.454, G = 0.909, and G = 1.9, Figure 28. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 100 kSPS,
fIN = 1 kHz 250 Samples Averaged per Reading
Rev. 0 | Page 14 of 35
Data Sheet ADAQ4003
10 20
VDD
9 18 VIO
REF
8 TOTAL POWER
16
OPEARTING CURRENT (mA)
7 14
POWER (mW)
6 12
5 10
4 8
VDD, HIGH-Z DISABLED
3 VDD, HIGH-Z ENABLED 6
VIO, HIGH-Z DISABLED
VIO, HIGH-Z ENABLED
2 VS+, HIGH-Z DISABLED 4
VS+, HIGH-Z ENABLED
1 2
0 0
21657-131
21657-137
–40 –5 25 85 125 100 1k 10k 100k 1M
TEMPERATURE (°C) THROUGHPUT (Hz)
Figure 29. Operating Current vs. Temperature, 2 MSPS Figure 32. Power vs. Throughput
30 130
25
POSITIVE FULL-SCALE ERROR, G = 0.454 120
20 POSITIVE FULL-SCALE ERROR, G = 0.909
POSITIVE FULL-SCALE ERROR, G = 1.9
NEGATIVE FULL-SCALE ERROR, G = 0.454
15 NEGATIVE FULL-SCALE ERROR, G = 0.909 110
NEGATIVE FULL-SCALE ERROR, G = 1.9
GAIN ERROR (LSB)
10
100
VS+
PSRR (dB)
5
VS–
0 90 VDD
–5
80
–10
–15 70
–20
60
–25
–30 50
21657-233
21657-135
–40 –5 25 85 125 100 1k 10k 100k 1M
TEMPERATURE (°C) FREQUENCY (Hz)
Figure 30. Gain Error vs. Temperature for Positive Full-Scale Error and Figure 33. PSRR vs. Frequency
Negative Full-Scale Error and for G = 0.454, G = 0.909, and G = 1.9
135 120
G = 0.454, DYNAMIC RANGE G = 0.454
G = 0.454, fIN = 1kHz G = 0.909
130 G = 0.454, fIN = 10kHz G = 1.9
110
G = 0.909, DYNAMIC RANGE
DYNAMIC RANGE AND SNR (dB)
G
115
80
110
70
105
100 60
95 50
90
21657-133
40
21657-136
Figure 31. Dynamic Range and SNR vs. Oversampling Rate for G = 0.454, Figure 34. CMRR vs. Frequency for G = 0.454, G = 0.909, and G = 1.9
G = 0.909, and G = 1.9, and for Input Frequencies, 2 MSPS
Rev. 0 | Page 15 of 35
ADAQ4003 Data Sheet
12 10
–4.55, +10 +4.55, +10
8 –4.77, +5.93 +4.77, +5.93
9 –4.55, +10 +4.55, +10
INPUT COMMON-MODE VOLTAGE (V)
21657-042
21657-047
–5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
FDA OUTPUT VOLTAGE (V) FDA OUTPUT VOLTAGE (V)
Figure 35. Input Common-Mode Voltage vs. FDA Output Voltage, G = 0.454, Figure 37. Input Common-Mode Voltage vs. FDA Output Voltage, G = 1.9,
Differential Input Differential Input
9 5
–4.55, +7.15 +4.55, +7.15
–4.55, +7.15 +4.55, +7.15
6
INPUT COMMON-MODE VOLTAGE (V)
0
–4.55, +6 +4.55, +6
3
–5
0
GAIN (dB)
21657-134
21657-046
Figure 36. Input Common-Mode Voltage vs. FDA Output Voltage, Figure 38. Small Signal Frequency Response and 0.1 dB Flatness for
G = 0.909, Differential Input G = 1.9, G = 0.454, and G = 0.909 at Full Power and Low Power
Rev. 0 | Page 16 of 35
Data Sheet ADAQ4003
TERMINOLOGY
Integral Nonlinearity (INL) Error Dynamic Range
INL error is the deviation of each individual code from a line Dynamic range is the ratio of the rms value of the full scale to
drawn from negative full scale through positive full scale. The the total rms noise measured. The value for dynamic range is
point used as negative full scale occurs ½ LSB before the first expressed in decibels. Dynamic range is measured with a signal
code transition. Positive full scale is defined as a level 1½ LSB at −60 dBFS so that the range includes all noise sources and
beyond the last code transition. The deviation is measured from DNL artifacts.
the middle of each code to the true straight line (see Figure 39). Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL) Error SNR is the ratio of the rms value of the actual input signal to
In an ideal ADC, code transitions are 1 LSB apart. DNL is the the rms sum of all other spectral components below the
maximum deviation from this ideal value. DNL error is often Nyquist frequency, excluding harmonics and dc. The value for
specified in terms of resolution for which no missing codes are SNR is expressed in decibels.
guaranteed. Signal-to-Noise-and-Distortion Ratio (SINAD)
Offset Error SINAD is the ratio of the rms value of the actual input signal to
Offset error is the difference between the ideal midscale voltage, the rms sum of all other spectral components that are less than
0 V, and the actual voltage producing the midscale output code, the Nyquist frequency, including harmonics but excluding dc.
0 LSB. The value of SINAD is expressed in decibels.
Gain Error Aperture Delay
The first transition (from 100 … 00 to 100 … 01) occurs at Aperture delay is the measure of the acquisition performance
a level ½ LSB above nominal negative full scale. The last and is the time between the rising edge of the CNV input and
transition (from 011 … 10 to 011 … 11) occurs for an analog when the input signal is held for a conversion.
voltage 1½ LSB below the nominal full scale. The gain error is Transient Response
the deviation of the difference between the actual level of the last Transient response is the time required for the ADC to acquire
transition and the actual level of the first transition from the a full-scale input step to ±1 LSB accuracy.
difference between the ideal levels.
Common-Mode Rejection Ratio (CMRR)
Spurious-Free Dynamic Range (SFDR) CMRR is the ratio of the power in the ADC output at the
SFDR is the difference, in decibels (dB), between the rms frequency, f, to the power of a 200 mV p-p sine wave applied to
amplitude of the input signal and the peak spurious signal, the input common-mode voltage of f.
including harmonics.
CMRR (dB) = 10log(PADC_IN/PADC_OUT)
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave where:
input. ENOB is related to SINAD as follows: PADC_IN is the common-mode power at f applied to the inputs.
PADC_OUT is the power at f in the ADC output.
ENOB = (SINADdB − 1.76)/6.02
Power Supply Rejection Ratio (PSRR)
ENOB is expressed in bits. PSRR is the ratio of the power in the ADC output at f to the
Total Harmonic Distortion (THD) power of a 200 mV p-p sine wave applied to the ADC VDD
THD is the ratio of the rms sum of the first five harmonic supply of f.
components to the rms value of a full-scale input signal and is PSRR (dB) = 10 log(PVDD_IN/PADC_OUT)
expressed in decibels.
where:
PVDD_IN is the power at f at the VDD pin.
PADC_OUT is the power at f in the ADC output.
Rev. 0 | Page 17 of 35
ADAQ4003 Data Sheet
THEORY OF OPERATION
CIRCUIT INFORMATION The fast conversion time of the ADAQ4003, along with turbo
mode, allows low clock rates to read back conversions, even when
The ADAQ4003 SiP is a fast, precision DAQ signal chain that
running at its maximum throughput rate. Note that for the
uses a SAR architecture. As shown in Figure 1, the ADAQ4003
ADAQ4003, the full throughput rate of 2 MSPS can be achieved
μModule DAQ solution contains a high bandwidth, fully
only with turbo mode enabled. Because the ADAQ4003 has on-
differential, ADC driver, a low noise reference buffer, and an
board conversion clocks, the serial clock (SCK) is not required
18-bit SAR ADC, along with the critical precision passive
for the conversion process.
components required to achieve optimized performance with
pin-selectable gain options of 0.454, 0.909, 1, or 1.9. All active The ADAQ4003 interfaces to any 1.8 V to 5 V digital logic
components including iPassives thin film resistors with ±0.005% family. The device is housed in a 7 mm × 7 mm, 0.80 mm pitch
matching in the circuit are designed by Analog Devices, which 49-ball CSP_BGA that provides significant space savings and
are factory calibrated to achieve a high degree of specified accuracy allows flexible configurations.
and minimize temperature dependent error sources. TRANSFER FUNCTIONS
The ADAQ4003 is capable of converting 2,000,000 samples per The ideal transfer characteristics for the ADAQ4003 are shown
second (2 MSPS). The ADAQ4003 has a valid first conversion in Figure 39 and Table 10.
after being powered down for long periods that can reduce
21657-012
resistors can be pin strapped to achieve different gains for the –FSR + 0.5 LSB +FSR – 1.5 LSB
ANALOG INPUT
fully differential ADC driver, which allows the user to match
Figure 39. ADC Ideal Transfer Function (FSR Is Full-Scale Range)
the input signal range. The fully ADC driver can be used in a
differential manner or to perform a single-ended to differential
conversion for a single-ended input.
Rev. 0 | Page 18 of 35
Data Sheet ADAQ4003
APPLICATIONS INFORMATION
TYPICAL APPLICATION DIAGRAMS
Figure 40 through Figure 47 show the recommended connection diagrams for the ADAQ4003 when applying a single-ended and
differential input signal for four different gain options with respect to ground reference.
VS+ = 5.5V REF = 5V REF_OUT VDD = 1.8V
0.1µF
G = 0.454
PD_REF
10µF 2.2µF
+11V R1K1– 10kΩ
VCMO
OUT+ 10kΩ
R1K– 1kΩ VIO
0.1µF
R1K1– 1kΩ
0V 1nF
1.1kΩ 33Ω SDI
IN–
VCMO FDA ADC SCK
IN+ SDO
R1K1+ 1.1kΩ 33Ω 1nF CNV
–11V 1kΩ
R1K+
1kΩ
0.1µF
ADAQ4003
OUT–
21657-013
VCMO PD_AMP VS– MODE GND ADCIN+ ADCIN–
0.1µF
G = 0.909
PD_REF
10µF 2.2µF
10kΩ
VCMO
R1K1– 10kΩ
+5.5V OUT+ VIO
R1K– 1kΩ 0.1µF
0V R1K1– 1kΩ
1nF
1.1kΩ 33Ω SDI
IN–
–5.5V VCMO SCK
FDA ADC
IN+ SDO
R1K1+ 1.1kΩ 33Ω 1nF CNV
1kΩ
R1K+
1kΩ
0.1µF
ADAQ4003
OUT–
21657-014
0.1µF
G=1
PD_REF
10µF 2.2µF
10kΩ
R1K– VCMO
+5V 10kΩ
OUT+ VIO
R1K– 1kΩ 0.1µF
0V
R1K1– 1kΩ
1nF
–5V 1.1kΩ 33Ω SDI
IN–
VCMO FDA ADC SCK
IN+ SDO
R1K1+ 1.1kΩ 33Ω 1nF CNV
R1K+ 1kΩ
1kΩ 0.1µF
ADAQ4003
OUT–
21657-015
Rev. 0 | Page 19 of 35
ADAQ4003 Data Sheet
VS+ = 5.5V REF = 5V REF_OUT VDD = 1.8V
0.1µF
PD_REF
10µF 2.2µF
G = 1.9 10kΩ
VCMO
10kΩ
OUT+ VIO
R1K–/R1K1– R1K– 1kΩ 0.1µF
+2.6V
0V R1K1– 1kΩ
1nF
–2.6V 1.1kΩ 33Ω SDI
IN–
VCMO FDA ADC SCK
IN+ SDO
R1K1+ 1.1kΩ 33Ω 1nF CNV
R1K+ 1kΩ
1kΩ
0.1µF
ADAQ4003
OUT–
21657-016
VCMO PD_AMP VS– MODE GND ADCIN+ ADCIN–
21657-017
VCMO PD_AMP VS– MODE GND ADCIN+ ADCIN–
Rev. 0 | Page 20 of 35
Data Sheet ADAQ4003
G=1 VS+ = 5.5V REF = 5V REF_OUT VDD = 1.8V
21657-019
–7V –7V
VCMO PD_AMP VS– MODE GND ADCIN+ ADCIN–
21657-020
VCMO PD_AMP VS– MODE GND ADCIN+ ADCIN–
EASE OF DRIVE FEATURES Driving the ADAQ4003 Using a High Impedance PGIA
Rev. 0 | Page 21 of 35
ADAQ4003 Data Sheet
–92
In Figure 50, the LTC6373 is used in a differential input to fIN = 1kHz
differential output configuration with dual supplies of ±15V. fIN = 5kHz
–97 fIN = 10kHz
The LTC6373 can also be used in a single-ended input to
differential output configuration, if required. The LTC6373 is
–102
directly driving the ADAQ4003 with its gain set as 0.454. The
THD (DB)
VOCM pin of LTC6373 is connected to ground and its outputs –107
swing between −5.5 V and +5.5 V (opposite in phase). The
FDA of ADAQ4003 level shifts the outputs of the LTC6373 to –112
match the desired input common mode of the ADAQ4003 and
provides the signal amplitude necessary to utilize the maximum –117
21657-053
0.5 1.0 2.0 4.0 8.0 16.0
the SNR and THD performance using various gain settings of LTC6373 GAIN SETTING (G)
the LTC6373 for the circuit configuration shown in Figure 50. Figure 49. THD vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4003
95 (Gain = 0.454)
fIN = 1kHz
fIN = 5kHz
fIN = 10kHz
93
91
SNR (dB)
89
87
85
21657-052
Figure 48. SNR vs. LTC6373 Gain Setting, LTC6373 Driving the ADAQ4003
(Gain = 0.454)
VS+ = 5.5V REF = 5V REF_OUT VDD = 1.8V
0.1µF
PD_REF
10µF 2.2µF
+15V 10kΩ
(+5.5V)/G VCMO
OUT+ 10kΩ
+5.5V VIO
V+ R1K– 1kΩ 0.1µF
(–5.5V)/G V+OUT
R1K1– 1kΩ
A1
– 1nF
A2
–5.5V 33Ω
A0
1.1kΩ SDI
V–IN IN–
VOCM VCMO FDA ADC SCK
LTC6373 IN+ SDO
+5.5V R1K1+ 1.1kΩ 33Ω 1nF CNV
DGND
(+5.5V)/G + R1K+ 1kΩ
CAP
V+IN V– 1kΩ 0.1µF
–5.5V
(–5.5V)/G ADAQ4003
–15V
OUT–
180pF
21657-054
Rev. 0 | Page 22 of 35
Data Sheet ADAQ4003
VOLTAGE REFERENCE INPUT POWER SUPPLY (POWER TREE)
The ADAQ4003 voltage reference input (REF) is the The ADAQ4003 uses four power supply pins: an ADC driver
noninverting node of the on board, low noise reference buffer. positive (VS+) and negative supply (VS−), a core ADC supply
The reference buffer is included to optimally drive the dynamic (VDD), a digital input and output interface supply (VIO). VIO
input impedance of the SAR ADC reference node. allows direct interface with any logic among 1.8 V, 2.5 V, 3 V,
Also housed in the ADAQ4003 is a 10 µF decoupling capacitor or 5 V. To reduce the number of supplies needed, VIO and
that is ideally laid out within the device. This decoupling capacitor VDD can be tied together for 1.8 V operation. A combination
is a required piece of the SAR architecture. The REF_OUT of the ADP5070 (dual, high performance dc-to-dc switching
capacitor is not just a bypass capacitor. This capacitor is part regulator), the LT3032 (dual, low noise, positive and negative,
of the SAR ADC that cannot fit on the silicon simply. During low dropout voltage linear regulator), and the LT3023 (dual,
the bit decision process, because the bits are settled in a few micropower, low noise, low dropout regulator) can generate
tens of nanoseconds or faster, the storage capacitor replenishes independently regulated positive and negative rails for all four
the charge of the internal capacitive DAC. As the binary bit power supply pins, including ±15 V rails for any additional signal
weighted conversion is processed, small chunks of charge are conditioning. Refer to the EVAL-ADAQ4003FMCZ user guide
taken from the 10 µF capacitor. The internal capacitor array is a for details. The ADAQ4003 is insensitive to power supply
fraction of the size of the decoupling capacitor, but this large variations (PSRR) over a wide frequency range, as shown in
value storage capacitor is required to meet the SAR bit decision Figure 33.
settling time. There is no need for an additional lower value The ADAQ4003 ADC powers down automatically at the end of
ceramic decoupling capacitor (for example, 100 nF) between each conversion phase. Therefore, the power scales linearly
the REF_OUT and GND pins. with the sampling rate. This feature makes the device ideal for
The reference value sets the maximum ADC input voltage that low sampling rates (even a few samples per second) and battery-
the SAR capacitor array can quantize. The reference buffer is powered applications. Figure 32 shows the ADAQ4003 total
set in the unity-gain configuration. Therefore, the user sets the power dissipation and individual power dissipation for each rail.
reference voltage value with the REF pin and observes this DIGITAL INTERFACE
value at the REF_OUT pin. The user is responsible for selecting
Although the ADAQ4003 has a reduced number of pins, the
a reference voltage value that is appropriate for the system
device offers flexibility in its serial interface modes. The
under design. Allowable reference values range from 2.4 V to
ADAQ4003 can also be programmed via 16-bit SPI writes
5.1 V. However, do not violate the input common-mode
to the configuration registers.
voltage range specification of the reference buffer. With the
inclusion of the reference buffer, the user can implement a When in CS mode, the ADAQ4003 is compatible with SPI, QSPI™,
much lower power reference source than many traditional SAR MICROWIRE®, digital hosts, and digital signal processors (DSPs).
ADC signal chains because the reference source drives a high In this mode, the ADAQ4003 can use either a 3-wire or 4-wire
impedance node instead of the dynamic load of the SAR interface. A 3-wire interface using the CNV, SCK, and SDO
capacitor array. Root sum square the reference buffer noise signals minimizes wiring connections, which is useful in
with the reference source noise to arrive at a total noise isolated applications. A 4-wire interface using the SDI, CNV,
estimate. Generally, the reference buffer has a noise density SCK, and SDO signals allows CNV, which initiates the
much less than that of the reference source. conversions, to be independent of the readback timing (SDI).
This interface is useful in low jitter sampling or simultaneous
For highest performance and lower drift, use a reference such
sampling applications.
as the ADR4550, or use a low power reference such as the
ADR3450 at the expense of a decrease in the noise The ADAQ4003 provides a daisy-chain feature using the SDI for
performance. cascading multiple ADCs on a single data line, similar to a shift
register.
The mode in which the ADAQ4003 operates depends on the
SDI level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and daisy-chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, daisy-chain mode is automatically selected.
In either 3-wire or 4-wire mode, the ADAQ4003 offers the
option of forcing a start bit in front of the data bits. This start bit
can be used as a busy signal indicator to interrupt the digital
Rev. 0 | Page 23 of 35
ADAQ4003 Data Sheet
host and trigger the data reading. Otherwise, without a busy Table 14. The OV clamp flag is a read only sticky bit, and this
indicator, the user must time out the maximum conversion time bit is cleared only if the register is read and the overvoltage
prior to readback. condition is no longer present. The OV clamp flag gives an
The busy indicator feature is enabled in CS mode if CNV or indication of the overvoltage condition when this bit is set to 0.
SDI is low when the ADC conversion ends.
Table 12. Register Bits
The state of SDO on power-up is either low or high-Z Register Bits Default Status
depending on the states of CNV and SDI (see Table 11). OV Clamp Flag 1 bit, 1 = inactive (default)
Table 11. State of SDO on Power-Up Span Compression 1 bit, 0 = disabled (default)
High-Z Mode 1 bit, 0 = disabled (default)
CNV SDI SDO
Turbo Mode 1 bit, 0 = disabled (default)
0 0 Low
Enable Six Status Bits 1 bit, 0 = disabled (default)
0 1 Low
1 0 Low All access to the register map must start with a write to the 8-bit
1 1 High-Z command register in the SPI interface block. The ADAQ4003
ignores all 1s until the first 0 is clocked in (represented by WEN
The ADAQ4003 has a turbo mode capability in both 3-wire
and 4-wire mode. Turbo mode is enabled by writing to the in Figure 51, Figure 52, and Table 13). The value loaded into
configuration register and replaces the busy indicator feature the command register is always 0 followed by seven command
when enabled. Turbo mode allows a slower SPI clock rate, bits. This command determines whether that operation is a write
making interfacing simpler. The maximum throughput of or a read. The ADAQ4003 command register is listed in Table 13.
2 MSPS for the ADAQ4003 can be achieved only with turbo Table 13. Command Register
mode enabled and a minimum SCK rate of 75 MHz. The SCK Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
rate must be sufficiently fast to ensure the conversion result is
WEN R/W 0 1 0 1 0 0
clocked out before another conversion initiates. The minimum
required SCK rate for an application can be derived based on All register read and writes must occur while CNV is low. Data
the sample period (tCYC), the number of bits that must be read on SDI is clocked in on the rising edge of SCK. Data on SDO is
(including the data and optional status bits), and the digital clocked out on the falling edge of SCK. At the end of the data
interface mode used. Timing diagrams and explanations for transfer, SDO is put in a high impedance state on the rising edge of
each digital interface mode are given in the digital modes of CNV if daisy-chain mode is not enabled. If daisy-chain mode is
operation sections (see the CS Mode, 3-Wire Turbo Mode enabled, SDO goes low on the rising edge of CNV. Register reads
section and the CS Mode, 4-Wire with Busy Indicator section). are not allowed in daisy-chain mode.
Status bits can also be clocked out at the end of the conversion A register write requires three signal lines: SCK, CNV, and SDI.
data if the status bits are enabled in the configuration register. During a register write to read the current conversion results on
The six status bits are described in Table 12. SDO, the CNV pin must be brought low after the conversion
completes. Otherwise, the conversion results may be incorrect
The ADAQ4003 is configured by 16-bit SPI writes to the on SDO. However, the register write occurs regardless.
desired configuration register. The 16-bit word can be written
via the SDI line while CNV is held low. The 16-bit word consists The LSB of each configuration register is reserved because a user
of an 8-bit header and 8-bit register data. For isolated systems, reading 16-bit conversion data may be limited to a 16-bit SPI
the ADuM141D is recommended, which can support the 75 MHz frame. The state of SDI on the last bit in the SDI frame may be
SCK rate required to run the ADAQ4003 at its full throughput the state that then persists when CNV rises. Because interface
of 2 MSPS. mode is partly set based on the SDI state when CNV rises, in
this scenario, the user may need to set the final SDI state.
REGISTER READ AND WRITE FUNCTIONALITY
The timing diagrams in Figure 51 through Figure 53 show how
The ADAQ4003 register bits are programmable, and the bits
data is read and written when the ADAQ4003 is configured in
default statuses are listed in Table 12. The register map is shown in
register read, write, and daisy-chain mode.
Rev. 0 | Page 24 of 35
Data Sheet ADAQ4003
tCYC
tCNVH
tSCK
CNV
tSCNVSCK
tSCKL
SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tHSDISCK tSCKH
tSSDISCK
0 1 0 1 0 1 0 0 tHSDO
tEN tDSDO tDIS
21657-021
SDO D17 D16 D15 D14 D13 D12 D11 D10 B7 B6 B5 B4 B3 B2 B1 B0 X
tSCNVSCK
tSCKL
SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tHSDISCK tSCKH
tSSDISCK
0 0 0 1 0 1 0 0
tHSDO
tEN
tDSDO
21657-022
1THE USER MUST WAIT t
CONV TIME WHEN READING BACK THE CONVERSION RESULT AND DOING A REGISTER WRITE AT THE SAME TIME.
tCYC
tCNVH tSCK
CNV
tSCNVSCK tSCKL
SCK 1 24
tSCKH
tDIS
SDOB
21657-023
0 COMMAND (0x14) 0
Rev. 0 | Page 25 of 35
ADAQ4003 Data Sheet
STATUS WORD
The 6-bit status word can be appended to the end of a conversion The SDO line returns to high impedance after the sixth status
result, and the default conditions of these bits are shown in bit is clocked out (except in daisy-chain mode). The user is not
Table 15. The status bits must be enabled in the register setting. required to clock out all status bits to start the next conversion.
When the OV clamp flag is 0, this bit indicates an overvoltage The serial interface timing for CS mode, 3-wire without busy
condition. The OV clamp flag status bit updates on a per indicator, including status bits, is shown in Figure 54.
conversion basis.
SDI = 1
tCYC
tCNVH
CN V
ACQ
tCONV tSCK
tQUIET2
tSCKL
SCK 1 2 3 16 17 18 22 23 24
tHSDO tSCKH
tEN tDSDO tDIS
21657-024
STATUS BITS B[5:0]
Figure 54. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram Including Status Bits (SDI High)
Rev. 0 | Page 26 of 35
Data Sheet ADAQ4003
CS MODE, 3-WIRE TURBO MODE SDO to high impedance. The user must wait the tQUIET1 time
after CNV is brought high before bringing CNV low to clock out
This mode is typically used when a single ADAQ4003 device is
the previous conversion result. When the conversion is complete
connected to an SPI-compatible digital host. This mode provides
(after tCONV), the ADAQ4003 enters the acquisition phase and
additional time during the end of the ADC conversion process to
powers down. The user must also wait the tQUIET2 time after the
clock out the previous conversion result, providing a lower SCK
last falling edge of SCK to when CNV is brought high.
rate. The ADAQ4003 can achieve a throughput rate of 2 MSPS
only when turbo mode is enabled and using a minimum SCK rate When CNV goes low, the MSB is output to SDO. The remaining
of 75 MHz. The connection diagram is shown in Figure 55, and data bits are clocked by subsequent SCK falling edges. The data is
the corresponding timing diagram is shown in Figure 56. valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
To enable turbo mode, set the turbo mode enable bit in the
reading rate, provided it has an acceptable hold time, as dictated by
configuration register to 1 (see Table 12). This mode replaces
tHSDO (see Table 3). If the status bits are not enabled, SDO returns
the 3-wire with busy indicator mode by programming the turbo
to high impedance after the 18th SCK falling edge. If the status
mode bit, Bit 1 (see Table 14). Writing to the user configuration
bits are enabled, the bits are shifted out on SDO on the 19th
register requires SDI to be connected to the digital host (see the
through the 24th SCK falling edges (see the Status Word
Register Read and Write Functionality section). When turbo
section). SDO returns to high impedance after the 18th SCK
mode is enabled, the conversion result read on SDO corresponds
falling edge, or when CNV goes high (whichever occurs first).
to the result of the previous conversion.
The user must also provide a delay of tQUIET2 between the final
When performing conversions in this mode, SDI must be held SCK falling edge and the next CNV rising edge to ensure
high, and a CNV rising edge initiates a conversion and forces specified performance.
DATA OUT
CONVERT
SCK
21657-025
CLK
Figure 55. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High)
SDI = 1
tCYC
CNV
tACQ
tCONV tSCK
tSCKL
tQUIET2
tQUIET1
SCK 1 2 3 16 17 18
tHSDO tSCKH
tEN tDSDO tDIS
21657-026
Figure 56. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 27 of 35
ADAQ4003 Data Sheet
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR When the conversion completes, the ADAQ4003 enters the
acquisition phase and powers down. When CNV goes low, the
This mode is typically used when a single ADAQ4003 device is
MSB is output onto SDO. The remaining data bits are clocked by
connected to an SPI-compatible digital host. The connection
subsequent SCK falling edges. The data is valid on both SCK
diagram is shown in Figure 57, and the corresponding timing
edges. Although the rising edge can capture the data, a digital host
diagram is shown in Figure 58.
using the SCK falling edge allows a faster reading rate, provided
When SDI is connected to VIO, a rising edge on CNV initiates a that the digital host has an acceptable hold time. After the 18th
conversion, selects the CS mode, and forces SDO to high SCK falling edge or when CNV goes high (whichever occurs
impedance. After a conversion initiates, it continues until first), SDO returns to high impedance.
completion irrespective of the state of CNV. This feature can be
There must not be any digital activity on SCK during the
useful, for instance, to bring CNV low to select other SPI devices,
conversion.
such as analog multiplexers. However, CNV must be returned
high before the minimum conversion time elapses and then
held high for the maximum possible conversion time to avoid
the generation of the busy signal indicator.
CONVERT
SCK
21657-027
CLK
Figure 57. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV tSCK
tSCKL tQUIET2
SCK 1 2 3 16 17 18
tHSDO tSCKH
tEN tDSDO tDIS
Figure 58. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 28 of 35
Data Sheet ADAQ4003
CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion completes, SDO goes from high
impedance to low impedance. With a pull-up resistor of 1 kΩ
This mode is typically used when a single ADAQ4003 device is
on the SDO line, this transition can be used as an interrupt
connected to an SPI-compatible digital host with an interrupt
signal to initiate the data reading controlled by the digital host.
input (IRQ).
The ADAQ4003 then enters the acquisition phase and powers
The connection diagram is shown in Figure 59, and the down. The data bits are then clocked out, MSB first, by
corresponding timing diagram is shown in Figure 60. subsequent SCK falling edges. The data is valid on both SCK
When SDI is connected to VIO, a rising edge on CNV initiates a edges. Although the rising edge can capture the data, a digital
conversion, selects the CS mode, and forces SDO to high host using the SCK falling edge allows a faster reading rate,
impedance. SDO is maintained in high impedance until the provided that the digital host has an acceptable hold time. After
completion of the conversion irrespective of the state of CNV. the optional 19th SCK falling edge or when CNV goes high
Prior to the minimum conversion time, CNV can select other SPI (whichever occurs first), SDO returns to high impedance.
devices, such as analog multiplexers. However, CNV must be If multiple ADAQ4003 devices are selected at the same time,
returned low before the minimum conversion time elapses and the SDO output pin handles this contention without damage or
then held low for the maximum possible conversion time to induced latch-up. Meanwhile, it is recommended to keep this
guarantee the generation of the busy signal indicator. contention as short as possible to limit extra power dissipation.
There must not be any digital activity on the SCK during the
conversion.
CONVERT
VIO
CNV DIGITAL HOST
VIO 1kΩ
SCK IRQ
21657-029
CLK
Figure 59. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV tSCK
tSCKL tQUIET2
SCK 1 2 3 17 18 19
tHSDO tSCKH
tDSDO tDIS
21657-030
Figure 60. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High)
Rev. 0 | Page 29 of 35
ADAQ4003 Data Sheet
CS MODE, 4-WIRE TURBO MODE rising edge. The user must wait tQUIET1 after CNV is brought high
before bringing SDI low to clock out the previous conversion
This mode is typically used when a single ADAQ4003 is
result. The user must also wait tQUIET2 after the last falling edge
connected to an SPI-compatible digital host. This mode provides
of SCK to when CNV is brought high.
additional time during the end of the ADC conversion process
to clock out the previous conversion result, giving a lower SCK When the conversion is complete, the ADAQ4003 enters the
rate. The ADAQ4003 can achieve a throughput rate of 2 MSPS acquisition phase and powers down. The ADC result can be
only when turbo mode is enabled and using a minimum SCK rate read by bringing its SDI input low, which consequently outputs
of 75 MHz. The connection diagram is shown in Figure 61, and the MSB onto SDO. The remaining data bits are then clocked
the corresponding timing diagram is shown in Figure 62. by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can capture the data, a digital
This mode replaces the 4-wire with busy indicator mode by
host using the SCK falling edge allows a faster reading rate,
programming the turbo mode bit, Bit 1 (see Table 14).
provided that the digital host has an acceptable hold time. After
With SDI high, a rising edge on CNV initiates a conversion. the 18th SCK falling edge or when SDI goes high (whichever
The previous conversion data is available to read after the CNV occurs first), SDO returns to high impedance.
CS1
CONVERT
VIO
CNV DIGITAL HOST
1kΩ
SCK IRQ
21657-031
CLK
CNV
tCYC
tSSDICNV
SDI
tHSDICNV
tACQ
tCONV tSCK
tSCKL tQUIET2
tQUIET1
SCK 1 2 3 16 17 18
tHSDO tSCKH
tEN tDSDO tDIS
21657-032
Rev. 0 | Page 30 of 35
Data Sheet ADAQ4003
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
This mode is typically used when multiple ADAQ4003 devices
signal indicator.
are connected to an SPI-compatible digital host.
When the conversion is complete, the ADAQ4003 enters the
A connection diagram example using two ADAQ4003 devices
acquisition phase and powers down. Each ADC result can be
is shown in Figure 63, and the corresponding timing diagram is
read by bringing its SDI input low, which consequently outputs
shown in Figure 64.
the MSB onto SDO. The remaining data bits are then clocked
With SDI high, a rising edge on CNV initiates a conversion, by subsequent SCK falling edges. The data is valid on both SCK
selects the CS mode, and forces SDO to high impedance. In this edges. Although the rising edge can capture the data, a digital
mode, CNV must be held high during the conversion phase host using the SCK falling edge allows a faster reading rate,
and the subsequent data readback. If SDI and CNV are low, provided that the digital host has an acceptable hold time. After
SDO is driven low. Prior to the minimum conversion time, SDI the 18th SCK falling edge or when SDI goes high (whichever occurs
can select other SPI devices, such as analog multiplexers. first), SDO returns to high impedance and another ADAQ4003
However, SDI must be returned high before the minimum can be read.
CS2
CS1
CONVERT
CNV CNV
DIGITAL HOST
SDI ADAQ4003 SDO SDI ADAQ4003 SDO
DEVICE A DEVICE B
SCK SCK
21657-033
DATA IN
CLK
tCYC
CNV
tACQ
tCONV
tSSDICNV tQUIET2
SDI (CS1)
tHSDICNV
SDI (CS2)
tSCK
tSCKL
SCK 1 2 3 16 17 18 19 20 34 35 36
tHSDO tSCKH
tEN tDSDO tDIS
21657-034
Figure 64. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram
Rev. 0 | Page 31 of 35
ADAQ4003 Data Sheet
CS MODE, 4-WIRE WITH BUSY INDICATOR However, SDI must be returned low before the minimum
conversion time elapses and then held low for the maximum
This mode is typically used when a single ADAQ4003 device is
possible conversion time to guarantee the generation of the
connected to an SPI-compatible digital host with an interrupt
busy signal indicator.
input (IRQ), and when it is desired to keep CNV, which samples
the analog input, independent of the signal used to select the data When the conversion is complete, SDO goes from high impedance
reading. This independence is particularly important in to low impedance. With a pull-up resistor of 1 kΩ on the SDO
applications where low jitter on CNV is desired. line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The ADAQ4003
The connection diagram is shown in Figure 65, and the
then enters the acquisition phase and powers down. The data
corresponding timing diagram is shown in Figure 66.
bits are then clocked out, MSB first, by subsequent SCK falling
With SDI high, a rising edge on CNV initiates a conversion, edges. The data is valid on both SCK edges. Although the rising
selects the CS mode, and forces SDO to high impedance. In this edge can capture the data, a digital host using the SCK falling
mode, CNV must be held high during the conversion phase edge allows a faster reading rate, provided that the digital host
and the subsequent data readback. If SDI and CNV are low, has an acceptable hold time. After the optional 19th SCK falling
SDO is driven low. Prior to the minimum conversion time, SDI edge or when SDI goes high (whichever occurs first), SDO
can select other SPI devices, such as analog multiplexers. returns to high impedance.
CS1
CONVERT
VIO
CNV DIGITAL HOST
1kΩ
SCK IRQ
21657-035
CLK
CNV
tACQ
tCONV
tSSDICNV tQUIET2
SDI
tSCK
tHSDICNV
tSCKL
SCK 1 2 3 17 18 19
tHSDO tSCKH
tDSDO tDIS
tEN
21657-036
Figure 66. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram
Rev. 0 | Page 32 of 35
Data Sheet ADAQ4003
DAISY-CHAIN MODE first, and 18 × N clocks are required to read back the N ADCs.
The data is valid on both SCK edges. The maximum conversion
Use this mode to daisy-chain multiple ADAQ4003 devices on
rate is reduced because of the total readback time.
a 3-wire or 4-wire serial interface. This feature is useful for
reducing component count and wiring connections, for It is possible to write to each ADC register in daisy-chain mode
example, in isolated multiconverter applications or for systems (see Figure 68). This mode requires 4-wire operation because
with a limited interfacing capacity. Data readback is analogous data is clocked in on the SDI line with CNV held low. The same
to clocking a shift register. command byte and register data can be shifted through the entire
chain to program all ADCs in the chain with the same register
A connection diagram example using two ADAQ4003 devices
contents, which requires 8 × (N + 1) clocks for N ADCs. It is
is shown in Figure 67, and the corresponding timing diagram is
possible to write different register contents to each ADC in the
shown in Figure 68.
chain by writing to the furthest ADC in the chain, first using 8 ×
When SDI and CNV are low, SDO is driven low. With SCK (N + 1) clocks, and then the second furthest ADC with 8 × N
low, a rising edge on CNV initiates a conversion, selects daisy- clocks, and so forth until reaching the nearest ADC in the chain,
chain mode, and disables the busy indicator. In this mode, which requires 16 clocks for the command and register data.
CNV is held high during the conversion phase and the
It is not possible to read register contents in daisy-chain mode.
subsequent data readback. When the conversion is complete,
However, the six status bits can be enabled if the user wants to
the MSB is output onto SDO, and the ADAQ4003 enters the
determine the ADC configuration. Note that enabling the
acquisition phase and powers down. The remaining data bits
status bits require six extra clocks to clock out the ADC result
stored in the internal shift register are clocked out of SDO by
and the status bits per ADC in the chain. Turbo mode cannot
subsequent SCK falling edges. For each ADC, SDI feeds the
be used in daisy-chain mode.
input of the internal shift register and is clocked by the SCK
rising edges. Each ADC in the daisy-chain outputs its data MSB
CONVERT
SCK SCK
21657-037
CLK
CNV
tACQ
tCONV tSCK
tSCKL tQUIET2
tQUIET2
SCK 1 2 3 16 17 18 19 20 34 35 36
tHSDO
tDIS
tDSDO
21657-038
Rev. 0 | Page 33 of 35
ADAQ4003 Data Sheet
LAYOUT GUIDELINES The ADAQ4003 enables high channel density PCB layout by
incorporating all the necessary decoupling ceramic capacitors for
The PCB layout is critical for preserving signal integrity and
the reference and power supply (REF, VS+, VS−, VDD, and
achieving the expected performance from the ADAQ4003. It is
VIO) pins to provide a low impedance path to ground at high
recommended to design a multilayer board with an internal,
frequencies and to handle the transient currents so that the
clean ground plane and a separate power plane to route various
additional external decoupling capacitors are not required
supply rails beneath the ADAQ4003. Care must be taken with
without causing any performance impact or electromagnetic
the placement of individual components and routing of various
interference (EMI) issues, saving board space. This performance
signals on the board. It is highly recommended to route input
impact was verified on the EVAL-ADAQ4003FMCZ by
and output signals symmetrically while keeping the power
removing the external decoupling capacitors on the output of
supply circuitry away from the analog signal path. Keep the
reference and LDO regulators that generate the on-board rails
sensitive analog and digital sections separate and confined to
(REF, VS+, VS−, VDD, and VIO). Figure 69 shows that any
certain areas of the board and avoid crossover of digital and
spurs are buried well below −120 dB in the noise floor whether
analog signals.
the external decoupling capacitors are used or removed. The
The pinout of the ADAQ4003 eases the layout and allowing its recommended board layout is outlined in the EVAL-
analog signals on the left side and its digital signals on the right ADAQ4003FMCZ user guide.
side. Fast switching signals, such as CNV or clocks, must not 0
run near or crossover analog signal paths to prevent noise
–20
coupling to the ADAQ4003. Remove the ground and power
–40
planes beneath the input and output pins of ADAQ4003 to
avoid undesired parasitic capacitance, especially underneath –60
AMPLITUDE (dB)
summing junction nodes (IN+ and IN−) and any floating –80
junction nodes tends to reduce the phase margin of the FDA –120
–180
–200
21657-172
0 200k 400k 600k 800k 1M
FREQUENCY (Hz)
Rev. 0 | Page 34 of 35
Data Sheet ADAQ4003
OUTLINE DIMENSIONS
7.10
7.00 SQ A1 BALL
A1 BALL 6.90 CORNER
CORNER 1.10 7 6 5 4 3 2 1
REF
A
B
4.80 REF C
SQ
D
G
0.80
BSC
TOP VIEW BOTTOM VIEW
DETAIL A
2.432 1.65 REF
2.332 SIDE VIEW DETAIL A
0.372
2.232
0.40 0.332
0.35 0.292
0.30
COPLANARITY
0.50
07-02-2018-A
SEATING 0.08
0.45
PKG-005496
PLANE
0.40
BALL DIAMETER
Figure 70. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2 Temperature Range Ordering Quantity Package Description Package Option
ADAQ4003BBCZ −40°C to +125°C Tray, 416 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-49-5
ADAQ4003BBCZ-RL13 −40°C to +125°C Reel, 2000 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-49-5
EVAL-ADAQ4003FMCZ Evaluation Board Kit
1
Z = RoHS Compliant Part.
2
The EVAL-ADAQ4003FMCZ evaluation board kit is compatible with the EVAL-SDP-CH1Z. See the UG-1533 for more details.
Rev. 0 | Page 35 of 35