Prajit Nandi
Prajit Nandi
Prajit Nandi
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TCAD.2015.2474379, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper Control Number: 1
Dear Editor,
Enclosed is a revised manuscript, entitled "A Novel Approach to Design SAR-ADC: Design Partitioning Method” to be
considered for publication in the “IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems". All
the modifications are highlighted by Yellow background.
Author Details:
1. Prajit Nandi
Design Engineering Director, Sankalp Analog Solutions,
Sankalp Semiconductor Pvt. Ltd., DLF II IT Park, Block 2F, AA-2, New Town, Kolkata, West Bengal-700156, India.
E-mail: [email protected]
2. Hirak Talukdar
Design Engineer, Sankalp Analog Solutions,
Sankalp Semiconductor Pvt. Ltd., DLF II IT Park, Block 2F, AA-2, New Town, Kolkata, West Bengal-700156, India.
E-mail: [email protected]
3. Dhiraj Kumar
Technical Lead, Sankalp Analog Solutions,
Sankalp Semiconductor Pvt. Ltd., DLF II IT Park, Block 2F, AA-2, New Town, Kolkata, West Bengal-700156, India.
E-mail: [email protected]
We, hereby certify that we are the sole authors of this work and that no part of this work has been published or submitted for
publication in any other journal or conference. Information derived from the published and unpublished work of others has been
acknowledged in the text and a list of references is given in the bibliography.
Sincerely,
Prajit Nandi
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according to their functionality rather than their actual used as S/H circuit in SAR-ADC. Bottom-plate-sampling
structure. Thus, it can be viewed as a technique to partition the technique [13] is employed in CDAC based S/H circuits. For
whole design. Hence, the name Design-Partitioning-Method simplicity single ended bottom plate sampling mechanism is
(DPM) has been used. Root-cause analysis can be done easily shown in the Fig.4b. The clock (φ) and delayed clock (φ d) are
by making individual blocks real while keeping all the other used for bottom-plate sampling. Output voltage of S/H circuit
blocks ideal. It aims at striking an optimized analysis across can be described by Eq.1 and Eq.2 in ideal scenario. Based on
the design vectors, as illustrated in Fig.1. The proposed rms-jitter of the sampling clock, Half-Cycle-Jitter [14] is
platform uses Verilog-A [4] language to model different
components of SAR-ADC.
II. IMPLEMENTATION
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Ci Di
N
Vout_p_C Vcm (Vrefp Vcm ) e Cp (4)
i 1 C tot
N
C Di
Vout_n_C Vcm i (Vrefn Vcm ) e Cn (5)
i 1 C tot
Fig.4 a) S/H Port diagram b) Bottom-Plate Sampling Where,
mechanism (Single-Ended) c) Spread of sampling clock e Cp , e Cn f 2 ( C , C , clk FT , clk CI , Q LEAK ,
transition-edges (σ stands for RMS value of the uncorrelated (6)
clock-jitter) d) Structure of S/H corresponding to a 4bit CDAC COMPLOAD , N KT/C )
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a)
C gs_sw
clk FT VCLK * (7)
C tot
W L C 1
clk CI sw sw OX * (VCLK VREF VTH ) * (8)
2 C tot
kT
N KT/C (9)
C tot
N
C Di K R j
Vout_p_R Vcm ( i ) b)
i Q 1 C tot j0 R tot (10)
(Vrefp Vcm ) e Rp
N
Ci Di K R j
Vout_n_R Vcm ( )
i Q 1 C tot j0 R tot (11)
(Vrefn Vcm ) e Rn
Where,
Q
K 2 (x -1) Dx (12)
x 1
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2) Latch
TLatch
( )
L
Vcomp OP e (21)
D. SAR-Logic Block
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As shown in Fig.11, in the proposed modelling scheme each B. Comparative Study of Digital to Analog Converter (DAC)
block is realized separately (i.e. separate S/H and DAC,
though in reality they are a single block with dual A hybrid-DAC [20, 26] is used in the 14-bit SAR-ADC design
functionality). It results in easy root-cause analysis. (Capacitive DAC for MSB-bits and Resistive DAC for LSB-
bits). Unit resistance (Runit) and unit capacitance (Cunit) values
III. ANALYSIS AND RESULTS for hybrid-DAC are determined based on their mismatch
numbers. σR and σC represents the Standard-Deviations (S.D.)
As a case study 14bit, 4.2MSPS SAR-ADC architecture is of the resistor-mismatch and capacitor-mismatch respectively.
evaluated. Conventional static and dynamic tests have been
done. In static testing a dc-analysis is done by applying a dc-
sweep voltage at input. In dynamic testing a transient analysis a)
is performed with sine-wave input. In post-simulations,
standard parameters of ADC [35-37] are evaluated. For apple
to apple comparison all the simulations are done on spice-
netlist, structural-model and proposed modelling scheme
(DPM).
Fig.13 a) SINAD vs. (σR – σC) plots and b) SFDR vs. (σR – σC)
plots (RED: Spice- Netlist, YELLOW: Structural-Model,
BLUE: DPM)
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C. Comparative Study of Comparator In the proposed modelling scheme top-level simulations are
done with different number of Pre-Amplifier stages with
different values of Latch-Time-Constant (τL). For simplicity,
a) Voltage Gains (Av) of all the Pre-Amplifier stages are kept
same. The SINAD and SFDR results are shown in Fig.14a and
Fig.14b. The specifications of the Comparator are also derived
using the behavioral-model of the comparator. Three-stage
Pre-Amplifier along with a latch of τL ≈ 80ps are used in the
actual design. Spice-netlist simulation of the final top-level
design reviles ADC performance is satisfactory with the
derived comparator architecture.
b)
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realized by a set of multi-variable time-independent equations. Data in the LUTs for DAC as well as S/H are stored in uV
The equations accurately calculate the final comparator output order with 6-digits after decimal point, effectively the data
by solving algebraic equations only, which makes the model accuracy is in the order of pV. As the LUT files contain arrays
independent of iterations. Spice-netlists need iterations in of numbers only, so the memory requirement is insignificant.
continuous-time as they work by solving differential- As shown in the Table-III, for a 2^14 point FFT simulation,
equations. In the proposed model, iterations are required only ~1.2MB memory is required for storing the LUTs.
at clock-edges. This helps in reducing the computational-
In the case of Monte-Carlo simulation, mismatched element
effort.
values are generated using random numbers. The values of
Standard-Deviation for those random numbers are derived
from the Process-Design-Kit (PDK) and Monte-Carlo
simulation results. Then the mismatched element values are
used to generate block level LUTs. In multiple Monte-Carlo
runs different seed values are used to generate different sets of
random numbers.
Fig.20 Accuracy and Simulation-Time (RED: Spice-Netlist, TABLE I. SIMULATION TIME COMPARISON
YELLOW: Structural Model and BLUE: DPM)
Proposed Structural Spice
Analysis
Fig.20 shows simulation-time reduction in the proposed Platform Model Netlist
modelling scheme while providing better accuracy than the Dynamic
structural-model. The accuracy numbers are evaluated by Testing
13.5 hrs 88 hrs 416 hrs
calculating percentage accuracy in terms of SINAD (Fig.12a (16384 FFT
and 13a), SFDR (Fig.12b and 13b) and offset measurement Points)
(Fig.15), assuming spice-netlist results are 100% accurate
(reference results). Structural model lags in accuracy as
individual blocks are not as accurate as spice-netlist while in TABLE II. SIMULATION TIME BREAK-UP
the proposed modelling scheme; data for each individual block
is generated by simulating spice-netlist only. The simulation- Analysis Attributes DAC S/H Top-Level
time of Structural Model is also 7-times that of the proposed
Simulation 1.15
modelling scheme. The extremely fast top-level simulation (by Dynamic 4.8 hrs 0.8 hrs
Time hrs
eliminating the need of iteration) results in this simulation- Testing
Simulator
time reduction. (16384 2 2 2
Licenses
FFT
Points) Effective 2.3
Time taken by the proposed modelling platform for a 9.6 hrs 1.6 hrs
Time hrs
dynamic-simulation (16,384 point FFT) is only ~3% of the
time taken by equivalent spice-netlist. Detail simulation-time
measurements are given in Table-I. Effective simulation-time
is calculated by multiplying actual simulation time and
number of simulator licenses. TABLE III. MEMORY REQUIREMENT FOR LUT
LUT Memory
The simulation-time advantage becomes more pronounced Block Data- No. of
Size Requirement
in the cases where design changes are required in selective Name Points LUTs
(KB) (KB)
blocks only. Any changes in a single block results in re-
generation of that block’s data only. Table-II describes the 16384
DAC ~300 2 ~600
simulation-time (13.5hrs mentioned in Table-I) break-up for (2^14)
different blocks. Similarly for large number of FFT points 16384
S/H ~300 2 ~600
only S/H block and top-level need longer simulation times, (2^14)
same DAC data can be re-used there. It also increases the Total Memory Requirement (KB) ~1200
reusability of the model.
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