A Solar Power Generation System With A Seven-Level Inverter: Jinn-Chang Wu, Member, IEEE, Chia-Wei Chou
A Solar Power Generation System With A Seven-Level Inverter: Jinn-Chang Wu, Member, IEEE, Chia-Wei Chou
A Solar Power Generation System With A Seven-Level Inverter: Jinn-Chang Wu, Member, IEEE, Chia-Wei Chou
Abstract-- This paper proposes a new solar power generation conversion interface is important to insure there is no waste of
system, which is composed of a DC/DC power converter and a the energy generated by the solar cell array. The active
new seven-level inverter. The DC/DC power converter integrates devices and passive devices in the inverter produce a power
a DC-DC boost converter and a transformer to convert the
loss. The power losses due to active devices include both
output voltage of the solar cell array into two independent
voltage sources with multiple relationships. This new seven-level conduction losses and switching losses [5]. Conduction loss
inverter is configured using a capacitor selection circuit and a results from the use of active devices, while the switching loss
full-bridge power converter, connected in cascade. The capacitor is proportional to the voltage and the current changes for each
selection circuit converts the two output voltage sources of DC- switching and switching frequency. A filter inductor is used to
DC power converter into a three-level DC voltage and the full- process the switching harmonics of an inverter, so the power
bridge power converter further converts this three-level DC
loss is proportional to the amount of switching harmonics.
voltage into a seven-level AC voltage. In this way, the proposed
solar power generation system generates a sinusoidal output The voltage change in each switching operation for a
current that is in phase with the utility voltage and is fed into the multi-level inverter is reduced in order to improve its power
utility. The salient features of the proposed seven-level inverter conversion efficiency [6-15] and the switching stress of the
are that only six power electronic switches are used and only one active devices. The amount of switching harmonics is also
power electronic switch is switched at high frequency at any attenuated, so the power loss caused by the filter inductor is
time. A prototype is developed and tested to verify the
performance of this proposed solar power generation system..
also reduced. Therefore, multi-level inverter technology has
been the subject of much research in the past few years. In
Index Terms—multilevel inverter, grid-connected, pulse width theory, multi-level inverters should be designed with higher
modulated (PWM) inverter voltage levels in order to improve the conversion efficiency
and to reduce harmonic content and electromagnetic
I. INTRODUCTION
interference (EMI).
The extensive use of fossil fuels has resulted in the
Conventional multi-level inverter topologies include the
global problem of greenhouse emissions. Moreover, as the
diode-clamped [6-10], the flying-capacitor [11-13] and the
supplies of fossil fuels are depleted in the future, they will
cascade H-bridge [14-18] types. Diode-clamped and flying-
become increasingly expensive. Thus solar energy is
capacitor multi-level inverters use capacitors to develop
becoming more important since it produces less pollution and
several voltage levels. But it is difficult to regulate the voltage
the cost of fossil fuel energy is rising, while the cost of solar
of these capacitors. Since it is difficult to create an
arrays is decreasing. In particular, small-capacity distributed
asymmetric voltage technology in both the diode-clamped and
power generation systems using solar energy may be widely
the flying-capacitor topologies, the power circuit is
used in residential applications in the near future [1, 2].
complicated by the increase in the voltage levels that is
The power conversion interface is important to grid-
necessary for a multi-level inverter. For a single-phase seven-
connected solar power generation systems because it converts
level inverter, twelve power electronic switches are required
the DC power generated by a solar cell array into AC power
in both the diode-clamped and the flying-capacitor topologies.
and feeds this AC power into the utility grid. An inverter is
Asymmetric voltage technology is used in the cascade H-
necessary in the power conversion interface to convert the DC
bridge multi-level inverter to allow more levels of output
power to AC power [2-4]. Since the output voltage of a solar
voltage [17], so the cascade H-bridge multi-level inverter is
cell array is low, a DC-DC power converter is used in a
suitable for applications with increased voltage levels. Two
small-capacity solar power generation system to boost the
H-bridge inverters with a dc bus voltage of multiple
output voltage so it can match the DC bus voltage of the
relationships can be connected in cascade to produce a single-
inverter. The power conversion efficiency of the power
phase seven-level inverter and eight power electronic
switches are used. More recently, various novel topologies for
seven-level inverters have been proposed. For example, a
J. C. Wu is with the Department of Microelectronic Engineering, National
Kaohsiung Marine University, Kaohsiung, Taiwan, R.O.C. (e-mail: single-phase seven-level grid-connected inverter has been
[email protected]). developed for a photovoltaic system [18]. This seven-level
C. W. Chou is with the Department of Microelectronic Engineering, grid-connected inverter contains six power electronic
National Kaohsiung Marine University, Kaohsiung, Taiwan, R.O.C. switches. However, three dc capacitors are used to construct
the three voltage levels, which results in that balancing the
voltages of the capacitors is more complex. In [19], a seven-
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
2
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
3
Fig. 2 operation of DC-DC power converter, (a) SD1 is on, (b) SD1 is off.
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
4
Fig. 4 operation of seven-level inverter in the negative half cycle, (a) mode
5, (b) mode 6, (c) mode 7, (d) mode 8.
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
5
shown in Fig. 5, should be used to eliminate the disturbance, Table I states of power electronic switches for seven-level inverter
positive half cycle
and the gain Gf should be 1/kpwm.
SS1 SS2 S1 S2 S3 S4
In the negative half cycle, the seven-level inverter is on
v u <Vdc/3 off off PWM off off
switched between modes 5 and 8, in order to output a voltage
2Vdc/3> v u >Vdc/3 off on off off on
of -Vdc/3 or 0 when the absolute value of the utility voltage is PWM
smaller than Vdc/3. Accordingly, S3 is switched in PWM. The v u >2Vdc/3 PWM on on off off on
seven-level inverter is switched in modes 6 and 5 to output a negative half cycle
voltage of -2Vdc/3 or -Vdc/3 when the utility voltage is in the v u <Vdc/3 off off off on PWM off
range (-Vdc/3, -2Vdc/3).Within this voltage range, SS2 is on
2Vdc/3> v u >Vdc/3 off PWM off on off
switched in PWM. The seven-level inverter is switched in
modes 7 and 6 to output a voltage of -Vdc or -2Vdc/3 when the v u >2Vdc/3 PWM on off on on off
utility voltage is in the range (-2Vdc/3, -Vdc). At this voltage
range, SS1 is switched in PWM and SS2 remains in the on state
to avoid switching of SS2. The simplified model for the seven-
level inverter in the negative half cycle is the similar to that
for the positive half cycle.
Since only six power electronic switches are used in the
proposed seven-level inverter, the power circuit is
significantly simplified compared with a conventional seven-
level inverter. The states of the power electronic switches of
the seven-level inverter, as detailed previously, are
summarized in Table I. It can be seen that only one power
Fig. 6 configuration of the proposed solar power generation system for
electronic switch is switched in PWM within each voltage suppressing the leakage current.
range and the change in the output voltage of the seven-level
inverter for each switching operation is Vdc/3, so switching
power loss is reduced. Figures 3 and 4 show that only three
semiconductor devices are conducting in series in modes 1, 3,
4, 5, 7 and 8 and four semiconductor devices are conducting
in series in modes 2 and 6. This is superior to the
conventional multi-level inverter topologies, in which at least
four semiconductor devices are conducting in series.
Therefore, the conduction loss of the proposed seven-level
inverter is also reduced slightly. The drawback of the
proposed seven-level inverter is that the voltage rating of the
full-bridge converter is higher than that of conventional multi-
Fig. 7 simulation results of proposed solar power generation system, (a)
level inverter topologies. utility voltage, (b) negative terminal voltage for adding the
The leakage current is an important parameter in a solar symmetric filter inductor, (c) negative terminal voltage for adding
power generation system for transformerless operation. The the symmetric filter inductor and the extra filter C f-Rf-Cf.
leakage current is dependent on the parasitic capacitance and
(S1, S2). Figure 7(c) shows the negative terminal voltage of a
the negative terminal voltage of the solar cell array respect to
solar cell array for the seven-level inverter with the symmetric
ground [22, 23]. To reduce the leakage current, the filter
inductor Lf should be replaced by a symmetric topology and filter inductor and the extra filter Cf-Rf-Cf of 1F-25-1F.
the solar power generation system is redrawn as Fig. 6. Figure As seen in Fig. 7(c), the high-frequency ripple is attenuated
7 shows the simulation results of the proposed solar power effectively, so the leakage current can be further reduced.
generation system. Figure 7(b) is the negative terminal
voltage of the solar cell array for the seven-level inverter with V. Control Block
the symmetric filter inductor of 0.95mH. As seen in Fig. 7(b), The proposed solar power generation system consists of a
this voltage contains a high-frequency ripple. The peak-to- DC-DC power converter and a seven-level inverter. The
peak value of the high-frequency ripple is about 30V, which seven-level inverter converts the DC power into high quality
is much smaller than that of a full-bridge inverter with AC power and feeds it into the utility and regulates the
unipolar switching [22, 23]. This high-frequency ripple will voltages of capacitors C1 and C2. The DC-DC power
result in a leakage current of solar cell array. If the leakage converter supplies two independent voltage sources with
current of solar cell array is too high to be accepted, an extra multiple relationships and performs maximum power point
filter Cf-Rf-Cf, as shown in Fig. 6, can be added. Since the tracking (MPPT) in order to extract the maximum output
switching of S4 is synchronized with the utility voltage, the power from the solar cell array.
extra filter Cf-Rf-Cf is only added in the power-electronic leg A. Seven-Level Inverter
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
6
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
7
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
8
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.
9
Biographies
Jinn-Chang Wu (M’07) was born in
Tainan, Taiwan in 1968. He graduated
from National Kaohsiung Institute of
Technology, Kaohsiung, Taiwan in 1988,
and received his M.S. and Ph.D. degree
from National Cheng Kung University,
Tainan, Taiwan in 1992 and 2000, all in
electrical engineering. Since 2007, he has
been an associate professor at the
Department of Microelectronic Engineering, National
Kaohsiung Marine University. His research interests are
power quality and power electronic applications.
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected].