Implementing Ddr2/Mddr PCB Layout On The Tms320Dm335 Dmsoc: Application Report

Application Report
SPRAAL2D – November 2009
Implementing DDR2/mDDR PCB Layout on the

TMS320DM335 DMSoC
DSPS Applications ...........................................................................................................................
ABSTRACT
This application report contains implementation instructions for the DDR2/mDDR interface contained on
the TMS320DM335 Digital Media System-on-Chip (DMSoC) device. The approach to specifying interface
timing for the DDR2/mDDR interface is quite different than on previous devices.
The previous approach specified device timing in terms of data sheet specifications and simulation
models. The system designer was required to obtain compatible memory devices, as well as the
device-specific data sheets and simulation models. This information would then be used to design the
printed circuit board (PCB) using high-speed simulation to close system timing.
For the DM335 DDR2/mDDR interface, the approach is to specify compatible DDR2/mDDR devices and
provide the PCB routing rule solution directly. TI has performed the simulation and system design work to
ensure DDR2/mDDR interface timings are met. This document describes the required routing rules.
The DM335 EVM provides an example of a PCB layout following these routing rules that passes FCC EMI
requirements. You can copy the DDR2/mDDR portion of this layout directly, but the intent is to allow
enough flexibility in the routing rules to meet other PCB requirements.
Contents
1 TMS320DM335 .............................................................................................................. 2
2 References ................................................................................................................. 14
List of Figures
1 DM335 DDR2/mDDR Single-Memory High Level Schematic ......................................................... 5
2 DM335 DDR2/mDDR Dual-Memory High Level Schematic ........................................................... 5
3 DM335 and DDR2/mDDR Device Placement ........................................................................... 6
4 DDR2/mDDR Keepout Region ............................................................................................ 7
5 VREF Routing and Topology ............................................................................................ 11
6 CK and ADDR_CTRL Routing and Topology.......................................................................... 11
7 DQS and DQ Routing and Topology .................................................................................... 12
8 DQGATE Routing ......................................................................................................... 13
List of Tables
1 Compatible JEDEC DDR2/mDDR Devices .............................................................................. 2
2 DM335 Minimum PCB Stack Up .......................................................................................... 3
3 PCB Stack Up Specifications .............................................................................................. 6
4 Placement Specifications .................................................................................................. 7
5 Bulk Bypass Capacitors .................................................................................................... 8
6 High-Speed Bypass Capacitors ........................................................................................... 9
7 Clock Net Class Definitions .............................................................................................. 10
8 Signal Net Class Definitions ............................................................................................. 10
9 DDR2/mDDR Signal Terminations ...................................................................................... 10
10 CK and ADDR_CTRL Routing Specification .......................................................................... 12
SPRAAL2D – November 2009 Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC 1
Submit Documentation Feedback
Copyright © 2009, Texas Instruments Incorporated
TMS320DM335 www.ti.com
11 DQS and DQ Routing Specification .................................................................................... 13

12 DQGATE Routing Specification ......................................................................................... 14
1 TMS320DM335
1.1 DDR2/mDDR Interface

This section provides the timing specification for the DDR2/mDDR interface as a PCB design and
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR
memory system without the need for a complex timing closure process. For more information regarding
guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing
Specification (SPRAAV0).
1.1.1 DDR2/mDDR Interface Schematic

Figure 1 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The
dual-memory system shown in Figure 2. Pin numbers for the DM335 can be obtained from the pin
description section of the TMS320DM335 Digital Media System-on-Chip (DMSoC) Data Manual
(SPRS528) and the DDR2/mDDR device pin numbers can be obtained from their device-specific data
sheets.
1.1.2 Compatible JEDEC DDR2/mDDR Devices

Table 1 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface.
Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade DDR2/mDDR
devices.
The DM335 also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case,
one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control
signals are shared just like regular dual chip memory configurations.
Table 1. Compatible JEDEC DDR2/mDDR Devices

No. Parameter Min Max Unit Notes
(1)
1 JEDEC DDR2/mDDR Device Speed Grade DDR2/mDDR- See Note
400
2 JEDEC DDR2/mDDR Device Bit Width x8 x16 Bits
3 JEDEC DDR2/mDDR Device Count 1 2 Devices
(1)
Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.
2 Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC SPRAAL2D – November 2009
www.ti.com TMS320DM335
1.1.3 PCB Stackup

The minimum stackup required for routing the DM335 is a six layer stack as shown in Table 2. Additional
layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB
footprint.
Table 2. DM335 Minimum PCB Stack Up

Layer Type Description
1 Signal Top Routing Mostly Horizontal
2 Plane Ground
3 Plane Power
4 Signal Internal Routing
5 Plane Ground
6 Signal Bottom Routing Mostly Vertical
Complete stack up specifications are provided in Table 3.
DMSoC DDR2/mDDR
ODT
DDR_DQ00 T DQ0
DDR_DQ07 T DQ7
DDR_DQM0 T LDM
DDR_DQS0 T LDQS
NC LDQS
DDR_DQ08 T DQ8
DDR_DQ15 T DQ15
DDR_DQM1 T UDM
DDR_DQS1 T UDQS
NC UDQS
DDR_BA0 T BA0
DDR_BA2 T BA2
DDR_A00 T A0
(C)
DDR_A13 T A13
DDR_CS T CS
DDR_CAS T CAS
DDR_RAS T RAS
DDR_WE T WE
DDR_CKE T CKE
DDR_CLK T CK
DDR_CLK T CK
DDR_ZN
50 Ω .5%
(A)
DDR_DQGATE0 T Vio 1.8
DDR_DQGATE1
(D)
VREF 0.1 μF
1 K Ω 1%
(D) (D)
DDR_VREF VREF
(B) (B) (B)
0.1 μF 0.1 μF 0.1 μF 1 K Ω 1%
0.1 μF
T Terminator, if desired. See terminator comments.

A Vio1.8 is the power supply for the DDR2/mDDR memories and the DM335 DDR2/mDDR interface.
B One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the
case of mDDR, these capacitors can be eliminated completely.
C Connect A13 signals together when present
D VREF applies in the case of DDR2 memories. For mDDR, the DMSoC DDR_VREF pin still needs to be connected to
the divider circuit.
Figure 1. DM335 DDR2/mDDR Single-Memory High Level Schematic
DMSoC
ODT
DDR_DQ00-07 T DQ0 - DQ7

BA0-BA2
(C)
A0-A13
DDR_DQM0 T DM
DDR2/mDDR
Lower Byte
DDR_DQS0 T DQS
NC DQS
CK
CK
CS
CAS
RAS
WE
CKE
(D)
VREF
DDR_BA0-BA2 T BA0-BA2
DDR_A00-A13 (C)
T A0-A13
DDR_CLK T CK
DDR_CLK T CK
DDR_CS T CS
DDR_CAS T CAS
DDR_RAS T RAS
DDR2/mDDR
Upper Byte
DDR_WE T WE
DDR_CKE T CKE
DDR_DQM1 T DM
DDR_DQS1 T DQS
NC DQS
DDR_DQ08-15 T DQ0 - DQ7 (A)
Vio 1.8
DDR_ZN ODT
50 Ω .5%
DDR_DQGATE0 T (D)
VREF
DDR_DQGATE1 0.1 μF
1 K Ω 1%
(D) (D)
DDR_VREF VREF
(B) (B) (B)
0.1 μF 0.1 μF 0.1 μF 1 K Ω 1%
0.1 μF
T Terminator, if desired. See terminator comments.

A Vio1.8 is the power supply for the DDR2/mDDR memories and the DM335 DDR2/mDDR interface.
B One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. In the
case of mDDR, these capacitors can be eliminated completely.
C Connect A13 signals together when present
D VREF applies in the case of DDR2 memories. For mDDR, the DMSoC DDR_VREF pin still needs to be connected to
the divider circuit.
Figure 2. DM335 DDR2/mDDR Dual-Memory High Level Schematic
Table 3. PCB Stack Up Specifications

No. Parameter Min Typ Max Unit Notes
1 PCB Routing/Plane Layers 6
2 Signal Routing Layers 3
3 Full ground layers under DDR2/mDDR routing Region 2
4 Number of ground plane cuts allowed within DDR routing region 0
5 Number of ground reference planes required for each DDR2/mDDR 1
routing layer
6 Number of layers between DDR2/mDDR routing layer and reference 0
ground plane
7 PCB Routing Feature Size 4 Mils
8 PCB Trace Width w 4 Mils
8 PCB BGA escape via pad size 18 Mils
9 PCB BGA escape via hole size 8 Mils
(1)
10 DMSoC Device BGA pad size See Note
(2)
11 DDR2/mDDR Device BGA pad size See Note
12 Single Ended Impedance, Zo 50 75 Ω
(3)
13 Impedance Control Z-5 Z Z+5 Ω See Note
(1)
Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DMSoC device BGA pad size.
(2)
Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.
(3)
Z is the nominal singled ended impedance selected for the PCB specified by item 12.
1.1.4 Placement
Figure 2 shows the required placement for the DM335 device as well as the DDR2/mDDR devices. The
dimensions for Figure 3 are defined in Table 4. The placement does not restrict the side of the PCB that
the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths
and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR
device is omitted from the placement.
A1
Y
DDR2/mDDR
OFFSET
Controller
DDR2/mDDR
Y
Device
Y
DM335
OFFSET
A1
Recommended DDR2/mDDR
Device Orientation
Figure 3. DM335 and DDR2/mDDR Device Placement
Table 4. Placement Specifications

(1) (2)
1 X 1750 Mils See Notes ,
(1) (2)
2 Y 1280 Mils See Notes ,
(1) (2)
3 Y Offset 650 Mils See Notes . ,
(3)
(4)
4 DDR2/mDDR Keepout Region See Note
(5)
5 Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout 4 w See Note
Region
(1)
See Figure 1 for dimension definitions.
(2)
Measurements from center of DMSoC device to center of DDR2/mDDR device.
(3)
For single memory systems it is recommended that Y Offset be as small as possible.
(4)
DDR2/mDDR Keepout region to encompass entire DDR2/mDDR routing area
(5)
Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing
layers by a ground plane.
1.1.5 DDR2/mDDR Keep Out Region

The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 4. The size of this region
varies with the placement and DDR routing. Additional clearances required for the keep out region are
shown in Table 4.
A1 DDR2/mDDR
Controller
DDR2/mDDR
Device
A1
Region should encompass all DDR2/mDDR circuitry and varies

depending on placement. Non-DDR2/mDDR signals should not be
routed on the DDR signal layers within the DDR2/mDDR keep out
region. Non-DDR2/mDDR signals may be routed in the region
provided they are routed on layers separated from DDR2/mDDR
signal layers by a ground layer. No breaks should be allowed in the
reference ground layers in this region. In addition, the 1.8 V power
plane should cover the entire keep out region.
Figure 4. DDR2/mDDR Keepout Region
1.1.6 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other
circuitry. Table 5 contains the minimum numbers and capacitance required for the bulk bypass capacitors.
Note that this table only covers the bypass needs of the DMSoC and DDR2/mDDR interfaces. Additional
bulk bypass capacitance may be needed for other circuitry.
Table 5. Bulk Bypass Capacitors

1 DVDD18 Bulk Bypass Capacitor Count 3 Devices See Note
(1)
2 DVDD18 Bulk Bypass Total Capacitance 30 μF

3 DDR#1 Bulk Bypass Capacitor Count 1 Devices See Note
(1)
4 DDR#1 Bulk Bypass Total Capacitance 22 μF

5 DDR#2 Bulk Bypass Capacitor Count 1 Devices See
Notes (1),
(2)
6 DDR#2 Bulk Bypass Total Capacitance 22 μF See Note

(2)
(1)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the
high-speed (HS) bypass caps.
(2)
Only used on dual-memory systems
1.1.7 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is
particularly important to minimize the parasitic series inductance of the HS bypass cap,
DMSoC/DDR2/mDDR power, and DMSoC/DDR2/mDDR ground connections. Table 6 contains the
specification for the HS bypass capacitors as well as for the power connections on the PCB.
1.1.8 Net Classes

Table 7 lists the clock net classes for the DDR2/mDDR interface. Table 8 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for
the termination and routing rules that follow.
Table 6. High-Speed Bypass Capacitors

(1)
1 HS Bypass Capacitor Package Size 0402 10 Mils See Note
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
(2)
3 Number of connection vias for each HS bypass capacitor 2 Vias See Note
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each DDR2/mDDR device power or ground balls 1 Vias
6 Trace length from DDR2/mDDR device power ball to connection via 35 Mils
(3)
7 DVDD18 HS Bypass Capacitor Count 10 Devices See Note
8 DVDD18 HS Bypass Capacitor Total Capacitance 1.2 μF
(3)
9 DDR#1 HS Bypass Capacitor Count 8 Devices See Note
10 DDR#1 HS Bypass Capacitor Total Capacitance 0.4 μF
11 DDR#2 HS Bypass Capacitor Count 8 Devices See Notes
(3) (4)
,
(4)
12 DDR#2 HS Bypass Capacitor Total Capacitance 0.4 μF See Note
(1)
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2)
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3)
These devices should be placed as close as possible to the device being bypassed.
(4)
Only used on dual-memory systems
Table 7. Clock Net Class Definitions

Clock Net Class DMSoC Pin Names
CK DDR_CLK/DDR_CLK
DQS0 DDR_DQS0
DQS1 DDR_DQS1
Table 8. Signal Net Class Definitions

Associated Clock Net
Clock Net Class Class DMSoC Pin Names
ADDR_CTRL CK DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,
DDR_CKE
DQ0 DQS0 DDR_DQ[7:0], DDR_DQM0
DQ1 DQS1 DDR_DQ[15:8], DDR_DQM1
DQGATE CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1
1.1.9 DDR2/mDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 9 shows the specifications for the series terminators.
Table 9. DDR2/mDDR Signal Terminations

(1)
1 CK Net Class 0 10 Ω See Note
(1)
2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes ,
(2) (3)
,
3 Data Byte Net Classes (DQS0-DQS1, DQ0-DQ1) 0 22 Zo Ω See Notes (1),
(2) (3) (4)
, , ,
(1)
4 DQGATE Net Class (DQGATE) 0 10 Zo Ω See Notes ,
(2) (3)
,
(1)
Only series termination is permitted, parallel or SST specifically disallowed.
(2)
Terminator values larger than typical only recommended to address EMI issues.
(3)
Termination value should be uniform across net class.
(4)
When no termination is used on data lines (0 Ωs), the DDR2/mDDR devices must be programmed to operate in 60% strength
mode.
1.1.10 VREF Routing

VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the DM335’s.
VREF is intended to be ½ the DDR2/mDDR power supply voltage and should be created using a resistive
divider as shown in Figure 1. Other methods of creating VREF are not recommended. Figure 5 shows the
layout guidelines for VREF.
VREF Bypass Capacitor
DDR2/mDDR Device
A1
VREF Nominal Minimum

Trace Width is 20 Mils DM335
Device
A1
Neck down to minimum in BGA escape

regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
Figure 5. VREF Routing and Topology
1.1.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
DDR2/mDDR
B
Controller
T
A
C
DM335
A1
Figure 6. CK and ADDR_CTRL Routing and Topology
(1)
Table 10. CK and ADDR_CTRL Routing Specification
No Parameter Min Typ Max Unit Notes
1 Center to center CK-CK spacing 2w
(1)
2 CK A to B/A to C Skew Length Mismatch 25 Mils See Note
3 CK B to C Skew Length Mismatch 25 Mils
(2)
4 Center to center CK to other DDR2/mDDR trace 4w See Note
spacing
(3)
5 CK/ADDR_CTRL nominal trace length CACLM-50 CACLM CACLM+50 Mils See Note
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
(2)
8 Center to center ADDR_CTRL to other DDR2/mDDR 4w See Note
trace spacing
(2)
9 Center to center ADDR_CTRL to other ADDR_CTRL 3w See Note
trace spacing
(1)
10 ADDR_CTRL A to B/A to C Skew Length Mismatch 100 Mils See Note
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1)
Series terminator, if used, should be located closest to DMSoC.
(2)
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
(3)
CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 7 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
DDR2/mDDR
Controller
DM335
T
E2
A1
T
E3
Figure 7. DQS and DQ Routing and Topology
(1)
Table 11. DQS and DQ Routing Specification
1 Center to center DQS-DQS spacing 2w
2 DQS E Skew Length Mismatch 25 Mils
(2)
3 Center to center DQS to other DDR2/mDDR trace spacing 4w See Note
(1)
4 DQS/DQ nominal trace length DQLM- DQL DQLM Mils See Notes ,
(3)
50 M +50
(3)
5 DQ to DQS Skew Length Mismatch 100 Mils See Note
(3)
6 DQ to DQ Skew Length Mismatch 100 Mils See Note
(2)
7 Center to center DQ to other DDR2/mDDR trace spacing 4w See Notes ,
(4)
(5)
8 Center to Center DQ to other DQ trace spacing 3w See Notes ,
(2)
(3)
9 DQ/DQS E Skew Length Mismatch 100 Mils See Note
(1)
Series terminator, if used, should be located closest to DDR.
(2)
Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and
routing congestion.
(3)
There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and
data byte 1.
(4)
DQ's from other DQS domains are considered other DDR2/mDDR trace.
(5)
DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
Figure 8 shows the routing for the DQGATE net classes. Table 12 contains the routing specification.
A1
FL
T
DDR2/mDDR
Controller
T DM335
A1
FH
Figure 8. DQGATE Routing
References www.ti.com
Table 12. DQGATE Routing Specification

1 DQGATE Length F CKB0B1 See Note
(1)
3 Center to center DQGATE to any other trace spacing 4w

4 DQS/DQ nominal trace length DQLM-50 DQLM DQLM+50 Mils
5 DQGATE Skew 100 Mils See Note
(2)
(1)
CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2)
Skew from CKB0B1
2 References
• TMS320DM335 Digital Media System-on-Chip (DMSoC) Data Manual (SPRS528)
• Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0)
• Flip Chip Ball Grid Array Package Reference Guide (SPRU811)
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Implementing Ddr2/Mddr PCB Layout On The Tms320Dm335 Dmsoc: Application Report

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Implementing Ddr2/Mddr PCB Layout On The Tms320Dm335 Dmsoc: Application Report

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Application Report

SPRAAL2D – November 2009

Implementing DDR2/mDDR PCB Layout on the

11 DQS and DQ Routing Specification .................................................................................... 13

1.1 DDR2/mDDR Interface

1.1.1 DDR2/mDDR Interface Schematic

1.1.2 Compatible JEDEC DDR2/mDDR Devices

Table 1. Compatible JEDEC DDR2/mDDR Devices

1.1.3 PCB Stackup

Table 2. DM335 Minimum PCB Stack Up

Complete stack up specifications are provided in Table 3.

T Terminator, if desired. See terminator comments.

DDR_DQ00-07 T DQ0 - DQ7

T Terminator, if desired. See terminator comments.

Table 3. PCB Stack Up Specifications

Figure 3. DM335 and DDR2/mDDR Device Placement

Table 4. Placement Specifications

1.1.5 DDR2/mDDR Keep Out Region

Region should encompass all DDR2/mDDR circuitry and varies

Figure 4. DDR2/mDDR Keepout Region

1.1.6 Bulk Bypass Capacitors

Table 5. Bulk Bypass Capacitors

2 DVDD18 Bulk Bypass Total Capacitance 30 μF

4 DDR#1 Bulk Bypass Total Capacitance 22 μF

6 DDR#2 Bulk Bypass Total Capacitance 22 μF See Note

1.1.7 High-Speed Bypass Capacitors

1.1.8 Net Classes

Table 6. High-Speed Bypass Capacitors

Table 7. Clock Net Class Definitions

Table 8. Signal Net Class Definitions

1.1.9 DDR2/mDDR Signal Termination

Table 9. DDR2/mDDR Signal Terminations

1.1.10 VREF Routing

VREF Nominal Minimum

Neck down to minimum in BGA escape

Figure 5. VREF Routing and Topology

1.1.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6. CK and ADDR_CTRL Routing and Topology

Figure 7. DQS and DQ Routing and Topology

Figure 8. DQGATE Routing

Table 12. DQGATE Routing Specification

3 Center to center DQGATE to any other trace spacing 4w

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