CS4227

Six Channel, 20-Bit Codec

Features Description
l Stereo 20-bit A/D Converters The CS4227 is a single-chip codec providing stereo an-
l Six 20-bit D/A Converters alog-to-digital and six digital-to-analog converters using
delta-sigma conversion techniques. This +5 V device
l 108 dB DAC Signal-to-Noise Ratio (EIAJ) also contains volume controls that are independently se-
l Mono 20-bit A/D Converter lectable for each of the six D/A channels. Applications
l Programmable Input Gain & Output include Dolby® Pro-logic™, THX®, and Dolby Digital AC-
Attenuation 3™ home theater systems, DSP based car audio sys-
tems, and other multi-channel applications.
l On-chip Anti-aliasing and Output Smoothing
Filters ORDERING INFORMATION
CS4227-KQ -10° to +70° C 44-pin TQFP
l De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
CS4227-BQ -40° to +85° C 44-pin TQFP
CDB4227 Evaluation Board
I

SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS SPI/I2C VD+ VA+

Voltage
PDN Control Port Reference CMOUT

DAC#1 Volume AOUT1

Control
LRCK
DAC#2 Volume AOUT2
SCLK
Control
Analog Low Pass and

SDIN1
Digital Filters
Serial Audio Data Interface

Output Stage

DAC#3 Volume AOUT3

SDIN2
Control
SDIN3
DAC#4 Volume AOUT4
Control
DAC#5 Volume AOUT5
Control

DAC#6 Volume AOUT6

SDOUT1 Control
SDOUT2 Mono
AINAUX
Digital Filters

ADC
OVL AIN1L
MUX Left
Input
Gain

AIN1R
Input MUX

ADC
Right AIN2L
ADC AIN2R
DEM DEM AIN3L
Clock Osc/ AIN3R
Auxiliary Input
Divider AGND1
AGND2
CLKOUT XTI XTO HOLD DATAUX LRCKAUX SCLKAUX DGND1 DGND2

This document contains information for a new product.

Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 1999 SEP ‘99

P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved)
(512) 445 7222 FAX: (512) 445 7581 DS281PP2
http://www.cirrus.com 1
 CS4227

TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ANALOG CHARACTERISTICS ................................................................................................ 4
SWITCHING CHARACTERISTICS .......................................................................................... 6
SWITCHING CHARACTERISTICS - CONTROL PORT........................................................... 8
ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10
RECOMMENDED OPERATING CONDITIONS ..................................................................... 10
DIGITAL CHARACTERISTICS ............................................................................................... 10
2. FUNCTIONAL DESCRIPTION ............................................................................................... 12
2.1 Overview .......................................................................................................................... 12
2.2 Analog Inputs ................................................................................................................... 12
2.2.1 Line Level Inputs ................................................................................................. 12
2.2.2 Adjustable Input Gain .......................................................................................... 13
2.2.3 High Pass Filter ................................................................................................... 13
2.3 Analog Outputs ................................................................................................................ 13
2.3.1 Line Level Outputs .............................................................................................. 13
2.3.2 Output Level Attenuator ...................................................................................... 14
2.4 Clock Generation ............................................................................................................. 14
2.4.1 Clock Source ....................................................................................................... 14
2.4.2 Master Clock Output ........................................................................................... 14
2.4.3 Synchronization ................................................................................................... 14
2.5 Digital Interfaces .............................................................................................................. 15
2.5.1 Audio DSP Serial Interface Signals ..................................................................... 15
2.5.2 Audio DSP Serial Interface Formats ................................................................... 15
2.5.3 Auxiliary Audio Port Signals ................................................................................ 15
2.5.4 Auxiliary Audio Port Formats ............................................................................... 15
2.6 Control Port Signals ......................................................................................................... 17
2.6.1 SPI Mode ............................................................................................................ 17
2.6.2 I2C® Mode ........................................................................................................... 18
2.6.3 Control Port Bit Definitions .................................................................................. 18
2.7 Power-up/Reset/Power Down Mode ................................................................................ 18
2.8 DAC Calibration ............................................................................................................... 19
2.9 De-Emphasis ................................................................................................................... 19
2.10 Hold Function ................................................................................................................. 19

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

Dolby is a registered trademark of Dolby Labratories Licensing Corporation.

Pro Logic, and AC-3 are trademarks of Dolby Labratories Licensing Corporation.
THX is a registered trademark of LucasArts Entertainment Company.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.

2 DS281PP2
 CS4227

2.11 Power Supply, Layout, and Grounding .......................................................................... 19

2.12 ADC and DAC Filter Response Plots ............................................................................ 20
3. PIN DESCRIPTIONS .............................................................................................................. 29
4. PARAMETER DEFINITIONS .................................................................................................. 33
5. PACKAGE DIMENSIONS ...................................................................................................... 34

LIST OF FIGURES
Figure 1. Audio Ports Master Mode Timing..................................................................................... 7
Figure 2. Audio Ports Slave Mode and Data I/O Timing ................................................................. 7
Figure 3. Control Port SPI Mode ..................................................................................................... 8
Figure 4. Control Port I2C Mode...................................................................................................... 9
Figure 5. Recommended Connection Diagram............................................................................. 11
Figure 6. Optional Line Intput Buffer ............................................................................................. 12
Figure 7. Butterworth Filters.......................................................................................................... 13
Figure 8. Audio DSP and Auxiliary Port Data Input Formats ........................................................ 16
Figure 9. Audio DSP Port Data Output Formats ........................................................................... 16
Figure 10. One Data Line Modes .................................................................................................. 16
Figure 11. Control Port Timing, SPI Mode .................................................................................... 17
Figure 12. Control Port Timing, I2C® Mode................................................................................... 18
Figure 13. De-emphasis Curve. .................................................................................................... 19
Figure 14. Suggested Layout Guideline........................................................................................ 20
Figure 15. 20-bit ADC Filter Response ......................................................................................... 21
Figure 16. 20-bit ADC Passband Ripple ....................................................................................... 21
Figure 17. 20-bit ADC Transition Band ......................................................................................... 21
Figure 18. DAC Frequency Response .......................................................................................... 21
Figure 19. DAC Passband Ripple ................................................................................................. 21
Figure 20. DAC Transition Band ................................................................................................... 21

LIST OF TABLES
Table 1. Single-ended vs Differential Input Pin Assignments .............................................................. 12
Table 2. High Pass Filter Characteristics ............................................................................................ 13
Table 3. DSP Serial Input Ports........................................................................................................... 15

DS281PP2 3
 CS4227

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = +5 V; Full Scale Input Sine wave, 997 kHz;
Fs = 44.1 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figure 5; SPI mode,
Format 3, unless otherwise specified.)
CS4227-KQ CS4227-BQ
Parameter Symbol Min Typ Max Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified.
ADC Resolution Stereo Audio channels 16 - 20 16 - 20 Bits
Mono channel 16 - 20 16 - 20 Bits
Total Harmonic Distortion THD 0.003 - 0.003 - %
Dynamic Range (A weighted, Stereo) 92 95 - 90 93 - dB
(unweighted, Stereo) - 92 - - 90 - dB
(A weighted, Mono) 89 - - 87 - - dB
Total Harmonic -1 dB, Stereo (Note 1) THD+N - -88 -82 - -86 -80 dB
Distortion + Noise -1 dB, Mono (Note 1) - - -72 - - -70 dB
Interchannel Isolation - 90 - - 90 - dB
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Programmable Input Gain Span 8 9 10 8 9 10 dB
Gain Step Size 2.7 3 3.3 2.7 3 3.3 dB
Offset Error (with high pass filter) - - 0 - - 0 LSB
Full Scale Input Voltage (Single Ended): 0.90 1.0 1.10 0.90 1.0 1.10 Vrms
Gain Drift - 100 - - 100 - ppm/°C
Input Resistance (Note 2) 10 - - 10 - - kΩ
Input Capacitance - - 15 - - 15 pF
CMOUT Output Voltage - 2.3 - - 2.3 - V
A/D Decimation Filter Characteristics
Passband (Note 3) 0.02 - 20.0 0.02 - 20.0 kHz
Passband Ripple - - 0.01 - - 0.01 dB
Stopband (Note 3) 27.56 - 5617.2 27.56 - 5617.2 kHz
Stopband Attenuation (Note 4) 80 - - 80 - - dB
Group Delay (Fs = Output Sample Rate) (Note 5) tgd - 15/Fs - - 15/Fs - s
Group Delay Variation vs. Frequency ∆ tgd - - 0 - - 0 µs

Notes: 1. Referenced to typical full-scale differential input voltage (2Vrms).

2. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input resistance.
The input resistance will vary with gain value selected, but will always be greater than the min. value
specified.
3. Filter characteristics scale with output sample rate.
4. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is
no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 MHz ±20.0 kHz
where n = 0,1,2,3...).
5. Group delay for Fs = 44.1 kHz, tgd = 15/44.1 kHz = 340 µs

4 DS281PP2
 CS4227

ANALOG CHARACTERISTICS (Continued)

CS4227-KQ CS4227-BQ
Parameter Symbol
Min Typ Max Min Typ Max Units
High Pass Filter Characteristics
Frequency Response: -3 dB (Note 3) - 3.4 - - 3.4 - Hz
-0.13 dB - 20 - - 20 - Hz
Phase Deviation @ 20 Hz (Note 3) - 10 - - 10 - Deg.
Passband Ripple - - 0 - - 0 dB
Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified.
DAC Resolution 16 - 20 16 - 20 Bits
Signal-to-Noise/Idle (DAC muted, A weighted) 101 108 - 99 106 - dB
Channel Noise
Dynamic Range (DAC not muted, A weighted) 93 98 - 91 96 - dB
(DAC not muted, unweighted) - 95 - - 93 - dB
Total Harmonic Distortion THD - 0.003 - - 0.003 - %
Total Harmonic Distortion + Noise (Stereo) THD+N - -88 -83 - -86 -81 dB
Interchannel Isolation - 90 - - 90 - dB
Interchannel Gain Mismatch - 0.1 - - 0.1 - dB
Attenuation Step Size (All Outputs) 0.7 1 1.3 0.7 1 1.3 dB
Programmable Output Attenuation Span -84 -86 - -84 -86 - dB
Offset Voltage (relative to CMOUT) - ±15 - - ±15 - mV
Full Scale Output Voltage 0.92 1.0 1.08 0.92 1.0 1.08 Vrms
Gain Drift - 100 - - 100 - ppm/°C
Out-of-Band Energy (Fs/2 to 2Fs) - -60 - - -60 - dBFs
Analog Output Load Resistance: 10 - - 10 - - kΩ
Capacitance: - - 100 - - 100 pF
Combined Digital and Analog Filter Characteristics
Frequency Response 10 Hz to 20 kHz - ±0.1 - - ±0.1 - dB
Deviation from Linear Phase - ±0.5 - - ±0.5 - Deg.
Passband: to 0.01 dB corner (Notes 6, 7) 0 - 20.0 0 - 20.0 kHz
Passband Ripple (Note 7) - - ±0.01 - - ±0.01 dB
Stopband (Notes 6 ,7) 24.1 - - 24.1 - - kHz
Stopband Attenuation (Note 8) 70 - - 70 - - dB
Group Delay (Fs = Input Word Rate) (Note 5) tgd - 16/Fs - - 16/Fs - s
Analog Loopback Performance
Signal-to-noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K - 71 - - 71 - dB
Power Supply
Power Supply Current Operating - 90 113 - 90 115 mA
Power Down - 1 3 - 1 3 mA
Power Supply Rejection (1 kHz, 10 mVrms) - 45 - - 45 - dB
Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,
the 0.05 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs.
7. Digital filter characteristics.
8. Measurement bandwidth is 10 Hz to 3Fs.
Specifications are subject to change without notice

DS281PP2 5
 CS4227

SWITCHING CHARACTERISTICS (TA = 25 °C; VA+, VD+ = +5 V ±5%; outputs loaded with 30 pF.)
Parameter Symbol Min Typ Max Unit
Audio ADC’s and DAC’s Sample Rate Fs 4 - 50 kHz
XTI Frequency XTI = 256, 384, or 512 Fs 1.024 - 26 MHz
XTI Pulse Width High XTI = 512 Fs 10 - - ns
XTI = 384 Fs 21 - -
XTI = 256 Fs 31 - -
XTI Pulse Width Low XTI = 512 Fs 10 - - ns
XTI = 384 Fs 21 - -
XTI = 256 Fs 31 - -
XTI Jitter Tolerance - 500 - ps
CLKOUT Jitter (Note 9) - 200 - psRMS
CLKOUT Duty Cycle (high timer/cycle time) (Note 10) 40 50 60 %
PDN Low Time (Note 11) 500 - - ns
SCLK Falling Edge to SDOUT Output Valid DSCK = 0 tdpd - - Note 12 ns
LRCK edge to MSB valid tlrpd - - 40 ns
SDIN Setup Time Before SCLK Rising Edge DSCK = 0 tds - - 25 ns
SDIN Hold Time After SCLK Rising Edge DSCK = 0 tdh - - 25 ns
Master Mode
SCLK Falling to LRCK Edge DSCK = 0 tmslr - ±10 - ns
SCLK Period (Note 14) - - - - -
SCLK Duty Cycle - 50 - %
Slave Mode
SCLK Period tsckw Note 13 - - ns
SCLK High Time tsckh 40 - - ns
SCLK Low Time tsckl 40 - - ns
SCLK Rising to LRCK Edge DSCK = 0 tlrckd 20 - - ns
LRCK Edge to SCLK Rising DSCK = 0 tlrcks 40 - - ns
Notes: 9. CLKOUT Jitter is for 256x Fs selected as output frequency measured from falling edge to falling edge.
Jitter is greater for 384x Fs and 512x Fs as selected output frequency.
10. For CLKOUT frequency equal to 1x Fs, 384x Fs, and 512x Fs. See Master Clock Output section.
11. After powering up the CS4227, PDN should be held low for 1 ms to allow the power supply to settle.
1
12. --------------------- + 20
( 384 )Fs
1
13. ---------------------
( 128 )Fs

14. 1
-------------------
( 256 )Fs

6 DS281PP2
 CS4227

SCLK*
SCLKAUX*
(output)

t mslr

LRCK
LRCKAUX
(output)

SDOUT1
SDOUT2

Figure 1. Audio Ports Master Mode Timing

LRCK
LRCKAUX
(input) t lrckd t lrcks t sckh t sckl

SCLK*
SCLKAUX*
(input)
t sckw
SDIN1
SDIN2
SDIN3
DATAUX
t lrpd t ds t dh t dpd

SDOUT1 MSB MSB-1

SDOUT2

*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0.

SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.

Figure 2. Audio Ports Slave Mode and Data I/O Timing

DS281PP2 7
 CS4227

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VA+, VD+ = +5 V ±5%;

Inputs: logic 0 = DGND, logic 1 = VD+; CL = 30 pF)
Parameter Symbol Min Max Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency fsck - 6 MHz
CS High Time Between Transmissions tcsh 1.0 - µs
CS Falling to CCLK Edge tcss 20 - ns
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCL Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 15) tdh 15 - ns
CCLK Falling to CDOUT stable tpd - 45 ns
Rise Time of CDOUT tr1 - 25 ns
Fall Time of CDOUT tf1 - 25 ns
Rise Time of CCLK and CDIN (Note 16) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 16) tf2 - 100 ns

Notes: 15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For FSCK < 1 MHz.

CS
t css t scl t sch t csh

CCLK

t r2 t f2

CDIN

t dsu t t pd
dh

CDOUT

Figure 3. Control Port SPI Mode

8 DS281PP2
 CS4227

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 °C; VA+, VD+ = +5 V ±5%;

Inputs: logic 0 = DGND, logic 1 = VD+; CL = 30 pF)
Parameter Symbol Min Max Unit
I2C® Mode (SPI/I2C = 1) (Note 17)
SCL Clock Frequency fscl - 100 kHz
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low Time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time for SCL Falling (Note 18) thdd 0 - µs
SDA Setup Time to SCL Rising tsud 250 - ns
Rise Time of Both SDA and SCL Lines tr - 1 µs
Fall Time of Both SDA and SCL Lines tf - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs

Notes: 17. I2C® is a registered trademark of Philips Semiconductors.

18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Repeated
Stop Start Start Stop

SDA
t buf t hdst t high t tf
hdst t susp

SCL

t t t sud t sust tr
low hdd

Figure 4. Control Port I2C Mode

DS281PP2 9
 CS4227

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltage with respect to 0 V.)
Parameter Symbol Min Max Unit
Power Supplies Digital VD+ -0.3 6.0 V
Analog VA+ -0.3 6.0
Input Current (Note 19) - ±10 mA
Analog Input Voltage (Note 20) -0.7 (VA+) + 0.7 V
Digital Input Voltage (Note 20) -0.7 (VD+) + 0.7 V
Ambient Temperature (Power Applied) -55 +125 °C
Storage Temperature -65 +150 °C

Notes: 19. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
20. The maximum over or under voltage is limited by the input current.
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltage with respect to

0 V.)
Parameter Symbol Min Typ Max Unit
Power Supplies Digital VD+ 4.75 5.0 5.25 V
|VA+ - VD+| < 0.4 V Analog VA+ 4.75 5.0 5.25
Operating Ambient Temperature TA -10 25 70 °C

DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = +5 V ±5%)

Parameter Symbol Min Max Unit
High-level Input Voltage (Except XTI) VIH 2.8 (VD+) + 0.3 V
Low-level Input Voltage (Except XTI) VIL -0.3 0.8 V
High-level Output Voltage (Except XTO) VOH (VD+) - 1.0 - V
Low-level Output Voltage (Except XTO) VOL - 0.4 V
Input Leakage Current (Digital Inputs) - 10 µA
Output Leakage Current (High-Impedance Digital Outputs) - 10 µA

10 DS281PP2
 CS4227

Ferrite Bead
2.0 Ω
+5V
Supply + 1 µF 0.1 µF + 1 µF 0.1 µF

19 40
VA+ VD+
16 21 ANALOG
To Optional CMOUT AOUT1
Input and 1 µF + FILTER
Output Buffers

22 ANALOG
AOUT2
10 µF * 14 FILTER
AIN1L

10 µF * 13
AIN1R
CS4227
From Optional Input Buffer

23 ANALOG
AOUT3
10 µF * 11 FILTER
AIN2L

10 µF * 12
AIN2R
24 ANALOG
AOUT4
10 µF * 10 FILTER
AIN3L

10 µF * 9
AIN3R
25 ANALOG
AOUT5
10 µF * 15 FILTER
AINAUX

26 ANALOG
AOUT6
FILTER
27
DEM
2
HOLD
3
Digital SCL/CCLK
Audio 1 4
DATAUX SDA/CDOUT
Source RS 44 6
LRCKAUX AD0/CS Microcontroller
RS 43 5
SCLKAUX AD1/CDIN

8
Mode PDN
Setting 7 34
SPI/I2C SDIN1
33
SDIN2
32
SDIN3
36
SDOUT1 Audio
35 DSP
SDOUT2
37 RS
LRCK
38 RS
R S = 50 Ω SCLK
31
CLKOUT
30
OVL
All unused digital inputs
should be tied to 0V.
AGND1, 2 DGND1, 2 NC XTO XTI
Unused analog inputs
should be left unconnected. 18 20 41 39 17 29 28

* Optional if analog inputs biased External

to within 1% of CMOUT Clock Input
C1** C2**

Figure 5. Recommended Connection Diagram

(Also see recommended layout diagrams, Figure 14)

DS281PP2 11
 CS4227

2. FUNCTIONAL DESCRIPTION
2.1 Overview 100 pF
The CS4227 has 2 channels of 20-bit analog-to-
digital conversion and 6 channels of 20-bit digital- 3.3 µF
20 k 10 k
Line In -
to-analog conversion. A mono 20-bit ADC is also Right
AINxR
provided. All ADCs and DACs are delta-sigma +
Example
converters. The stereo ADC inputs have adjustable Op-Amps are
5k
MC34074 or
input gain, while the DAC outputs have adjustable MC33078
CMOUT

output attenuation. 0.47 µF

Digital audio data received by the DACs and trans-

mitted from the ADCs is communicated over sepa- 3.3 µF +
Line In 20 k AINxL
-
rate serial ports, allowing concurrent writing to and Left
10 k
reading from the device. The CS4227 functions are
controlled via a serial microcontroller interface. 100 pF
Figure 1 shows the recommended connection dia-
gram for the CS4227. Figure 6. Optional Line Intput Buffer

2.2 Analog Inputs The analog inputs may also be configured as differ-
ential inputs. This is enabled by setting bits
2.2.1 Line Level Inputs
AIS1/0 = 3. In the differential configuration, the
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L left channel inputs reside on pins 10 and 11, and the
and AINAUX are the line level input pins (See Fig- right channel inputs reside on pins 12 and 13 as de-
ure 5). These pins are internally biased to the scribed in the table below. In differential mode, the
CMOUT voltage (nominally 2.3 V). A 10 µF DC full scale input level is 2 Vrms.
blocking capacitor allows signals centered around
0 V to be input. Figure 6 shows an optional dual op Single-ended Pin # Differential Inputs
amp buffer which combines level shifting with a AIN3L Pin 10 AINL+
AIN3R Pin 9 unused
gain of 0.5 to attenuate the standard line level of
AIN2L Pin 11 AINL-
2 Vrms to 1 Vrms. The CMOUT reference level is AIN2R Pin 12 AINR-
used to bias the op-amps to approximately one half AIN1L Pin 14 unused
the supply voltage. With this input circuit, the AIN1R Pin 13 AINR+
10 µF DC blocking caps in Figure 5 may be omit-
ted. Any remaining DC offset will be removed by Table 1. Single-ended vs Differential Input Pin
Assignments
the internal high-pass filters.
The analog signal is input to the mono ADC via the
Selection of the stereo input pair for the 20-bit AINAUX pin.
ADC's is accomplished by setting the AIS1/0 bits,
Independent Muting of both the stereo ADC's and
which are accessible in the ADC Control Byte. On-
the mono ADC is possible through the ADC Con-
chip anti-aliasing filters follow the input mux, pro-
trol Byte (#11) with the MUTR, MUTL and
viding anti-aliasing for all input channels.
MUTM bits.

12 DS281PP2
 CS4227

2.2.2 Adjustable Input Gain 2.3 Analog Outputs

The signals from the line inputs are routed to a pro- 2.3.1 Line Level Outputs
grammable gain circuit which provides up to 9 dB
The CS4227 contains an on-chip buffer amplifier
of gain in 3 dB steps, adjustable through the Input
producing single-ended outputs capable of driving
Control Byte. Right and left channel gain settings
10 kΩ loads. Each output (AOUT 1-6) will produce
are controlled independently with the GNR1/0 and
a nominal 2.83 Vpp (1 Vrms) output with a 2.3 volt
GNL1/0 bits. To minimize audible artifacts, level
quiescent voltage for a full scale digital input. The
changes should be done with the channel muted, as
recommended off-chip analog filter is a 2nd order
the changes occur immediately on register updates.
Butterworth with a -3 dB corner at Fs (see
The ADC Status Report Byte provides feedback of Figure 7). This filter provides out-of-band noise at-
input level for each ADC channel. This register tenuation along with a gain of 2, providing a 2 Vrms
continously monitors the ADC output and records output signal. A 3rd order Butterworth filter with a
the peak output level since the last register read. -3 dB corner at 0.75 Fs can be used if greater out of
Reading this register causes it to reset to 0, where- band noise filtering is desired. The CS4227 DAC
upon peak monitoring begins again. interpolation filter is a linear phase design which
2.2.3 High Pass Filter has been pre-compensated for an external 2nd or-
der Butterworth filter to provide a flat frequency re-
The operational amplifiers in the input circuitry sponse and linear phase response over the
driving the CS4227 may generate a small DC offset passband. If this filter is not used, small frequency
into the A/D converter. The CS4227 includes a response magnitude and phase errors will occur.
high pass filter after the decimator to remove any
DC offset which could result in recording a DC lev- 150pF

el, possibly yielding "clicks" when switching be- 22 kΩ

tween devices in a multichannel system. 11 kΩ 3.9 kΩ

_

The characteristics of this first-order high pass fil- 1000pF

+
Example
ter are outlined below for an output sample rate of Op-Amps
are
5 kΩ
44.1 kHz. This filter response scales linearly with CMOUT MC33078

sample rate. 0.47 µF

Frequency Response -3dB @ 3.4 Hz 2-Pole Butterworth Filter

-0.13 dB @ 20 Hz
Phase Deviation 10 degrees @ 20 Hz
560 pF
Passband Ripple None 5.85 kΩ

Table 2. High Pass Filter Characteristics 1.1 kΩ 4.75 kΩ 1.21 kΩ

_
AOUT
+
5600 pF 5600 pF

5 kΩ
CMOUT

0.47 µF

3-Pole Butterworth Filter

Figure 7. Butterworth Filters

DS281PP2 13
 CS4227

2.3.2 Output Level Attenuator 2.4.1 Clock Source

The DAC outputs are each routed through an atten- The CS4227 requires a high frequency master
uator which is adjustable in 1 dB steps. Output at- clock to run the internal logic. The clock enable bit
tenuation is available through the Output (CE) must be set to 0 after power-up of the device
Attenuator Data Bytes. Level changes are imple- (see Power-up/Reset/Power Down Mode section).
mented such that the noise is attenuated by the A high frequency crystal can be connected to XTI
same amount as the signal (equivalent to using an and XTO, or a high frequency clock can be applied
analog attenuator after the signal source) until the to XTI. This high frequency clock can be 256 Fs,
residual output noise is equal to the noise floor in 384 Fs or 512 Fs; this is set by the CI0/1 bits in the
the mute state. Level changes only take effect on Clock Mode Byte (#1). When using the on-chip
zero crossings to minimize audible artifacts. If crystal oscillator, external loading capacitors are
there is no zero crossing, then the requested level required (see Figure 5). High frequency crystals
change will occur after a time-out period between (>8 MHz) should be parallel resonant, fundamental
512 and 1024 frames (11.6 ms to 23.2 ms at mode and designed for 20 pF loading (equivalent to
44.1 kHz frame rate). There is a separate zero 40 pF to ground on each leg).
crossing detector for each channel. Each ACC bit
in the DAC Status Report Byte provides informa-
2.4.2 Master Clock Output
tion on when a volume control change has taken ef- CLKOUT is a master clock output provided to al-
fect. This bit goes high when a new setting is low synchronization of external components.
loaded and returns low when it has taken effect. Available CLKOUT frequencies of 1 Fs, 256 Fs,
Volume control changes can be instantaneous by 384 Fs, and 512 Fs, are selectable by the CO0/1 bits
setting the Zero Crossing Disable (ZCD) bit in the of the Clock Mode Byte.
DAC Control Byte (#3) to 1. Generation of CLKOUT for 384 Fs and 512 Fs is
Each output can be independently muted via mute accomplished with an on chip clock multiplier and
control bits, MUT6-1, in the DAC Control Byte may contain clock jitter. The source of the 256 Fs
(#3). The mute also takes effect on a zero-crossing CLKOUT is a divided down clock from the
or after a timeout. In addition, the CS4227 has an XTI/XTO input. If 384 Fs is chosen as the input
optional mute on consecutive zeros feature, where clock at XTI and 256 Fs is chosen as the output,
all DAC outputs will mute if they receive between CLKOUT will have approximately a 33% duty cy-
512 and 1024 consecutive zeros (or -1 code) on all cle. In all other cases CLKOUT will typically have
six channels. A single non-zero value will unmute a 50% duty cycle.
the DAC outputs. This feature can be disabled with
2.4.3 Synchronization
the MUTC bit in the DAC Control Byte (#3).
The DSP port and Auxiliary port must operate syn-
2.4 Clock Generation chronously to the CS4227 clock source. The serial
The master clock to operate the CS4227 may be port will force a reset of the data paths in an attempt
generated by using the on-chip inverter and an ex- to resynchronize if non-synchronous data is input
ternal crystal or by using an external clock source. to the CS4227. It is advisable to mute the DACs
If the active clock source stops for 10 µs, the when changing from one clock source to another to
CS4227 will enter a power down state. In all modes avoid the output of undesirable audio signals as the
it is required to have SCLK and LRCK synchro- CS4227 resynchronizes.
nous to the selected master clock.

14 DS281PP2
 CS4227

2.5 Digital Interfaces DAC Inputs

There are 2 digital audio interface ports: the audio SDIN1 left channel DAC #1
right channel DAC #2
DSP port and the auxiliary digital audio port. The single line All 6 DAC channels
serial data is represented in 2’s complement format SDIN2 left channel DAC #3
with the MSB-first in all formats. right channel DAC #4
SDIN3 left channel DAC #5
2.5.1 Audio DSP Serial Interface Signals right channel DAC #6
The serial interface clock, SCLK, is used for trans- Table 3. DSP Serial Input Ports
mitting and receiving audio data. The active edge
of SCLK is chosen by setting the DSCK bit in the 2.5.2 Audio DSP Serial Interface Formats
DSP Port Mode Byte (#14). SCLK can be generat- The audio DSP port supports 7 alternate formats,
ed by the CS4227 (master mode) or it can be input shown in Figures 8, 9, and 10. These formats are
from an external SCLK source (slave mode). Mode chosen through the DSP Port Mode Byte (#14) with
selection is set with the DMS1/0 bits in the DSP the DDF2/1/0 bits.
Port Mode Byte (#14). The number of SCLK cy- Formats 5 and 6 are single line data modes where
cles in one system sample period is programmable all DAC channels are combined onto a single input
to be 32, 48, 64, or 128 by setting the DCK1/0 bits and all ADC channels are combined onto a single
in the DSP Port Mode Byte (#14). When SCLK is output. Format 6 is available in master mode only.
an input, 64 SCLK’s per system sample period is See Figure 10.
not recommended, due to potential interference ef-
fects; if possible 128 SCLK’s per sample period 2.5.3 Auxiliary Audio Port Signals
should be used instead. For master mode, bursting The auxiliary port provides an alternate way to in-
of a 128 Fs clock is preferrable over evenly distrib- put digital audio signals into the CS4227. This port
uted clocks. consists of clock, data and left/right clock pins
The Left/Right clock (LRCK) is used to indicate named, SCLKAUX, DATAUX and LRCKAUX.
left and right data and the start of a new sample pe- The Auxiliary Audio Port input is output on
riod. It may be output from the CS4227, or it may SDOUT1 when IS is set to 1 or 2 in the ADC Con-
be generated from an external controller. The fre- trol Byte. Additionally, setting IS to 2 routes the
quency of LRCK must be equal to the system sam- stereo ADC outputs to SDOUT2. There is approx-
ple rate, Fs. imately a two frame delay from DATAUX to
SDOUT1. When the auxiliary port is used, the fre-
SDIN1, SDIN2, and SDIN3 are the data input pins,
quency of LRCKAUX must be equal to the system
each of which drives a pair of DACs. SDOUT1 and
sample rate, Fs, but no particular phase relationship
SDOUT2 can carry the output data from the two
is required.
20-bit ADC’s, the mono ADC and the auxiliary dig-
ital audio port. Selection depends on the IS1/0 bits De-emphasis can be performed on input data to the
in the ADC control byte (#11). The audio DSP port auxiliary audio port; this is controlled by the Aux-
may also be configured so that all 6 DAC’s data is iliary Port Control Byte (#16).
input on SDIN1, and all 3 ADC’s data is output on
2.5.4 Auxiliary Audio Port Formats
SDOUT1. Table 3 outlines the serial interface
ports. Input data on DATAUX is clocked into the part by
SCLKAUX using the format selected in the Auxil-
iary Port Mode Byte. The auxiliary audio port sup-

DS281PP2 15
 CS4227

FORMAT 0, 1, 2: LRCK Left Right

Format 0: M = 20
SCLK
Format 1: M = 18
Format 2: M = 16 SDIN LSB MSB LSB MSB LSB

M SCLKs M SCLKs

FORMAT 3: LRCK Left Right

SCLK
SDIN MSB LSB MSB LSB MSB

FORMAT 4: LRCK Left Right

SCLK
SDIN MSB LSB MSB LSB

Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.

Figure 8. Audio DSP and Auxiliary Port Data Input Formats

FORMAT 0, 1, 2: LRCK Left Right

Format 0: M = 20
SCLK
Format 1: M = 18
Format 2: M = 16 SDOUT LSB MSB LSB MSB LSB

M SCLKs M SCLKs

FORMAT 3: LRCK Left Right

SCLK
SDOUT MSB LSB MSB LSB MSB

FORMAT 4: LRCK Left Right

SCLK
SDOUT MSB LSB MSB LSB

Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.

Figure 9. Audio DSP Port Data Output Formats

64 SCLKS 64 SCLKS

FORMAT 5: LRCK
SCLK
SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
DAC #1 DAC #3 DAC #5 DAC #2 DAC #4 DAC #6
20 clks 20 clks 20 clks 20 clks 20 clks 20 clks
SDOUT1 SDOUT1 SDOUT2 SDOUT1 SDOUT2
20 clks 20 clks 20 clks 20 clks

128 SCLKS 128 SCLKS

FORMAT 6: LRCK
(Master Mode Only) SCLK
SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

DAC #1 DAC #3 DAC #5 DAC #2 DAC #4 DAC #6

32 clks 32 clks 32 clks 32 clks 32 clks 32 clks
SDOUT1 SDOUT1 SDOUT2 SDOUT1 SDOUT2
32 clks 32 clks 32 clks 32 clks

Figure 10. One Data Line Modes

16 DS281PP2
 CS4227

CS

CCLK
CHIP CHIP
ADDRESS MAP DATA ADDRESS
0010000 R/W MSB LSB 0010000
CDIN R/W

byte 1 byte n

CDOUT MSB LSB MSB LSB

High Impedance
MAP = Memory Address Pointer

Figure 11. Control Port Timing, SPI Mode

ports the same 5 formats as the audio DSP port in Figure 11 shows the operation of the control port in
multi-data line mode. LRCKAUX is used to indi- SPI mode. To write to a register, bring CS low. The
cate left and right data samples, and the start of a first 7 bits on CDIN form the chip address, and they
new sample period. SCLKAUX and LRCKAUX must be 0010000. The eighth bit is a read/write in-
may be output from the CS4227, or they may be dicator (R/W), which should be low to write. The
generated from an external source, as set by the next 8 bits form the Memory Address Pointer
AMS1/0 control bits in the Auxiliary Port Mode (MAP), which is set to the address of the register
Byte (#15). that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
2.6 Control Port Signals MAP. During writes, the CDOUT output stays in
The control port is used to load all the internal set- the high impedance state. It may be externally
tings. The operation of the control port may be pulled high or low with a 47 kΩ resistor.
completely asynchronous with the audio sample
The CS4227 has a MAP auto increment capability,
rate. However, to avoid potential interference prob-
enabled by the INCR bit in the MAP register. If
lems, the control port pins should remain static if
INCR is a zero, then the MAP will stay constant for
no operation is required.
successive reads or writes. If INCR is set to a 1,
The control port has 2 modes: SPI and I2C®, with then MAP will auto increment after each byte is
the CS4227 as a slave device. The SPI mode is se- read or written, allowing block reads or writes of
lected by setting the SPI/I2C pin low, and I2C® is successive registers.
selected by setting the SPI/I2C pin high. The state
To read a register, the MAP has to be set to the cor-
of this pin is continuously monitored.
rect address by executing a partial write cycle
2.6.1 SPI Mode which finishes (CS high) immediately after the
MAP byte. The auto MAP increment bit (INCR)
In SPI mode, CS is the CS4227 chip select signal,
may be set or not, as desired. To begin a read, bring
CCLK is the control port bit clock, (input into the
CS low, send out the chip address and set the
CS4227 from the microcontroller), CDIN is the in-
read/write bit (R/W) high. The next falling edge of
put data line from the microcontroller, CDOUT is
CCLK will clock out the MSB of the addressed
the output data line to the microcontroller, and the
register (CDOUT will leave the high impedance
chip address is 0010000. Data is clocked in on the
state). If the MAP auto increment bit is set to 1, the
rising edge of CCLK and out on the falling edge.
data for successive registers will appear consecu-
tively.

DS281PP2 17
 CS4227

Note 1
ADDR DATA DATA
SDA 00100 R/W ACK ACK 1-8 ACK
AD1-0 1-8

SCL

Start Stop

Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Figure 12. Control Port Timing, I2C® Mode

2.6.2 I2C® Mode 2.7 Power-up/Reset/Power Down Mode

In I2C® mode, SDA is a bidirectional data line. Upon power up, the user should hold PDN = 0 for
Data is clocked into and out of the part by the clock, approximately 1ms. In this state, the control port is
SCL, with the clock to data relationship as shown reset to its default settings. At the end of the PDN,
in Figure 12. There is no CS pin. Pins AD0, AD1 the device remains in a low power mode in which
form the partial chip address. The upper 5 bits of CMOUT will not supply current, but the control
the 7 bit address field must be 00100. To commu- port is active. The desired settings should be loaded
nicate with a CS4227, the LSBs of the chip address while keeping the RS bit set to 1. Normal operation
field, which is the first byte sent to the CS4227, is achieved by setting the CE bit to zero in the
should match the settings of the AD1, AD0 pins. Clock Mode Byte (#1) and the RS bit to zero in the
The eighth bit of the address bit is the R/W bit (high Converter Control Byte (#2). Once done, the part
for a read, low for a write). If the operation is a powers up and an offset calibration occurs. This
write, the next byte is the Memory Address Pointer process lasts approximately 50 ms.
which selects the register to be read or written. If Reset/power down is achieved by lowering the
the operation is a read, the contents of the register PDN pin causing the part to enter power down.
pointed to by the Memory Address Pointer will be Once PDN goes high, the control port is functional
output. Setting the auto increment bit in MAP, al- and the desired settings should be loaded in while
lows successive reads or writes of consecutive reg- keeping the RS bit set to 1. The remainder of the
isters. Each byte is separated by an acknowledge chip remains in a low power reset state until the RS
bit. Use of the I2C bus® compatible interface re- bit in the Convertor Control Byte is set to 0. After
quires a license from Philips. I2C bus® is a regis- clearing the RS bit, the CE bit (Clock Enable) in the
tered trademark of Philips Semiconductors. Clock Mode Byte (#1) should also be set to zero.
2.6.3 Control Port Bit Definitions The CS4227 will also enter a stand by mode if the
master clock source stops for approximately 10 µs
All registers can be written and read back, except
or if the LRCK is not synchronous to the master
the DAC Status Report Byte (#10) and ADC Status
clock. The control port will retain its current set-
Report Byte (#13), which are read only. See the fol-
tings.
lowing bit definition tables for bit assignment in-
formation.

18 DS281PP2
 CS4227

2.8 DAC Calibration

Gain
Output offset voltage is minimized by an internal dB
calibration cycle. A calibration will automatically
occur anytime the part comes out of reset, includ- T1=50 µs
ing the power-up reset, or when the master clock 0dB
source to the part changes by changing the CE or CI
bits in the Clock Mode Byte.
T2 = 15 µs
The CS4227 can be re-calibrated whenever de- -10dB
sired. A control bit, CAL, in the Converter Control
Byte, is provided to initiate a calibration. The se-
quence is: F1 F2 Frequency
Figure 13. De-emphasis Curve.
1) Set CAL to 1, the CS4227 sets CALP to 1 and
begins to calibrate. ples) by setting the MOH bit = 0 in the Auxiliary
2) CALP will go to 0 when the calibration is com- Port Control Byte. DACs will not be automatically
pleted. muted when MOH = 1. When the HOLD pin is de-
Additional calibrations can be implemented by set- asserted (HOLD = 0), the DAC outputs will return
ting CAL to 0 and then to 1. to one of two different states controlled by the
UMV (Unmute on Valid Data) bit in the Auxiliary
2.9 De-Emphasis Port Control Byte. When UMV = 0, the DAC out-
The CS4227 is capable of digital de-emphasis for puts will unmute when the HOLD is removed.
32, 44.1, or 48 kHz sample rates. Implementation When UMV = 1, the DACs must be unmuted in the
of digital de-emphasis requires reconfiguration of DAC Control Byte after the HOLD is removed.
the digital filter to maintain the filter response This allows the user to unmute the DAC after the
shown in Figure 13 at multiple sample rates. The invalid data has passed through the DSP.
Auxiliary Port Control Byte selects the de-empha- 2.11 Power Supply, Layout, and
sis control method. De-emphasis may be enabled Grounding
under hardware control, using the DEM pin
(DEM2/1/0=4,5,6), or by software control using The CS4227, along with associated analog circuit-
the DEM bit (DEM2/1/0=0,1,2,3) ry, should be positioned near the split between
ground planes, and have its own, separate, ground
2.10 Hold Function plane (see Figure 14). Preferably, it should also
If the digital audio source presents invalid data to have its own power plane. The +5 V supply must be
the CS4227, the CS4227 may be configured to connected to the CS4227 via a ferrite bead, posi-
cause the last valid digital input level to be held tioned closer than 1" to the device. A single con-
constant (this sounds much better than a potentially nection between the CS4227 ground and the board
random output level). Holding the previous output ground should be positioned as shown in Figure 14.
sample occurs when the user asserts the HOLD pin The location of the 1 µF CMOUT filtering capica-
(HOLD = 1) at any time during the stereo sample tor should be as close to the CS4227 as possible.
period. During a HOLD condition, AUXPort input See Crystal's layout Applications Note, and the
data is ignored. DAC outputs can be automatically CDB4227 evaluation board data sheet for recom-
muted after an extended HOLD period (>15 sam- mended layout of the decoupling components.

DS281PP2 19
 CS4227

The CS4227 will mute the analog outputs and enter

the Power Down Mode if the supply drops below
approximately 4 volts.
2.12 ADC and DAC Filter Response Plots
Figures 15 through 20 show the overall frequency
response, passband ripple and transition band for
the CS4227 ADC’s and DAC’s.

> 1/8"

Digital Analog Note that the CS4227

+5V
Ground Ground is oriented with its
Ferrite
Plane Plane digital pins towards the
Bead
digital end of the board.
CS4227
Ground
Connection

CPU & Digital Codec Codec

Logic digital analog
signals signals &
components

Figure 14. Suggested Layout Guideline

20 DS281PP2
 CS4227

Figure 15. 20-bit ADC Filter Response Figure 16. 20-bit ADC Passband Ripple

Figure 17. 20-bit ADC Transition Band Figure 18. DAC Frequency Response

Figure 19. DAC Passband Ripple Figure 20. DAC Transition Band

DS281PP2 21
 CS4227

2.13 Memory Address Pointer (MAP)

7 6 5 4 3 2 1 0
INCR 0 0 MAP4 MAP3 MAP2 MAP1 MAP0

MAP4-MAP0 Register Pointer

INCR Auto Increment Control Bit

0 - No auto increment
1 - Auto increment on
This register defaults to 01h.

2.14 Reserved Byte (0)

This byte is reserved for internal use and must be set to 00h for normal operation.

This register defaults to 00h.

2.15 Clock Mode Byte (1)

7 6 5 4 3 2 1 0
0 CO1 CO0 CI1 CI0 0 0 CE

CE Master clock enable

0 - Clock Enabled
1 - Clock Disabled

CI1-CI0 Determines frequency of XTI

0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - not used

CO1-CO0 Sets CLKOUT frequency

0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs

This register defaults to 01h.

22 DS281PP2
 CS4227

2.16 Converter Control Byte (2)

7 6 5 4 3 2 1 0
CALP CLKE DU 0 0 0 CAL RS

RS Chip reset
0 - No Reset
1 - Reset

CAL Calibration control bit

0 - Normal operation
1 - Rising edge initiates calibration
The following bits are read only:

DU Shows selected De-Emphasis setting used by DAC’s

0 - Normal Flat DAC frequency response
1 - De-Emphasis selected

CLKE Clocking system status

0 - No errors
1 - Crystal is not oscillating, or requesting clock change in progress

CALP Calibration status

0 - Calibration done
1 - Calibration in progres

This register defaults to 01h.

2.17 DAC Control Byte (3)

7 6 5 4 3 2 1 0
ZCD MUTC MUT6 MUT5 MUT4 MUT3 MUT2 MUT1

MUT6-MUT1 Mute control bits

0 - Normal output level
1 - Selected DAC output muted

MUTC Controls mute on consecutive zeros function

0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros

ZCD Zero crossing disable

0 - DAC mutes and volume control changes occur on zero-crossings
1 - DAC mutes and volume control changes occur immediately.

This register defaults to 3Fh.

DS281PP2 23
 CS4227

2.18 Output Attenuator Data Byte (4, 5, 6, 7, 8, 9)

7 6 5 4 3 2 1 0
0 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0

ATT6-ATT0 Sets attenuator level

0 - No attenuation
127 - 127 dB attenuation
ATT0 represents 1.0 dB of attenuation

This register defaults to 7Fh.

2.19 DAC Status Report Byte (Read Only) (10)

7 6 5 4 3 2 1 0
0 - ACC6 ACC5 ACC4 ACC3 ACC2 ACC1

ACC6-ACC1 Acceptance Bit

0 - ATT6-ATT0 has been accepted.
1 - New setting is waiting for zero-crossing to be accepted.

This register is read-only.

2.20 ADC Control Byte (11)

7 6 5 4 3 2 1 0
IS1 IS0 0 AIS1 AIS0 MUTM MUTR MUTL

MUTL, MUTR, MUTM - Left, right and mono channel mute control
0 - Normal output level
1 - Selected ADC output muted

AIS1-AIS0 ADC analog input mux control

0 - Selects stereo pair 1
1 - Selects stereo pair 2
2 - Selects stereo pair 3
3 - Differential Input

IS1-IS0 Input mux selection

0 - Stereo ADC output to SDOUT1, Mono ADC output to SDOUT2
1 - Auxiliary Digital Input Port to SDOUT1, Mono ADC output to SDOUT2
2 - Auxiliary Digital Input Port to SDOUT1, Stereo ADC output to SDOUT2
3 - Not used.

This register defaults to 00h.

24 DS281PP2
 CS4227

2.21 Input Control Byte (12)

7 6 5 4 3 2 1 0
OVRM 0 0 0 GNR1 GNR0 GNL1 GNL0

GNL1-GNL0 Sets left input gain

0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB

GNR1-GNR0 Sets right input gain

0 - 0 dB
1 - 3 dB
2 - 6 dB
3 - 9 dB

OVRM ADC Overflow Mask

This register defaults to 00h.

2.22 ADC Status Report Byte (Read Only) (13)

7 6 5 4 3 2 1 0
LVM1 LVM0 LVR2 LVR1 LVR0 LVL2 LVL1 LVL0

LVL2-LVL0, LVR2-0 Left and Right ADC output level

0 - Normal output levels
1 - -6 dB level
2 - -5 dB level
3 - -4 dB level
4 - -3 dB level
5 - -2 dB level
6 - -1 dB level
7 - Clipping

LVLM1-LVLM0 Mono ADC output level

0 - Normal output level
1 - -6 dB level
2 - -3 dB level
3 - Clipping

These bits are ’sticky’. They constantly monitor the ADC output for the peak levels and hold the max-
imum output. They are reset to 0 when read.

This register is read only.

DS281PP2 25
 CS4227

2.23 DSP Port Mode Byte (14)

7 6 5 4 3 2 1 0
DCK1 DCK0 DMS1 DMS0 DSCK DDF2 DDF1 DDF0

DDF2-DDF0 Data format

0 - Right justified, 20-bit
1 - Right justified, 18-bit
2 - Right justified, 16-bit
3 - Left justified, 20-bit in / 24-bit out
4 - I2S compatible, 20-bit in / 24-bit out
5 - One Data Line Mode (Figure 10)
6 - One Data Line (Master Mode only, Figure 10)
7 - Not used

DSCK Set the polarity of clocking data

0 - Data clocked in on rising edge, out on falling edge
1 - Data clocked in on falling edge, out on rising edge

DMS1-DMS0 Sets the mode of the port

0 - Slave
1 - Master Burst - SCLKs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKs are evenly distributed (No 48 Fs SCLK)
3 - not used - default to Slave

DCK1-DCK0* Set number of bit clocks per Fs period

0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All formats will default to 16 bits
3 - 64

This register defaults to 00h.

* Ignored in data formats 5 and 6.

26 DS281PP2
 CS4227

2.24 Auxiliary Port Mode Byte (15)

7 6 5 4 3 2 1 0
ACK1 ACK0 AMS1 AMS0 ASCK ADF2 ADF1 ADF0

ADF2-ADF0 Data format

0 - Right justified, 20-bit data
1 - Right justified, 18-bit data
2 - Right justified, 16-bit data
3 - Left justified, 20-bit
4 - I2S compatible, 20-bit
5 - Not used
6 - Not used
7 - Not used

ASCK Sets the polarity of clocking data

0 - Data clocked in on rising edge
1 - Data clocked in on falling edge

AMS1-AMS0 Sets the mode of the port.

0 - Slave
1 - Master Burst - SCLKAUXs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame
3 - Not used - default to slave

ACK1-ACK0 Set number of bit clocks per Fs period.

0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All input formats will default to 16 bits.
3 - 64

This register defaults to 00h.

DS281PP2 27
 CS4227

2.25 Auxilliary Port Control Byte (16)

7 6 5 4 3 2 1 0
0 0 UMV MOH 0 DEM2 DEM1 DEM0

DEM 2-0 Selects de-emphasis response/source

0 - De-emphasis off
1 - De-emphasis on 32 kHz
2 - De-emphasis on 44.1 kHz
3 - De-emphasis on 48 kHz
4 - De-emphasis pin 32 kHz
5 - De-emphasis pin 44.1 kHz
6 - De-emphasis pin 48 kHz
7 - Reserved

MOH Mute On Hold

0 - Extended Hold (16 frames) mutes DAC outputs
1 - DACs not muted

UMV Unmute on Valid Data

0 - DACs unmute when HOLD is removed
1 - DACs must be unmuted in DAC control byte after HOLD is removed.

This register defaults to 00h.

28 DS281PP2
 CS4227

3. PIN DESCRIPTIONS
DGND2
VD+ SCLK
DGND1 LRCK
NC SDOUT1
SCLKAUX SDOUT2
LRCKAUX SDIN1
DATAUX SDIN2
HOLD 44 43 42 41 40 39 38 37 36 35 34 SDIN3
1 33
SCL/CCLK 2 32 CLKOUT
SDA/CDOUT 3 31 OVL
4 30
AD1/CDIN XTO
5 29
CS4227-KQ
AD0/CS 6
44-pin TQFP
28 XTI
7 27
SPI/I2C DEM
8 Top View 26
PDN 9 25 AOUT6
AIN3R 10 24 AOUT5
11 23
AIN3L 12 13 14 15 16 17 18 19 20 21 22 AOUT4
AIN2L AOUT3
AIN2R AOUT2
AIN1R AOUT1
AIN1L AGND2
AINAUX VA+
CMOUT AGND1
NC

Power Supply

VA+ - Analog Power Input

+5 V analog supply.

AGND1, AGND2 - Analog Ground

Analog grounds.

VD+ - Digital Power Input

+ 5 V digital supply.

DGND1, DGND2 - Digital Ground

Digital grounds.

DS281PP2 29
 CS4227

Analog Inputs

AIN1L, AIN1R - Left and Right Channel Mux Input 1

Analog signal input connections for the right and left channels for multiplexer input 1.

AIN2L, AIN2R - Left & Right Channel Mux Input 2

Analog signal input connections for the right and left channels for multiplexer input 2.

AIN3L, AIN3R - Left & Right Channel Mux Input 3

Analog signal input connections for the right and left channels for multiplexer input 3.

AINAUX - Auxiliary Line Level Input

Analog signal input for the mono A/D converter.

Analog Outputs

AOUT1, AOUT2, AOUT3, AOUT4, AOUT5, AOUT6 - Audio Outputs

The analog outputs from the 6 D/A converters. Each output can be independently controlled for output
amplitude.

CMOUT - Common Mode Output

This common mode voltage output may be used for level shifting when DC coupling is desired. The load
on CMOUT must be DC only, with an impedance of not less than 50 kΩ. CMOUT should be bypassed
with a 1.0 µF to AGND.

Digital Audio Interface Signals

SDIN1 - Serial Data Input 1

Digital audio data for the DACs 1 and 2 is presented to the CS4227 on this pin. This pin is also used for
one-line data input modes.

SDIN2 - Serial Data Input 2

Digital audio data for the DACs 3 and 4 is presented to the CS4227 on this pin.

SDIN3 - Serial Data Input 3

Digital audio data for the DACs 5 and 6 is presented to the CS4227 on this pin.

SDOUT1- Serial Data Output 1

Digital audio data from the 20-bit stereo audio ADCs is output from this pin. When IS = 1 or 2,
DATAAUX is output on SDOUT1. This pin is also used for one line data output modes.

SDOUT2 - Serial Data Output 2

Digital audio data from the mono audio ADC is output from this pin. When IS = 2, the stereo audio
ADC's are output from this pin

SCLK - DSP Serial Port Clock I/O

SCLK clocks digital audio data into the DACs via SDIN1/2/3, and clocks data out of the ADCs on
SDOUT1/2. Active clock edge depends on the DSCK bit.

30 DS281PP2
 CS4227

LRCK - Left/Right Select Signal I/O

The Left/Right select signal. This signal has a frequency equal to the sample rate. The relationship of
LRCK to the left and right channel data depends on the selected format.

DEM - De-emphasis Control

When low, DEM controls the activation of the standard 50/15 us de-emphasis filter for either 32, 44.1 or
48 kHz sample rates. This pin is enabled by the DEM2-0 bits in the Auxiliary Port Control Byte.

OVL - Overload Indicator

This pin goes high if either of the stereo audio ADCs or the mono ADC is clipping.

Auxillary Digital Audio Signals

DATAUX - Auxiliary Data Input

DATAUX is the auxiliary audio data input line, usually connected to an external digital audio source.

LRCKAUX - Auxiliary Word Clock Input or Output

In auxiliary slave mode, LRCKAUX is a word clock (at Fs) from an external digital audio source. In
auxiliary master mode, LRCKAUX is a word clock output (at Fs) to clock an external digital audio
source.

SCLKAUX - Auxiliary Bit Clock Input or Output

In auxiliary slave mode, SCLKAUX is the serial data bit clock from an external digital audio source, used
to clock in data on DATAAUX. In auxiliary master mode, SCLKAUX is a serial data bit clock output.

HOLD - HOLD Control

This pin is sampled on the active edge of SCLKAUX. If it is high any time during the frame, DATAUX
data is ignored and the previous "good" sample is output to the serial output port.

Control Port Signals

SPI/I2C - Control Port Format

Setting this pin low configures the control port for the SPI interface; a high state configures the control
port for the I2C interface. The state of this pin sets the function of the control port input/output pins .

SCL/CCLK - Serial Control Interface Clock

SCL/CCLK is the serial control interface clock, and is used to clock control bits into and out of the
CS4227.

AD0/CS - Address Bit / Control Port Chip Select

In I2C® mode, AD0 is a chip address bit. In SPI software control mode, CS is used to enable the control
port interface on the CS4227.

AD1/CDIN - Address Bit / Serial Control Data In

In I2C® mode, AD1 is a chip address bit. In SPI software control mode, CDIN is the input data line for
the control port interface.

SDA/CDOUT - Serial Control Data Out

In I2C® mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the output data
from the control port interface on the CS4227.

DS281PP2 31
 CS4227

Clock and Crystal Pins

XTI, XTO - Crystal connections

Input and output connections for the crystal which may be used to operate the CS4227. Alternatively, a
clock may be input into XTI.

CLKOUT - Master Clock Output

CLKOUT allows external circuits to be synchronized to the CS4227. Alternate output frequencies are
selectable by the control port.

Miscellaneous Pins

PDN - Powerdown Pin

When low, the CS4227 enters a low power mode and all internal states are reset, including the control
port. When high, the control port becomes operational and the RS bit must be cleared before normal
operation will occur.

NC - No Connect

32 DS281PP2
 CS4227

4. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the
measurement to full scale. This technique ensures that the distortion components are below the noise
level and do not effect the measurement. This measurement technique has been accepted by the Audio
Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels.
ADCs are measured at -1 dBFs as suggested in AES 17-1991 Annex A.

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the rms analog output level with 1kHz full scale digital input to the rms analog output level
with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in
decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and
referred to as Idle Channel Noise. This specification has also been standardized by the Electronic
Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio.

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test
signal. Units in decibels.

Interchannel Isolation
A measure of crosstalk between channels. Measured for each channel at the converter’s output with no
signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.

Frequency Response
A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each channel. For
the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in
decibels.

Gain Error
The deviation from the nominal full scale output for a full scale input.

Gain Drift
The change in gain value with temperature. Units in ppm/°C.

Offset Error
For the ADCs, the deviation in LSB's of the output from mid-scale with the selected input grounded. For
the DAC's, the deviation of the output from zero (relative to CMOUT) with mid-scale input code. Units
are in volts.

DS281PP2 33
 CS4227

5. PACKAGE DIMENSIONS
44L TQFP PACKAGE DRAWING

E1

D D1

e B

∝ A

A1
L

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.000 0.065 0.00 1.60
A1 0.002 0.006 0.05 0.15
B 0.012 0.018 0.30 0.45
D 0.478 0.502 11.70 12.30
D1 0.404 0.412 9.90 10.10
E 0.478 0.502 11.70 12.30
E1 0.404 0.412 9.90 10.10
e 0.029 0.037 0.70 0.90
L 0.018 0.030 0.45 0.75
∝ 0.000 7.000 0.00 7.00

TYP MAX TYP MAX

Coplanarity .001 .004 .025 .10

JEDEC # : MS-026

34 DS281PP2
• Notes •