MPM3650

2.75V to 17V, 6A, 1.2MHz, Synchronous,

Ultra-Thin Power Module
DESCRIPTION FEATURES
The MPM3650 is a fully integrated high-  Wide 2.75V to 17V Operating Input Range
frequency, synchronous, rectified, step-down  Output Current:
power module with an internal inductor. It offers o 0.6V to 1.8V, 6A Output
a very compact solution to achieve 6A of o Above 1.8V, 5A Output
continuous output current over a wide input  Internal Power MOSFETs
range, with excellent load and line regulation.  Output Adjustable from 0.6V
The MPM3650 offer synchronous mode  High-Efficiency Synchronous Mode
operation for higher efficiency over the output Operation
current load range.  High Efficiency with DCM at Light-Load
Constant-on-time (COT) control operation  Supports Pre-Biased Start-Up
provides very fast transient response and easy  Fixed 1200kHz Switching Frequency
loop design, as well as very tight output  External Programmable Soft-Start Time
regulation.  EN and Power Good for Power Sequencing
Full protection features include short-circuit  Over-Current Protection and Hiccup Mode
protection (SCP), over-current protection (OCP),  Thermal Shutdown
under-voltage protection (UVP), and thermal  Available in a QFN-24 (4mmx6mmx1.6mm)
shutdown. Package
The MPM3650 requires a minimal number of APPLICATIONS
readily available, standard external components.  FPGA Power Systems
It is available in a space-saving QFN-24
 Optical Modules
(4mmx6mm) package.
 Telecom
 Networking
 Industrial Equipment
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS”, the MPS logo, and “Simple, Easy Solutions” are
trademarks of Monolithic Power Systems, Inc. or its subsidiaries.

TYPICAL APPLICATION
Efficiency vs. Load Current
BST SW VIN = 12V
2.75V to 17V VOUT
VIN 1V/6A 95 2.2
C1 VOUT
90
MPM3650 R1 C2 1.7
20kΩ
EFFICIENCY (%)

85
PG FB
R2
80 1.2
EN 30kΩ
SS
75 0.7
VCC Vou t=1V
70 Vou t=1.8 V
PGND

AGND

Vou t=3.3 V
Vou t=1V Ploss
0.2
65 Vou t=1.8 V P loss
Vou t=3.3 V P loss
60 -0.3
0 1 2 3 4 5 6
LOAD CURRENT (A)

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ORDERING INFORMATION
Part Number* Package Top Marking MSL Rating
QFN-24
MPM3650GQW See Below 3
(4mmx6mmx1.6mm)
* For Tape & Reel, add suffix –Z (e.g. MPM3650GQW–Z).

TOP MARKING

MPS: MPS prefix

Y: Year code
WW: Week code
MP3650: First six digits of the part number
LLLLLL: Lot number
M: Module

PACKAGE REFERENCE
TOP VIEW
PGND SW VIN PG
24 23 22 21

1 20 PG

PGND 2 19

PGND 3 18

PGND 4 17

5 16 EN

6 15 BST

7 14 SW

SW 8 13

OUT 9 12 OUT

10 11

OUT OUT

QFN-24 (4mmx6mmx1.6mm)
PACKAGE TOP VIEW

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PIN FUNCTIONS
Pin # Name Description
System ground. This pin is the reference ground of the regulated output voltage. Because
1, 2, 3, 4,
PGND of this, extra care must be taken when designing the PCB layout. It is recommended to
5, 24
connect this pin to GND with copper pours and vias.
6 VCC Internal bias supply output.
7, 8, 13,
SW Switch output. Float the SW pins.
14, 23
9, 10, 11,
OUT Output pin. Connect OUT to the output capacitor (COUT).
12
15 BST Bootstrap. Float the BST pin.
Enable. Pull the EN pin high to enable the part. When EN is floating, the device is disabled.
16 EN
EN is pulled down to GND by an internal 3.3MΩ resistor.
Feedback. Sets the output voltage when connected to the tap of an external resistor
17 FB
divider that is placed between output and GND.
Signal ground. AGND is not internally connected to the system ground, so ensure that
18 AGND
AGND is connected to the system ground in the PCB layout.
Soft start. Connect a capacitor across SS and GND to set the soft-start time and avoid
19 SS
start-up inrush current. This pin includes an internal 22nF SS capacitor.
Power good output. The output of the PG pin is an open-drain output. The PG pin
20, 21 PG changes its state if under-voltage protection (UVP), over-current protection (OCP), over-
temperature protection (OTP), or an over-voltage (OV) condition occurs.
Supply voltage. The part operates from a 2.75V to 17V input rail. Use a 0402 size, 0.1μF
22 VIN
input capacitor to decouple the input rail. Use wide PCB traces to make the connection.

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC

EVM3650-QW-00A (5)…...32.75….10.217..°C/W
VIN .................................................-0.3V to +20V
VSW………………………… - 0.3V (-5V < 10ns) to
VIN + 0.7V (23V < 10ns) Notes:
1) Exceeding these ratings may damage the device.
VBST ...................................................... VSW + 4V 2) The maximum allowable power dissipation is a function of the
VEN ................................................................. VIN maximum junction temperature, TJ (MAX), the junction-to-
All other pins ...................................-0.3V to +4V ambient thermal resistance, θJA, and the ambient temperature,
TA. The maximum allowable continuous power dissipation on
Continuous power dissipation (TA = 25°C) (2) the EVM3650-QW-00A evaluation board at any ambient
............................................................... 3.816W temperature is calculated by PD (MAX) = (TJ (MAX) - TA) / θJA.
Junction temperature ................................150°C Exceeding the maximum allowable power dissipation will
cause excessive die temperature, and the regulator will go into
Lead temperature .....................................260°C thermal shutdown. Internal thermal shutdown circuitry protects
Storage temperature ................ -65°C to +125°C the device from permanent damage.
3) The device is not guaranteed to function outside of its operating
ESD Ratings conditions.
4) Operation voltage after VOUT is regulated to a 0.6V or higher
Human body model (HBM) .......................... 2kV voltage.
Charged device model (CDM)......................2kV 5) Measured on EVM3650-QW-00A, 4-layer PCB.

Recommended Operating Conditions (3)

Supply voltage (VIN) ....................... 2.75V to 17V
Output voltage (VOUT)………...0.6V to VIN х DMAX
or 12V maximum (4)
Operating junction temp (TJ) .... -40°C to +125°C

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ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = -40°C to +125°C (6), typical values are tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Input voltage range VIN 2.75 17 V
Supply Current
Shutdown supply
IIN VEN = 0V 2 5 µA
current
Quiescent supply
IQ VEN = 2V, VFB = 0.65V 100 150 µA
current
MOSFET
Switch leakage SWLKG VEN = 0V, VSW = 7V 5 µA
Current Limit
Valley current limit ILIMIT_VY 6 7 A
Short hiccup duty cycle
(7) DHICCUP 10 %

Switching Frequency and Minimum On/Off Timer

Switching frequency fSW 0.9 1.2 1.6 MHz
(7)
Minimum on time tON_MIN 50 ns
(7)
Minimum off time tOFF_MIN 100 ns
Reference and Soft Start
TJ = 25°C 594 600 606 mV
Feedback voltage VFB
TJ = -40°C to +125°C 591 600 609 mV
Feedback current IFB VFB = 700mV 10 50 nA
Soft-start current ISS_START 4 6 8 µA
Enable and UVLO
EN rising threshold VEN_RISING 1.19 1.23 1.27 V
EN falling threshold VEN_FALLING 0.96 1 1.04 V
EN pin pull-down
REN_PD 1.2 MΩ
resistor
VCC
VCC under-voltage
VCCVTH 2.4 2.5 2.6 V
lockout rising threshold
VCC under-voltage
VCCHYS 200 mV
lockout threshold
VCC regulator VCC VIN = 5V 3.5 V
VCC load regulation REGVCC ICC = 5mA 3 %

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 5V, TJ = -40°C to +125°C, typical value is tested at TJ = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Power Good
Power good UV rising
PGUVVTH_HI 0.85 0.9 0.95 VFB
threshold
Power good UV falling
PGUVVTH_LO 0.75 0.80 0.85 VFB
threshold
Power good OV rising
PGOVVTH_HI 1.15 1.2 1.25 VFB
threshold
Power good OV falling
PGOVVTH_LO 1.05 1.1 1.15 VFB
threshold
Power good delay PGTD Both edges 50 µs
Power good sink
VPG Sink 4mA 0.4 V
current capability
Power good leakage
IPG_LEAK VPG = 5V 10 μA
current
Thermal Protection
Thermal shutdown (7) TSD 150 °C
Thermal hysteresis (7) TSD-HYS 20 °C
Notes:
6) Not tested in production. Guaranteed by over-temperature correlation.
7) Guaranteed by design and characterization tests.

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TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current Efficiency vs. Load Current
VOUT = 1V VOUT = 1.8V
100 100

90

EFFICIENCY (%)
EFFICIENCY (%)

90

80

80
70 VIN=5V VIN=5V
VIN=12V VIN=12V
VIN=17V VIN=17V
60 70
0 1 2 3 4 5 6 0 1 2 3 4 5 6
LOAD CURRENT (A) LOAD CURRENT (A)

Efficiency vs. Load Current Line Regulation

VOUT = 3.3V VOUT = 1V
100 0.5
0.4
LINE REGULATION (%)

0.3
EFFICIENCY (%)

90 0.2
0.1
0
-0.1
80
-0.2
VIN=5V -0.3
VIN=12V Iout=0.01A
-0.4 Iout=3A
VIN=17V
70 -0.5
0 1 2 3 4 5 3 5 7 9 11 13 15 17
LOAD CURRENT (A) INPUT VOLTAGE (V)
Line Regulation Line Regulation
VOUT = 1.8V VOUT = 3.3V
0.5 1
0.4 0.8
LINE REGULATION (%)

0.3 0.6
LINE REGULATION (%)

0.2 0.4
0.1 0.2
0 0
-0.1 -0.2
-0.2 -0.4
-0.3 -0.6
Iout=0.01A Iout=0.01A
-0.4 -0.8 Iout=2.5A
Iout=3A
-0.5 -1
3 5 7 9 11 13 15 17 3 5 7 9 11 13 15 17
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Load Regulation Load Regulation
VOUT = 1V VOUT = 1.8V
0.5 0.5
0.4 0.4
LOAD REGULATION (%)

LOAD REGULATION (%)

0.3 0.3
0.2 0.2
0.1 0.1
0 0
-0.1 -0.1
-0.2 -0.2
-0.3 VIN=5V -0.3 VIN=5V
VIN=12V VIN=12V
-0.4 -0.4
VIN=17V VIN=17V
-0.5 -0.5
0 1 2 3 4 5 6 0 1 2 3 4 5 6
LOAD CURRENT (A) LOAD CURRENT (A)

Load Regulation Temperature vs. IOUT

VOUT = 3.3V VOUT = 1.8V
0.5 90
0.4
80
LOAD REGULATION (%)

CASE TEMPERATURE (°C)

0.3
0.2 70
0.1
60
0
-0.1 50
-0.2 40
-0.3 VIN=5V Vin=5V
VIN=12V 30 Vin=12V
-0.4 VIN=17V Vin=17V
-0.5 20
0 1 2 3 4 5 1 2 3 4 5 6
LOAD CURRENT (A) LOAD CURRENT (A)

Temperature vs. IOUT Temperature vs. IOUT

VOUT = 1V, TA = 15°C VOUT = 3.3V
90 80

80
CASE TEMPERATURE (°C)
CASE TEMPERATURE (°C)

70
70
60
60
50
50
40
40
Vin=5V Vin=5V
30 Vin=12V 30 Vin=12V
Vin=17V Vin=17V
20 20
1 2 3 4 5 6 1 2 3 4 5 6
LOAD CURRENT (A) LOAD CURRENT (A)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.
Thermal Derating Thermal Derating
VIN = 12V without airflow VIN = 12V with airflow
7 7

6 6

LOAD CURRENT (A)

LOAD CURRENT (A)

5 5

4 4

3 3

2 Vin=12V,Vout=1V 2 Vin=12V,Vout=1V
1 Vin=12V,Vout=1.8V Vin=12V,Vout=1.8V
1
Vin=12V,Vout=3.3V Vin=12V,Vout=3.3V
0 0
0 10 20 30 40 50 60 70 80 90 100110120 0 10 20 30 40 50 60 70 80 90 100110120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

Thermal Derating Thermal Derating

VIN = 5V without airflow VIN = 5V with airflow
7 7

6 6
LOAD CURRENT (A)

LOAD CURRENT (A)

5 5

4 4

3 3

2 Vin=5V,Vout=1V 2 Vin=5V,Vout=1V
Vin=5V,Vout=1.8V 1 Vin=5V,Vout=1.8V
1
Vin=5V,Vout=3.3V Vin=5V,Vout=3.3V
0 0
0 10 20 30 40 50 60 70 80 90 100110120 0 10 20 30 40 50 60 70 80 90 100110120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.

VOUT Ripple VOUT Ripple

IOUT = 0A IOUT = 6A

CH1:
CH1: VOUT / AC
VOUT / AC 5mV/div.
20mV/div.

20ms/div. 400ns/div.

Load Transient Load Transient

IOUT = 0A to 3A IOUT = 3A to 6A

CH1: CH1:
VOUT / AC VOUT / AC
50mV/div. 20mV/div.

CH4: IOUT CH4: IOUT

2A/div. 5A/div.

100μs/div. 100μs/div.

VIN On VIN On
IOUT = 0A IOUT = 6A

CH1: VOUT CH1: VOUT

1V/div. 1V/div.
CH2: VSW CH2: VSW
5V/div. 5V/div.

CH3: VIN CH3: VIN

5V/div. 5V/div.
CH4: IOUT CH4: IOUT
5A/div. 5A/div.

10ms/div. 10ms/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.

VIN Off VIN Off

IOUT = 0A IOUT = 6A

CH1: VOUT
1V/div. CH1: VOUT
CH2: VSW 1V/div.
5V/div. CH2: VSW
5V/div.

CH3: VIN CH3: VIN

5V/div. 5V/div.
CH4: IOUT CH4: IOUT
5A/div. 5A/div.

10ms/div. 10ms/div.

EN On EN On
IOUT = 0A IOUT = 6A

CH1: VOUT CH1: VOUT

1V/div. 1V/div.
CH2: VSW CH2: VSW
10V/div. 5V/div.

CH3: VEN
2V/div. CH3: VEN
CH4: IOUT 2V/div.
5A/div. CH4: IOUT
5A/div.

10ms/div. 10ms/div.

EN Off EN Off
IOUT = 0A IOUT = 6A

CH1: VOUT CH1: VOUT

1V/div. 1V/div.
CH2: VSW CH2: VSW
10V/div. 5V/div.

CH3: VEN
2V/div. CH3: VEN
CH4: IOUT 2V/div.
5A/div. CH4: IOUT
5A/div.
10ms/div. 10ms/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 5V, VOUT = 1V, COUT = 4 x 22μF, fSW = 1200kHz, TA = 25°C, unless otherwise noted.

SCP Steady State SCP Entry and Recovery

CH1: VOUT
CH1: VOUT 1V/div.
1V/div.
CH2: VSW
5V/div.

CH3: VIN
5V/div.
CH4: IOUT CH4: IOUT
10A/div. 2A/div.

20ms/div. 200ms/div.

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

FUNCTIONAL BLOCK DIAGRAM

VIN

Bias and Bootstrap

EN BST
Voltage Regulator
Reference
3.3MΩ

LDO

VCC
Main
HS Switch
Driver (NCH)
ISS EAO
SS EA SW
22nF On Logic
AGND Timer Control 0.5μH
VCC
VOUT
COMP
FB LS
BUF Ramp Driver

PWM
Current Synchronous
90% of VREF Rising Modulator Rectifier (NCH)
80% of VREF Falling Current-Sense
Amplifier

PG

110% of VREF Rising

GND
120% of VREF Falling

Figure 1: Functional Block Diagram

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OPERATION (CCM). Figure 3 shows CCM operation. When

VFB is below VEAO, the HS-FET turns on for a
The MPM3650 is a fully integrated, synchronous,
fixed interval, which is determined by a one-shot
rectified, step-down, switch-mode converter.
on-timer. When the HS-SFET turns off, the LS-
Constant-on-time (COT) control is employed to
FET turns on until the next period.
provide fast transient response and easy loop
stabilization. tON is constant

Figure 2 shows the simplified ramp

compensation block in the MPM3650.
Whenever VRAMP drops
below VEAO, the HS-FET
turns on

REF
FB L VOUT
On Logic
BUF Timer Control
SW
RAMP RESR R1

COUT
R2
Ramp
Generator
PWM
Figure 3: Heavy Load Operation
In CCM operation, the switching frequency is
Figure 2: Simplified Ramp Compensation Block fairly constant. This is called pulse-width
modulation (PWM) mode.
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns on when the feedback VCC Regulator
voltage (VFB) drops below the reference voltage The 3.5V internal regulator powers most of the
(VREF), and indicates there is an insufficient internal circuitries. This regulator takes the VIN
output voltage. The on period is determined by input and operates in the full VIN range. If VIN
both the output voltage and input voltage to exceeds 3.5V, the output of the regulator is in full
make the switching frequency fairly constant regulation. If VIN falls below 3.5V, the output of
across the input voltage range. the regulator decreases following the changes in
VIN. There is an internal 1μF decoupling ceramic
After the on period elapses, the HS-FET turns on
capacitor within the module.
again when VFB drops below VREF. By repeating
this operation, the converter regulates the output Enable
voltage. The integrated low-side MOSFET (LS- EN is a digital control pin that turns the regulator
FET) turns on when the HS-FET is off to on and off. Drive EN above 1.23V to turn the
minimize conduction loss. There is a dead short regulator on; drive EN below 1V to turn it off.
between the input and GND if both the HS-FET
and LS-FET turn on at the same time. This is When floating EN, pull it down to GND using an
called shoot-through. To avoid shoot-through, a internal 3.3MΩ resistor. EN can be connected
dead-time (DT) is internally generated between directly to VIN, and supports a 17V input range.
the HS-FET off period and LS-FET on period, Under-Voltage Lockout (UVLO)
and vice versa. Under-voltage lockout (UVLO) protects the chip
Internal compensation is applied for COT control from operating at an insufficient supply voltage.
to stabilize operation. Internal compensation The MPM3650 UVLO comparator monitors the
improves the jitter performance without affecting output voltage of the internal regulator (VCC).
the line or load regulation, even if ceramic The VCC UVLO rising threshold is about 2.5V.
capacitors are used. and its falling threshold is 2.3V.
CCM Operation If the input voltage exceeds the UVLO rising
When the output current is high and the inductor threshold voltage, the MPM3650 powers up. The
current is always above 0A, the device operates
in continuous conduction mode

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

device shuts off when the input voltage drops Figure 4 shows the relationship between the PG
below the UVLO falling threshold. This is a non- voltage and the pull-up current.
latch protection.
1.2
Soft Start

PG CLAMPED VOLTAGE (V)

1
The MPM3650 employs a soft start (SS)
mechanism to ensure the output smoothly ramps
0.8
up during power-up. When the EN pin goes high,
an internal current source (6μA) charges up the 0.6
SS capacitor. The SS capacitor voltage takes
over VREF to the PWM comparator when the 0.4
device is powering on. The output voltage
smoothly ramps up with the SS voltage. Once 0.2
the SS voltage exceeds VREF, it continues to
0
ramp up until VREF takes over. Then soft start
0 1 2 3 4 5
finishes, and the device enters steady state
PULL-UP CURRENT (mA)
operation.
Figure 4: PG Clamped Voltage vs. Pull-Up Current
The SS capacitor value can be calculated with
Equation (1): Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
t SS (ms)  ISS (A)
CSS (nF)  0.83  (1) The MPM3650 has valley limit control. The LS-
VREF (V) FET monitors the current flowing through the LS-
FET. The HS-FET does not turn on again until
An internal 22nF SS capacitor is recommended.
the valley current limit disappears. Meanwhile,
If the output capacitor has a large capacitance, the output voltage drops until VFB falls below the
do not set the SS time too short. Otherwise, the under-voltage (UV) threshold (typically 50%
device easily reaches the current limit during soft below VREF). Once a UV condition is triggered,
start. the MPM3650 enters hiccup mode to periodically
restart the part.
Power Good Indicator
The PG pin is the open drain of a MOSFET that During over-current protection (OCP), the device
connects to VCC or a voltage source through a tries to recover from the OC fault with hiccup
resistor (e.g. 100kΩ). The MOSFET turns on mode. This means that the chip disables the
when an input voltage is applied, and the PG pin output power stage, discharges the soft-start
is pulled to GND before soft start completes. capacitor, then automatically tries to reinitiate
After the feedback voltage (VFB) reaches 90% of soft start. If the OC condition remains after soft
VREF, the PG pin is pulled high after a 50μs delay. start ends, the device repeats this operation until
When VFB drops below 80% of VREF, the PG pin the OC condition disappears, and the output
is pulled low. rises back to its regulation level. OCP is a non-
latch protection.
If under-voltage lockout (UVLO) or over-
temperature protection (OTP) occurs, the PG pin Pre-Biased Start-Up
is immediately pulled low. If an over-current (OC) The MPM3650 has been designed for monotonic
condition occurs, the PG pin is pulled low when startup into pre-biased loads. If the output is pre-
VFB drops below 80% of VREF after a 0.05ms biased to a certain voltage during start-up, the
delay. If an over-voltage (OV) condition occurs, BST voltage is refreshed and charged, and the
the PG pin pulls low when VFB rises above 120% voltage on the soft-start capacitor also charges.
of VREF after a 0.05ms delay. If VFB falls below If the BST voltage exceeds its rising threshold
110% of VREF, the PG pin is pulled high after a voltage and the soft-start capacitor voltage
0.05ms delay. exceeds the sensed output voltage at the FB pin,
the part begins operating normally.
If the input supply fails to power the MPM3650,
PG is clamped low, even if PG is tied to an
external DC source through a pull-up resistor.
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 MPM3650 – 6A, STEP-DOWN POWER MODULE

Thermal Shutdown Start-Up and Shutdown Circuit

Thermal shutdown prevents the chip from If both VIN and EN exceed their respective
operating at exceedingly high temperatures. thresholds, the chip starts. The reference block
When the silicon die temperature exceeds starts first, generating a stable reference voltage
150°C, it shuts down the whole chip. When the and current, and then the internal regulator is
temperature falls below its lower threshold enabled. The regulator provides a stable supply
(typically 130°C), the chip is enabled again. for the remaining circuits.
Three events can shut down the chip: EN going
low, VIN going low, and thermal shutdown. The
shutdown procedure starts by initially blocking
the signaling path to avoid any fault triggering.
The internal supply rail is then pulled down.

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

APPLICATION INFORMATION
COMPONENT SELECTION because they are fairly stable amid temperature
Setting the Output Voltage fluctuations.
The external resistor divider sets the output The capacitors must have a ripple current rating
voltage. First, choose a value for R2. Choose a that exceeds the maximum input ripple current of
reasonable R2, since a small R2 leads to the converter. The input ripple current can be
considerable quiescent current loss, and a large estimated with Equation (3):
R2 makes the FB noise sensitive. It is
VOUT V
recommended to choose a value between 2kΩ ICIN  IOUT   (1  OUT ) (3)
and 100kΩ for R2. Set the current through R2 VIN VIN
below 250μA to balance between system
stability and no-load loss. Then R1 can be The worst-case condition occurs at VIN = 2VOUT,
calculated with Equation (2): calculated with Equation (4):

VOUT  VREF ICIN 

IOUT
(4)
R1   R2 (2) 2
VREF
For simplification, choose the input capacitor
Figure 5 shows the feedback circuit. with an RMS current rating greater than half of
the maximum load current.
VOUT
The input capacitance determines the input
CF voltage ripple of the converter. If there is an input
MPM3650 R1
RT voltage ripple requirement in the system, choose
an input capacitor that meets the relevant
FB specifications.
R2
The input voltage ripple can be estimated with
Equation (5):
Figure 5: Feedback Network
IOUT V V
Table 1 lists recommended resistor values for VIN   OUT  (1  OUT ) (5)
fSW  CIN VIN VIN
common output voltages.
Table 1: Resistor Selection for Common Output The worst-case condition occurs at VIN = 2VOUT,
Voltages calculated with Equation (6):
VOUT (V) R1 (kΩ) R2 (kΩ) CF (pF) RT (Ω) 1 I
VIN   OUT (6)
1.0 20 30 39 0 4 fSW  CIN
1.2 20 20 39 0
1.5 20 13 39 0 Selecting the Output Capacitor
1.8 20 10 39 0 The output capacitor is required to maintain the
2.5 20 6.34 39 0 DC output voltage. Ceramic or POSCAP
3.3 20 4.42 39 0 capacitors are recommended. The output
voltage ripple can be calculated with Equation
Selecting the Input Capacitor
(7):
The step-down converter has a discontinuous
input current, and requires a capacitor to supply VOUT V 1
VOUT   (1  OUT )  (RESR  ) (7)
the AC current to the converter while maintaining fSW  L VIN 8  fSW  COUT
the DC input voltage. Ceramic capacitors are
recommended for the best performance, and In the case of ceramic capacitors, the
should be placed as close to the VIN pin as capacitance dominates the impedance at the
possible. Capacitors with X5R and X7R ceramic switching frequency. The output voltage ripple is
dielectrics are recommended mainly caused by the capacitance.

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

For simplification, the output voltage ripple can 6. Connect VIN, VOUT, and GND to a large
be calculated with Equation (8): copper area to cool the chip, and to improve
thermal performance and long-term reliability.
VOUT V
VOUT   (1  OUT ) (8)
7. Separate input GNDs from the other GND
8  fSW  L  COUT
2
VIN
areas at the top layer. Connect them at the
In the case of POSCAP capacitors, the ESR internal layers and the bottom layer through
dominates the impedance at the switching multiple vias.
frequency. For simplification, the output ripple
8. Ensure an integrated GND is used at the
can be estimated with Equation (9):
internal layer or bottom layer.
VOUT V
VOUT   (1  OUT )  RESR (9) 9. Use multiple vias to connect the power
fSW  L VIN planes to internal layers.

In addition to consideration regarding the output

ripple, a larger output capacitor also offers better VIN VOUT
Top Layer
load transient response. However, maximum 2
2 2
Via
output capacitor limitation should be also
considered in design application. If the output Pads 1
1 1

capacitor value is too high, the output voltage GND

cannot reach the design value during the soft- GND
start time, and the device will fail to regulate. The
maximum output capacitor value (CO_MAX) can be Figure 6: Recommended PCB Layout
limited using Equation (10): Note:

CO _ MAX  (ILIM _ AVG  IOUT )  t ss / VOUT (10) 8) The recommended layout is based on the Typical Application
Circuits section on page 18.

Where ILIM_AVG is the average start-up current

during soft start, and tSS is the soft-start time.
PCB Layout Guidelines (8)
PCB layout is critical for stable operation. A 4-
layer layout is recommended to improve thermal
performance. For the best results, refer to
Figure 6 and follow the guidelines below:
1. Keep the power loop as small as possible.
2. Use a large ground plane to connect directly
to PGND. If the bottom layer is a ground
plane, add vias near PGND.
3. Ensure the high-current paths at GND and
VIN have short, direct, and wide traces.
4. Place the ceramic input capacitor, especially
the small package size (0402) input bypass
capacitor as close to the VIN and PGND pins
as possible to minimize high-frequency noise.
Keep the input capacitor and VIN pin traces
as short and wide as possible.
5. Place the VCC capacitor as close to the VCC
pin and GND as possible.

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

TYPICAL APPLICATION CIRCUITS

VIN
2.75V to 17V
C2

21

BST 15
C1
0.1μF R1
22μF x 2

VIN
499kΩ VOUT
9-12
16 OUT 1V
EN
R2 C3 C4
NS 22μF x 4 0.1μF

1-4, 24
PGND
6 GND
VCC SW
MPM3650 7, 8,13,
R4 14, 23
GND 20, 21
PG R3 C9
100kΩ 20kΩ 39pF
C5 (optional)
1μF 17 R6
19
SS FB

AGND
0Ω
AGND R5
30kΩ

18
R7

0Ω
AGND AGND

AGND GND

Figure 7: Typical Application Circuits with 1V Output

VIN
2.75V to 17V
C2
21

BST 15

C1
0.1μF R1
22μF x 2 VOUT
VIN

499kΩ 9-12
16 OUT 1.8V
EN
C4
R2 C3
0.1μF
NS 22μF x 4
1-4, 24
PGND
6 GND
VCC SW
7, 8, 13,
R4
20, 21
MPM3650 14, 23
GND PG C9
R3
100kΩ 20kΩ 39pF
C5 (optional)
17 R6
1μF 19
SS FB
0Ω
AGND

AGND R5
10kΩ
18

R7

0Ω
AGND AGND

AGND GND

Figure 8: Typical Application Circuits with 1.8V Output

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

VIN
2.75V to 17V

21

BST 15
C1 C2 R1
22μF x 2 0.1μF 499kΩ VOUT

VIN
9-12
16 OUT 3.3V
EN
C4
R2 C3 0.1μF
NS 22μF x 4
1-4,24
PGND
6 GND
VCC SW
MPM3650 7, 8, 13,
R4 14, 23
GND 20, 21
PG R3 C9
20kΩ 39pF
100kΩ
C5 (optional)
17 R6
1μF 19
SS FB

AGND
0Ω
AGND R5
4.42kΩ

18
R7

0Ω

AGND AGND

AGND GND

Figure 9: Typical Application Circuits with 3.3V Output

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 MPM3650 – 6A, STEP-DOWN POWER MODULE
PACKAGE OUTLINE DRAWING FOR 24L FCMQFN (4X6MM)
MF-PO-D-0441 revision 0.0
PACKAGE INFORMATION
QFN-24 (4mmx6mmx1.6mm)

PIN 1 ID
PIN 1 ID 0.25X45º TYP
MARKING

PIN 1 ID
INDEX AREA

TOP VIEW BOTTOM VIEW

SIDE VIEW

0.25X45º
NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) LEAD COPLANARITY SHALL BE 0.08
MILLIMETERS MAX.
3) JEDEC REFERENCE IS MO-220.
4) DRAWING IS NOT TO SCALE.

RECOMMENDED LAND PATTERN

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

CARRIER INFORMATION

Pin1 1 1 1 1
ABCD ABCD ABCD ABCD

Feed Direction

Carrier Carrier
Quantity/ Quantity/ Reel
Part Number Package Description Tape Tape
Reel Tube Diameter
Width Pitch
QFN-24
MPM3650GQW–Z 2500 N/A 13in 12mm 8mm
(4mmx6mmx1.6mm)

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 MPM3650 – 6A, STEP-DOWN POWER MODULE

Revision History
Revision Pages
Revision # Description
Date Updated
1.0 6/3/2020 Initial Release -

Notice: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third-party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.

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