o o o o - : 8.11 Memory Read and Write Bus Cycles

• Types of bus cycles:
o Memory Read Bus Cycle

o Memory Write Bus Cycle
o Input/Output Read Bus Cycle
o Input/Output Write Bus Cycle
• The bus cycle of the 8086 microprocessor consists of at least four clock
periods. These four time states are called T1, T2, T3 and T4.
8.11 MEMORY READ AND WRITE BUS CYCLES

• Fig. 8-22(a) shows a memory read cycle of the 8086:
• During period T1,

o The 8086 outputs the 20-bit address of the memory location to be
accessed on its multiplexed address/data bus. BHE is also output along
with the address during T1.
o At the same time a pulse is also produced at ALE. The trailing edge or
the high level of this pulse is used to latch the address in external
circuitry.
o Signal M/ IO is set to logic 1 and signal DT/ R is set to the 0 logic level
and both are maintained throughout all four periods of the bus cycle.
• Beginning with period T2,

o Status bits S3 through S6 are output on the upper four address bus lines.
This status information is maintained through periods T3 and T4.
o On the other hand, address/data bus lines AD0 through AD7 are put in the
high-Z state during T2.
o Late in period T2, RD is switched to logic 0. This indicates to the memory

subsystem that a read cycle is in progress. DEN is switched to logic 0 to
enable external circuitry to allow the data to move from memory onto the
microprocessor's data bus.

o The memory must provide valid data during T3 and maintain it until after
the processor terminates the read operation. The data read by the 8086
microprocessor can be carried over all 16 data bus lines
7
• During T4,
o The 8086 switches RD to the inactive 1 logic level to terminate the read
operation. DEN returns to its inactive logic level late during T4 to disable
the external circuitry.
• Fig. 8-22(b) shows a memory write cycle of the 8088:
o The address along with BHE are output and latched with the ALE pulse.
o M/ IO is set to logic 1 to indicate a memory cycle.
o However, this time DT/ R is switched to logic 1. This signals external

circuits that the 8086 is going to transmit data over the bus.
• Beginning with period T2,
o WR is switched to logic 0 telling the memory subsystem that a write

operation is to follow.
o The 8086 puts the data on the bus late in T2 and maintains the data valid
through T4. Data will be carried over all 16 data bus lines.
o DEN enables the external circuitry to provide a path for data from the
processor to the memory.
8
Figure 8-22(a) Minimum-mode memory read bus cycle of the 8086.
9
Figure 8-22(b) Minimum-mode memory write bus cycle of the 8086.
10
8.8 HARDWARE ORGANIZATION OF MEMORY ADDRESS SPACE
• The memory address space of the 8086-based microcomputers has different
logical and physical organizations (see Fig. 8-15).
• Logically, memory is implemented as a single 1M × 8 memory chunk. The

byte-wide storage locations are assigned consecutive addresses over the range
from 0000016 through FFFFF16.
• Physically, memory is implemented as two independent 512Kbyte banks: the

low (even) bank and the high (odd) bank. Data bytes associated with an even
address (0000016, 0000216, etc.) reside in the low bank, and those with odd
addresses (0000116, 0000316, etc.) reside in the high bank.
• Address bits A1 through A19 select the storage location that is to be accessed.
They are applied to both banks in parallel. A0 and bank high enable ( BHE ) are
used as bank-select signals.
Figure 8-15 (a) Logical memory organization, and (b) Physical memory organization
(high and low memory banks) of the 8086 microprocessor.
11
• Each of the memory banks provides half of the 8086's 16-bit data bus. The
lower bank transfers bytes of data over data lines D0 through D7, while data
transfers for a high bank use D8 through D15.
• The 8086 microprocessor accesses memory as follows:
• Fig. 8-17(a) shows how a byte-memory operation is performed to address X,

an even-addressed storage location. A0 is set to logic 0 to enable the low bank of
memory and BHE to logic 1 to disable the high bank. Data are transferred to or
from the lower bank over data bus lines D0 through D7.
• Fig. 8-17(b) shows how a byte-memory operation is performed to an odd-

addressed storage location such as X + 1. A0 is set to logic 1 and BHE to logic 0.
This enables the high bank of memory and disables the low bank. Data are
transferred over bus lines D8 through D15. D8 represents the LSB.
• Fig. 8-17(c) illustrates how an aligned word (at even address X) is accessed.
Both the high and low banks are accessed at the same time. Both A0 and BHE
are set to 0. This 16-bit word is transferred over the complete data bus D0
through D15 in just one bus cycle.
• Fig. 8-17(d) illustrates how a misaligned word (at address X + 1) is accessed.

Two bus cycles are needed. During the first bus cycle, the byte of the word
located at address X + 1 in the high bank is accessed over D8 through D15. Even
though the data transfer uses data lines D8 through D15, to the processor it is the
low byte of the addressed data word. In the second memory bus cycle, the even
byte located at X + 2 in the low bank is accessed over bus lines D0 through D7.
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o o o o - : 8.11 Memory Read and Write Bus Cycles

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• Types of bus cycles:

o Memory Read Bus Cycle

8.11 MEMORY READ AND WRITE BUS CYCLES

• During period T1,

• Beginning with period T2,

o Late in period T2, RD is switched to logic 0. This indicates to the memory

• During period T3,

• Fig. 8-22(b) shows a memory write cycle of the 8088:

• During period T1,

o M/ IO is set to logic 1 to indicate a memory cycle.

o However, this time DT/ R is switched to logic 1. This signals external

• Beginning with period T2,

o WR is switched to logic 0 telling the memory subsystem that a write

• Logically, memory is implemented as a single 1M × 8 memory chunk. The

• Physically, memory is implemented as two independent 512Kbyte banks: the

• The 8086 microprocessor accesses memory as follows:

• Fig. 8-17(a) shows how a byte-memory operation is performed to address X,

• Fig. 8-17(b) shows how a byte-memory operation is performed to an odd-

• Fig. 8-17(d) illustrates how a misaligned word (at address X + 1) is accessed.

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