IRFR3710ZPbF
IRFU3710ZPbF
IRFU3710Z-701PbF
HEXFET® Power MOSFET
Features
 Advanced Process Technology   VDSS 100V
 Ultra Low On-Resistance
 175°C Operating Temperature RDS(on) 18m
 Fast Switching
ID 42A
 Repetitive Avalanche Allowed up to Tjmax
 Multiple Package Options
D
 Lead-Free D

Description S S
D
This HEXFET® Power MOSFET utilizes the latest processing G G
techniques to achieve extremely low on-resistance per silicon D- Pak I- Pak
area. Additional features of this design are a 175°C junction IRFR3710ZPbF IRFU3710ZPbF
operating temperature, fast switching speed and improved I-Pak Lead form 701
repetitive avalanche rating . These features combine to make IRFU3710Z-701PbF
this design an extremely efficient and reliable device for use in Refer to page 11 for package outline
a wide variety of applications.
G D S
Gate Drain Source

Standard Pack
Base part number Package Type Orderable Part Number
Form Quantity
IRFU3710ZPbF I-Pak Tube 75 IRFU3710ZPbF
Tube 75 IRFR3710ZPbF
IRFR3710ZPbF D-Pak
Tape and Reel Left 3000 IRFR3710ZTRLPbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 56
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 39
A 
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited) 42
IDM Pulsed Drain Current  220
PD @TC = 25°C Maximum Power Dissipation 140 W
Linear Derating Factor 0.95 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS (Thermally limited) Single Pulse Avalanche Energy 150
mJ
EAS (Tested ) Single Pulse Avalanche Energy Tested Value 200
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy  mJ
TJ Operating Junction and -55 to + 175  
TSTG Storage Temperature Range °C 
Soldering Temperature, for 10 seconds (1.6mm from case) 300  

Thermal Resistance  
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.05
RJA Junction-to-Ambient ( PCB Mount)  ––– 50 °C/W
RJA Junction-to-Ambient ––– 110

1 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.088 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 15 18 m VGS = 10V, ID = 33A 
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA  
gfs Forward Trans conductance 39 ––– ––– S VDS = 25V, ID = 33A
––– ––– 20 VDS = 100V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 100V,VGS = 0V,TJ =125°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– -200 VGS = -20V
Qg Total Gate Charge ––– 69 100 ID = 33A
Qgs Gate-to-Source Charge ––– 15 ––– nC  VDS = 80V
Qgd Gate-to-Drain (‘Miller’) Charge ––– 25 ––– VGS = 10V 
td(on) Turn-On Delay Time ––– 14 ––– VDD = 50V
tr Rise Time ––– 43 ––– ID = 33A
ns
td(off) Turn-Off Delay Time ––– 53 ––– RG = 6.8
tf Fall Time ––– 42 ––– VGS = 10V 
Between lead,
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH  
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact
Ciss Input Capacitance ––– 2930 –––   VGS = 0V
Coss Output Capacitance ––– 290 ––– pF   VDS = 25V
Crss Reverse Transfer Capacitance ––– 180 –––   ƒ = 1.0MHz
Coss Output Capacitance ––– 1200 –––   VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 180 –––   VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 430 –––   VGS = 0V, VDS = 0V to 80V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
IS ––– ––– 56
(Body Diode) showing the
A
Pulsed Source Current integral reverse
ISM ––– ––– 220
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 33A,VGS = 0V 
trr Reverse Recovery Time ––– 35 53 ns TJ = 25°C ,IF = 33A, VDS = 50V
Qrr Reverse Recovery Charge ––– 41 62 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11).
 starting TJ = 25°C, L = 0.28mH, RG = 25, IAS = 33A,VGS =10V. Part not recommended for use above this value.
 Pulse width 1.0ms; duty cycle  2%.
 Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.
 This value determined from sample failure population. 100% tested to this value in production.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.
 Refer to D-Pak package for Part Marking, Tape and Reel information

2 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
6.0V 6.0V
5.0V 5.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

4.8V 4.8V
4.5V 100 4.5V
4.3V
4.3V
BOTTOM 4.0V BOTTOM 4.0V
100

4.0V
10

10
1
4.0V
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1 0.1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics

1000 100
Gfs, Forward Transconductance (S)
ID , Drain-to-Source Current )

T J = 175°C 80 T J = 25°C

100
60

T J = 175°C
40
10
T J = 25°C

20
VDS = 25V
V DS = 10V
60µs PULSE WIDTH
1.0 0
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 10 20 30 40 50 60 70 80
VGS, Gate-to-Source Voltage (V) ID,Drain-to-Source Current (A)

Fig. 3 Typical Transfer Characteristics Fig. 4 Typical Forward Transconductance

vs. Drain Current

3 2016-5-31
  
IRFR/U3710ZPbF & IRFU3710Z-701PbF

100000 12.0
VGS = 0V, f = 1 MHZ
ID= 33A
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd 10.0

VGS, Gate-to-Source Voltage (V)

VDS = 80V
10000 Coss = Cds + Cgd
VDS = 50V
C, Capacitance(pF)

8.0 VDS = 20V

Ciss

1000 6.0

Coss
Crss 4.0
100

2.0

10 0.0
1 10 100 0 10 20 30 40 50 60 70 80
VDS , Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 1000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.00 100
T J = 175°C

100µsec
10.00 10

T J = 25°C 1msec
1.00 1
Tc = 25°C
Tj = 175°C 10msec
VGS = 0V Single Pulse
0.10 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 10 100 1000
VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig. 7 Typical Source-to-Drain Diode

Fig 8. Maximum Safe Operating Area
Forward Voltage

  4 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

60 3.0
ID = 56A

RDS(on) , Drain-to-Source On Resistance

Limited By Package VGS = 10V
50
2.5
ID, Drain Current (A)

40
2.0

(Normalized)
30

1.5
20

1.0
10

0 0.5
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

TC , Case Temperature (°C) T J , Junction Temperature (°C)

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance
vs. Temperature

10

1
Thermal Response ( Z thJC )

D = 0.50
0.20
0.1 0.10
0.05
R1 R2 R3
0.02 R1 R2 R3 Ri (°C/W) i (sec)
J
0.01 0.01 J
C
C 0.576 0.000540
1 2 3
1 2 3 0.249 0.001424
Ci= iRi
Ci= iRi 0.224 0.007998
0.001 SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

5 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

700
ID

EAS , Single Pulse Avalanche Energy (mJ)

15V
600 TOP 3.4A
4.8A
L DRIVER 500 BOTTOM 33A
VDS

400
RG D.U.T +
V
- DD
IAS A
20V 300
tp 0.01

200
Fig 12a. Unclamped Inductive Test Circuit

100
V(BR)DSS
tp 0
25 50 75 100 125 150 175

Starting T J , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

I AS vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms

4.0
VGS(th) Gate threshold Voltage (V)

3.0

ID = 250µA

2.0

Fig 13a. Gate Charge Waveform

1.0
-75 -50 -25 0 25 50 75 100 125 150 175 200

T J , Temperature ( °C )

Fig 14. Threshold Voltage vs. Temperature

Fig 13b. Gate Charge Test Circuit

  6 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF
1000
Duty Cycle = Single Pulse

100
Allowed avalanche Current vs
Avalanche Current (A)

avalanche pulsewidth, tav

0.01
assuming  Tj = 25°C due to
avalanche losses
10 0.05

0.10

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current vs. Pulse width

200 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.infineon.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
ID = 33A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

150 temperature far in excess of Tjmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long as Tjmax is
not exceeded.
100 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
50
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed
0
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25 50 75 100 125 150 175
D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

Fig 16. Maximum Avalanche Energy PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
vs. Temperature Iav = 2T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav

7 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

8 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER
WITH ASSEMBLY INTERNATIONAL
LOT CODE 1234 RECTIFIER IRFR120 DATE CODE
ASSEMBLED ON WW 16, 2001 LOGO 116A YEAR 1 = 2001
IN THE ASSEMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in assembly line position ASSEMBLY
indicates "Lead-Free" LOT CODE
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level

PART NUMBER
INTERNATIONAL
OR RECTIFIER IRFR120
DATE CODE
P = DESIGNATES LEAD-FREE
LOGO PRODUCT (OPTIONAL)
12 34
P = DESIGNATES LEAD-FREE
ASSEMBLY PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
LOT CODE
YEAR 1 = 2001
WEEK 16
A = ASSEMBLY SITE CODE

Notes:
1. For an Automotive Qualified version of this part please seehttp://www.infineon.com/product-info/datasheets/data/auirfr3710z.pdf
2. For the most current drawing please refer to Infineon website at http://www.infineon.com/package/

  9 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: THIS IS AN IRFU120 PART NUMBER

INTERNATIONAL
WITH ASSEMBLY
RECTIFIER IRFU120 DATE CODE
LOT CODE 5678
LOGO 119A YEAR 1 = 2001
ASSEMBLED ON WW 19, 2001
56 78 WEEK 19
IN THE ASSEMBLY LINE "A"
LINE A
ASSEMBLY
LOT CODE
Note: "P" in assembly line position
indicates Lead-Free"

OR
PART NUMBER
INTERNATIONAL
RECTIFIER IRFU120 DATE CODE
LOGO P = DESIGNATES LEAD-FREE
56 78 PRODUCT (OPTIONAL)
YEAR 1 = 2001
ASSEMBLY
LOT CODE WEEK 19
A = ASSEMBLY SITE CODE

Notes:
1. For an Automotive Qualified version of this part please seehttp://www.infineon.com/product-info/auto/
2. For the most current drawing please refer to Infineon website at http://www.infineon.com/package/

10 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

I-Pak Leadform Option 701 Package Outline 

Dimensions are shown in millimeters (inches)

11 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF

D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to Infineon’s web site www.infineon.com

12 2016-5-31
 
IRFR/U3710ZPbF & IRFU3710Z-701PbF
Qualification Information†  
Industrial
Qualification Level  
(per JEDEC JESD47F) ††
D-Pak MSL1
Moisture Sensitivity Level
I-Pak (per JEDEC J-STD-020D) ††
RoHS Compliant Yes

† Qualification standards can be found at Infineon’s web site www.infineon.com

†† Applicable version of JEDEC standard at the time of product release.

Revision History

Date Comments
 Updated datasheet with corporate template.
5/31/2016
 Added disclaimer on last page.

Trademarks of Infineon Technologies AG 
µHVIC™, µIPM™, µPFC™, AU‐ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, 
DAVE™, DI‐POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, 
HEXFET™,  HITFET™,  HybridPACK™,  iMOTION™,  IRAM™,  ISOFACE™,  IsoPACK™,  LEDrivIR™,  LITIX™,  MIPAQ™,  ModSTACK™,  my‐d™,  NovalithIC™,  OPTIGA™, 
Op MOS™,  ORIGA™,  PowIRaudio™,  PowIRStage™,  PrimePACK™,  PrimeSTACK™,  PROFET™,  PRO‐SIL™,  RASIC™,  REAL3™,  SmartLEWIS™,  SOLID  FLASH™, 
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ 
 
Trademarks updated November 2015 
 
Other Trademarks 
All referenced product or service names and trademarks are the property of their respec ve owners. 

 Edi on 2016‐04‐19  IMPORTANT NOTICE  For further informa on on the product, technology, 

The informa on given in this document shall in no  delivery  terms  and  condi ons  and  prices  please 
Published by  event be regarded as a guarantee of condi ons or  contact  your  nearest  Infineon  Technologies  office 
Infineon Technologies AG  characteris cs  (“Beschaffenheitsgaran e”) .  (www.infineon.com). 
81726 Munich, Germany    
With  respect  to  any  examples,  hints  or  any  typical   
    Please  note  that  this  product  is  not  qualified 
values  stated  herein  and/or  any  informa on 
© 2016 Infineon Technologies AG.  regarding  the  applica on  of  the  product,  Infineon  according to the AEC Q100 or AEC Q101 documents 
All Rights Reserved.  Technologies  hereby  disclaims  any  and  all  of the Automo ve Electronics Council.  
   warran es  and  liabili es  of  any  kind,  including 
Do you have a ques on about this  without  limita on  warran es  of  non‐infringement  WARNINGS 
document?  of intellectual property rights of any third party.   Due  to  technical  requirements  products  may 
Email: [email protected]     contain  dangerous  substances.  For  informa on  on 
In addi on, any informa on given in this document  the  types  in  ques on  please  contact  your  nearest 
is  subject  to  customer’s  compliance  with  its  Infineon Technologies office.  
  obliga ons  stated  in  this  document  and  any   
Document reference  applicable  legal  requirements,  norms  and  Except  as  otherwise  explicitly  approved  by  Infineon 
standards concerning customer’s products and any  Technologies  in  a  wri en  document  signed  by 
ifx1  authorized representa ves of Infineon Technologies, 
use  of  the  product  of  Infineon  Technologies  in  Infineon Technologies’ products may not be used in 
customer’s applica ons.  any  applica ons  where  a  failure  of  the  product  or 
   any consequences of the use thereof can reasonably 
The data contained in this document is exclusively  be expected to result in personal injury.  
intended  for  technically  trained  staff.  It  is  the 
responsibility of customer’s technical departments 
to  evaluate  the  suitability  of  the  product  for  the 
intended  applica on  and  the  completeness  of  the 
product  informa on  given  in  this  document  with 
respect to such applica on. 
  
        

  13 2016-5-31