STLD LAB MANUAL ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SWITCHING THEORY AND LOGIC DESIGN

LABORATORY MANUAL

(R20) II B.Tech I-Semester

Name of the Student:

H. T. NO:

Academic Year: _

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INDEX
S,NO Name of the Exp DATE MARKS SIGN

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SWITCHING THEORY AND LOGIC DESIGN LAB

List of Experiments: (Minimum of Twelve Experiments has to be performed)

1. Verification of truth tables of Logicgates Two input (i) OR (ii) AND (iii) NOR (iv) NAND (v)
Exclusive OR (vi) Exclusive NOR

2. Design a simple combinational circuit with four variables and obtain minimal SOP expression
and verify the truth table using Digital TrainerKit

3. Verification of functional table of 3 to 8 line Decoder /De-multiplexer

4. 4 variable logic function verification using 8 to 1multiplexer.

5. Design full adder circuit and verify its functionaltable.

6. Verification of functional tablesof (i) J K Edge triggered Flip –Flop (ii) J K Master Slave Flip
– Flop (iii)D Flip -Flop

7. Design a four bit ring counter using D Flip – Flops / JK Flip Flop and verifyoutput

8. Design a four bit Johnson’s counter using D Flip-Flops / JK Flip Flops and verifyoutput

9. Verify the operation of 4-bit Universal Shift Register for different Modes ofoperation.

10. Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-FlipFlops
and Test it with a low frequency clock and Sketch the outputwaveforms.

11. Design MOD – 8 synchronous counter using T Flip-Flop and verify the result and Sketch the
outputwaveforms.

12. (a) Draw the circuit diagram of a single bit comparator and test theoutput (b) Construct 7
Segment Display Circuit Using Decoder and 7 Segment LED and testit.

ADD on Experiments:

1. Design BCD Adder Circuit and Test the Same using RelevantIC

2. Design Excess-3 to 9-Complement convertor using only four Full Adders and test the Circuit.

3. Design an Experimental model to demonstrate the operation of74154 De-Multiplexer using

LEDs foroutputs.

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EXPERIMENT No. 1

VERIFICATION OF TRUTH TABLES OF LOGICGATES

AIM: To study and verify the truth table of logic gates

LEARNING OBJECTIVE:
Identify various ICs and their specification.

COMPONENTS REQUIRED:
Logic gates (IC) trainer kit.
Connecting patch chords.
IC 7400, IC 7408, IC 7432, IC 74266, IC 7402, IC 7404, IC 7486

THEORY:
The basic logic gates are the building blocks of more complex logic circuits.
These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion,
Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is seen
from the Fig that each gate has one or two binary inputs, A and B, and one binary output, C. The small
circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND, and
NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs
if the binary operation it represents is commutative and associative. These basic logic gates are implemented
as small-scale integrated circuits (SSICs) or as part of more complex medium scale (MSI) or very large-
scale (VLSI) integrated circuits. Digital IC gates are classified not only by their logic operation, but also
the specific logic-circuit family to which they belong. Each logic family has its own basic electronic circuit
upon which more complex digital circuits and functions are developed. The following logic families are the
most frequently used.
TTL -Transistor-transistor logic
ECL -Emitter-coupled logic
MOS-Metal-oxide semiconductor
CMOS-Complementary metal-oxide semiconductor
TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity among logic
families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are based on field
effect transistors. They are widely used in large scale integrated circuits because of their high component
density and relatively low power consumption. CMOS logic consumes far less power than MOS logic.
There are various commercial integrated circuit chips available. TTL ICs are usually distinguished by
numerical designation as the 5400 and 7400 series.

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs

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LOGIC GATES SYMBOLS AND TRUTH TABLES

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LOGIC GATES PIN CONFIGURATIONS

NAND GATE IC
7400

ic

AND GATE IC
7408

OR GATE IC
7432

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NOR GATE IC
7402

EX-OR GATE IC
7486

EX-NOR GATE IC
74266

NOT GATE IC
7404

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Result: Hence study and verify the truth table of logic gates

VIVA QUESTIONS:
1. Why NAND & NOR gates are called universal gates?
2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC‟s and CMOS IC‟s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

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EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION

AIM: To simplify the given expression and to realize it using Basic gates and
Universal gates

LEARNING OBJECTIVE:
_ To simplify the Boolean expression and to build the logic circuit.
_ Given a Truth table to derive the Boolean expressions and build the logic circuit to
realize it.

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit.

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds to
a minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property.
Karnaugh Maps
For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

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For a function of four variables: f(w, x, y, z)

Realization of Boolean expression:

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PROCEDURE:
Check the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Provide the input data via the input switches and observe the output on output LEDs
Verify the Truth Table

RESULT: Simplified and verified the Boolean function using basic gates and universal gates

VIVA QUESTIONS:
1) What are the different methods to obtain minimal expression?
2) What is a Min term and Max term
3) State the difference between SOP and POS

4) What is meant by canonical representation?

5) What is K-map? Why is it used?

6) What are universal gates?

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Exp-3 3 TO 8 LINE DECODER

AIM:-To study the operation of 3 to 8 line decoder and verify the truth table

LEARNING OBJECTIVE:-
study the operation of 3 to 8 line decoder and verify the truth table

COMPONENTS REQUIRED:-
IC 74LS138, Patch Cords & IC Trainer Kit.

THEORY:-
74LS138 is a member from ‘74xx’family of TTL logic gates. The chip is designed
for decoding or de-multiplexing applications and comes with 3 inputs to 8 output setup. The
design is also made for the chip to be used in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times. In high performance memory systems
these decoders can be used to minimize the effects of system decoding. The three enable pins of
chip (in which Two active-low and one active-high) reduce the need for external gates or inverters
when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line
decoder requires only one inverter.
74LS138 is used in de-multiplexing applications by using enable pin as data input pin. Also the
chip inputs are clamped with high-performance Schottky diodes to suppress line-ringing and
simplify system design.

FIG:- 74LS138 PIN CONFIGURATION

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3 TO 8 DECODER LOGIC DIAGRAM

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TRUTH TABLE

PROCEDURE:

1. Connections are made as shown in the logic diagram using the pin details of the
gates.
2. Connect Vcc and GND to respective pins of each IC.
3. Connect the data, select and enable inputs to the toggle switches and outputs to the
LED‟s
4. Switch on the supply on the Trainer
5. Verify the truth table of the De-Multiplexer.

RESULT:-Hence study the operation of 3 to 8 line decoder and verify the truth table

Viva Questions:-

1. What are the Applications of Decoder

2. Difference between decoder and de-Mux
3. Draw the logic diagram of 2 to 4 decoder
4. Difference between encoder and decoder

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EXP-4 8X1 MUX

AIM:-To study the operation of 8X1 MUX and verify the truth table

LEARNING OBJECTIVE:-
study the operation of of 8X1 MUXand verify the truth table

COMPONENTS REQUIRED:-
IC 74LS151, Patch Cords & IC Trainer Kit.

Theory

Multiplexing is the property of combining one or more signals and transmitting on

a single channel .This is achieved by the device multiplexer. A multiplexer is the most frequently
used combinational circuits and important building block in many in digital systems.These are
mostly used to form a selected path between multiple sources and a single destination. A basic
multiplexer has various data input lines and a single output line. These are found in many digital
system applications such as data selection and data routing, logic function generators, digital
counters with multiplexed displays, telephone network, communication systems, waveform
generators, etc. In this article we are going to discuss about types of multiplexers and its design.
The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational circuit
with more than one input line, one output line and more than one select line. It allows the binary
information from several input lines or sources and depending on the set of select lines , particular
input line , is routed onto a single output line.

IC 74LS151:-

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Block Diagram and Truth Table:-

8X1 MUX Circuit Diagram

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PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs

RESULT:-Hence the operation of 8X1 MUX is studied and verify the truth table

Viva Questions:-

1. What are the Applications of MUX

2. Difference between mux and de-Mux
3. Draw the logic diagram of 4X1 mux
4. Implement 8X1 MUX using two 4X1 MUXs

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EXPERIMENT: 5 ADDERS

AIM: To realize Half Adder and Full Adder and verified truth tables

LEARNING OBJECTIVE:
▪ To realize the adder circuit using basic gates and universal gates
▪ To realize full adder using two half adders

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7486, IC 7432, Patch Cords & IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A
and B, is called a half-adder. Addition will result in two output bits; one of which is the
sum bit, S, and the other is the carry bit, C. The Boolean functions describing the half-
adder are:
S =A  B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into
account. This carry bit from its previous stage is called carry-in bit. A combinational
logic circuit that adds two data bits, A and B, and a carry-in bit, Cin , is called a full-
adder. The Boolean functions describing the full-adder are:
S = (x  y)  Cin C = xy + Cin (x  y)

TO REALIZE HALF ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

SUM=A  B

CARRY=A B

INPUTS OUTPUTS
A B S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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HALF ADDER CIRCUIT

FULL ADDER
SUM= A  B C

C=A B + B Cin + A Cin

TRUTH TABLE

INPUTS OUTPUTS
A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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FULL ADDER CIRCUIT

PROCEDURE:
 Check the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:Hence realize Half Adder and Full Adder and verified truth tables

VIVA QUESTIONS:

1) What is a half adder?

2) What is a full adder?
3) What are the applications of adders?
4) What is a half subtractor?
5) Realize a full adder using two half adders

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EXPERIMENT: 06 FLIP FLOPS

AIM: Verify the Truth Tables of Edge Triggered

1) D type Flip Flop.
2) JK Flip Flop
3)
LEARNING OBJECTIVE:
▪ To learn about various Flip-Flops
▪ To learn and understand the working of Master slave FF
▪ To learn about applications of FFs
▪ Conversion of one type of Flip flop to another

COMPONENTS REQUIRED:
IC 7474 , IC 7476 , Patch Cords & IC Trainer Kit.

THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their
output depends not only upon the present value of the input but also upon the previous
values.
Sequential logic circuits often require a timing generator (a clock) for their
operation. The latch (flip-flop) is a basic bi-stable memory element widely used in
sequential logic circuits. Usually there are two outputs, Q and its complementary
value.

D FLIP-FLOP BLOCK DIAGRAM

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D FLIPFLOP IC 7474

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JK FLIPFLOP

JK-FLIPFLOP BLOCK DIAGRAM

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JK-FLIPFLOP IC

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:- Hence verify Truth Table verification of

1) D type Flip Flop.
2) JK Flip Flop

VIVA QUESTIONS:
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?
7. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
8. List the functions of asynchronous inputs?

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EXPERIMENT: 07 JK-MASTER SLAVE FLIP FLOP

AIM: Verify the Truth Table of JK-Master Slave FlipFlop

LEARNING OBJECTIVE:
▪ To learn about various Flip-Flops
▪ To learn and understand the working of Master slave FF
▪ To learn about applications of FFs
▪ Conversion of one type of Flip flop to another

COMPONENTS REQUIRED:
IC 7473, Patch Cords & IC Trainer Kit.

THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their
output depends not only upon the present value of the input but also upon the
previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The
latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits.
Usually there are two outputs, Q and its complementary

JK-MASTER SLAVE BLOCK DIAGRAM

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JK-MASTER SLAVE LOGIC DIAGRAM

JK-MASTER SLAVE IC 7473

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PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:- Hence verify Truth Table of JK-Master Slave FF

VIVA QUESTIONS:

1.What is the difference between Flip-Flop & latch?

2.What is Race around condition
3.Explain different clock pulses
4.Give examples for synchronous & asynchronous inputs?
5.What are the applications of different Flip-Flops?

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Experiment No: 08 :

RING COUNTER USING D-FFs

AIM:
To design and set up four bit ring counter using D-FF

COMPONENTS REQUIRED:

Digital IC trainer kit, IC 7474

THEORY:

It is made by connecting Q&Q‟ output of one JK FF to J&K input of next FF respectively. The
output of final FF is connected to the input of first FF. To start the counter the first FF is set by using
preset facility and the remaining FF are reset input. When the clock arrives the set condition continues
to shift around the ring
As it can be seen from the truth table there are four unique output stages for this counter. The
modulus value of a ring counter is n, where n is the number of flip flops. Ring counter is called
divided by N counter where N is the number of FF

RING COUNTER USING D-FFs

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RING COUNTER TRUTH TABLE

RING COUNTER TIMING DIAGRAM

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PROCEDURE:

1. Set up the ring counter and set clear Q outputs using PRESET and apply mono pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.

RESULT :

Four bit ring counter is set up using the D FF and verified

VIVA QUESTIONS:
1.What is ring counter?
2.Applications of ring counter?
3.Difference between synchronous and asynchronous counter?
4.How many flip-flops required for 5-bit ring counter?

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Experiment No: 09 :

JHONSON COUNTER USING D-FFs

AIM:
To design and set up four bit jhonson counter using D-FF

COMPONENTS REQUIRED:

Digital IC trainer kit, IC 7474

THEORY
The modulus value of a ring counter can be doubled by making a small change in the ring counter
circuit. The Q‟ and Q of the last FFS are connected to the J and K input of the first FF respectively.
Johnson counter also known as creeping counter, is an example of synchronous counter.
In Johnson counter, the complemented output of last flip flop is connected to input of first
flip flop and to implement n-bit Johnson counter we require n flip-flop.It is one of the most
important type of shift register counter. It is formed by the feedback of the output to its
own input.Johnson counter is a ring with an inversion.Another name of Johnson counter
are:creeping counter, twisted ring counter, walking counter, mobile counter and switch tail
counter.

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JHONSON COUNTER using D-FF and Truth Table

JHONSON COUNTER TIMING DIAGRAM

PROCEDURE:

1.Set up the jhonson counter and set clear Q outputs using PRESET and apply mono pulse.
2.Note down the state of the jhonson counter on the truth table for successive clock 0.

RESULT :
Four bit Johnson counter were set up using the D FF and verified
Viva Q

1.What is jhonson counter?

2.Applications of jhonson counter?
3.Difference between ring and jhonson counter?
4.How many flip-flops required for 5-bit jhonson counter ?

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EXP-10:- 4-BIT UNIVERSAL SHIFT REGISTER

AIM:-To study the operation of 4-bit universal shift register and verify the truth table

LEARNING OBJECTIVE:-
study the operation of 4-bit universal shift register and verify the truth table

COMPONENTS REQUIRED:-
IC 74LS194, Patch Cords & IC Trainer Kit.

Pin Diagram

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CIRCUIT DIAGRAM

Theory

A Universal shift register is a register which has both the right shift and left shift with parallel load capabilities.
Universal shift registers are used as memory elements in computers. A Unidirectional shift register is capable
of shifting in only one direction. A bidirectional shift register is capable of shifting in both the directions. The
Universal shift register is a combination design of bidirectional shift register and a unidirectional shift
register with parallel load provision.
n-bituniversalshiftregister–A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers.
All the n multiplexers share the same select lines(S1 and S0)to select the mode in which the shift register
operates. The select inputs select the suitable input for the flip-flops.

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Basic connections –
1. The first input (zeroth pin of multiplexer) is connected to the output pin of the corresponding flip-
flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-previous flip flop
which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the very-next flip-flop
which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of the input data which
facilitates parallel loading.

RESULT:-Hence study the operation operation of 4-bit universal shift register and verify the
truth table

Viva Q

1.Define Register?

2.Purpose of USR?

3.Draw the logic diagram of 4-bit buffer register

4.what is bi-directional register?

5.Applications of Registers

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EXP11:- MOD – 8 RIPPLE counter

AIM:- To Design MOD – 8 ripple counter using D Flip-Flop and verify the result and Sketch the
outputwaveforms

LEARNING OBJECTIVE:
To realize MOD – 8 ripple counter using T Flip-Flop and verify the result and Sketch
the outputwaveforms

COMPONENTS REQUIRED:
D-FlipFlop IC , Patch Cords & IC Trainer Kit.

Theory

An Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit counter,
(0-15) making it ideal for use in Frequency Division applications. But it is also possible to use the
basic asynchronous counter configuration to construct special counters with counting states less
than their maximum output number. For example, modulo or MOD counters.
This is achieved by forcing the counter to reset itself to zero at a pre-determined value producing
a type of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up
to its maximum modulus ( 2n ) is called a full sequence counter and a n-bit counter whose modulus
is less than the maximum possible is called a truncated counter.
But why would we want to create an asynchronous truncated counter that is not a MOD-4, MOD-
8, or some other modulus that is equal to the power of two. The answer is that we can by using
combinational logic to take advantage of the asynchronous inputs on the flip-flop.
If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can
be made to give a decade (divide-by-10) counter output for use in standard decimal counting and
arithmetic circuits.
Such counters are generally referred to as Decade Counters. A decade counter requires resetting
to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do
this we need to feed this condition back to the reset input. A counter with a count sequence from
binary “0000” (BCD = “0”) through to “1001” (BCD = “9”) is generally referred to as a BCD
binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary
decade counters are more common.

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Truth Table

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TRUTH TABLE:-

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LOGIC DIAGRAM

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Timing Wave forms:-

PROCEDURE:
1. Set up the MOD – 8 ripple counter and set clear Q outputs using PRESET and
apply mono pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.

Result:-Hence Design MOD – 8 ripple counter using T Flip-Flop and verify the result and
Sketch the outputwaveforms

Viva Q
1.Draw the state diagram of MOD-4 counter
2.How many flip flops required for MOD-12 COUNTER
3.difference between ripple and synchronous counter
4.Define counter
5.Applications of counters

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EXP-12 1-BIT COMPARATOR

Aim:- Verify the operation of single bit comparator

COMPONENTS REQUIRED:
NOT IC , XNOR IC, AND IC , Patch Cords & IC Trainer Kit.

Theory:-
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B condition, one for A = B condition
and one for A < B condition. A comparator used to compare two bits is called a single bit
comparator. It consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.

TRUTH TABLE:-

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CIRCUIT DIAGRAM:-

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

Result:-Hence verify the operation of single bit comparator using logic gates

Viva Q

1.What is comparator
2.Draw the table for 2-bit comparator
3.Applcations of comparators

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