012 THURS - 215PM - 1450 Seidl - 0 - To - Safety - Accelerating - Functional - Safety - Projects
012 THURS - 215PM - 1450 Seidl - 0 - To - Safety - Accelerating - Functional - Safety - Projects
012 THURS - 215PM - 1450 Seidl - 0 - To - Safety - Accelerating - Functional - Safety - Projects
Accelerating Functional
Safety Projects
Senior Marketing Manager
Arm
Christopher Seidl
#ArmTechCon
Copyright © 2019 Arm TechCon, All rights reserved. 1
Agenda
System Design
Verification & System testing Test automation
Validation
Access protection
(MPU, TrustZone, Verification
Safety requirements
of safety
Fault Injection
stack overflow)
Likely SIL1
1 SIL2
2 SIL3
3 SIL4
4 5x
Very Likely SIL2
2 SIL3
3 SIL4
4 5x 6x
Certain SIL3
3 SIL4
4 5x 6x 7x
Cortex-R52
Virtualization
Cortex-R5 Bus protection
SW test library (STL)
Cortex-M7 System error
Cortex-M33 Bus ECC Bus ECC
Cortex-A55 Cortex-M23 Error management Error management
Cortex-A TCM ECC interface TCM ECC
& future Cortex-A TCM ECC
Cortex-M3/M4 MBIST interface MBIST interface
Armv8-A Dual core lockstep† MBIST interface
Dual core lockstep
Cortex-M0+ Cache parity / ECC Exception handling
Cache ECC
Dual core lockstep Dual core lockstep
Cache parity / ECC† Exception handling MPU Cache ECC Cache ECC
Exception handling Exception handling Exception handling
Exception handling MMU Stack limit check Exception handling
MPU MPU MPU
MMU RAS features SW test library (STL) Two-stage MPU
SW test library (STL)
Thread
Events Mutex
Semaphore
Event library (STL) • Medical: IEC 62304, Class C
Self-test code for • Railway: EN 50128, SIL 4
Time RTOS Scheduler Memory Recorder run-time verification
Supported processors:
FuSa CMSIS-Core CMSIS-Core
(device-specific) • Cortex-M0/M0+
(Arm-Core specific)
• Cortex-M3
FuSa C library • Cortex-M4
• Cortex-M7
Arm Cortex-M processor
FuSa RTS components certified with safety Arm C/C++ Compiler
• Tests save and restore the processor context to minimize side effects
DMA STL
Accelerator STL
Arm offers STLs that cover processor and core peripherals Peripheral STL
• Enable partners to perform simulation/execution for processor fault grading Peripheral STL
• Limit additional hardware needed for efficient testing of the CPU at run time .........
• Use existing processor resources for STL- execute from deterministic memory
Hardware
Software development
development
Hardware
Models are available early
development Fast and functionally accurate
TTM Non-intrusive debug, no HW dependency
Software development
Gain
Unlimited memory for unit testing
Debugger
Application Code
Event Annotations Software
Component Viewer
Description
Event Recorder (SCVD) file
Event Filter
The SCVD file
contains descriptive
Event Buffer information for
output formatting by
Memory the debugger.
Debugger
Application Code
while (1) {
EventStartA(0);
// user code
EventStopA(0);
...
EventStartB(0);
// user code
EventStopB(0);
}
Event Recorder
Up to 64 statistic slots can be defined For each statistic slot, statistical data is available:
with start/stop events in user code • Execution timing (total, average, min, max, first, last)
• Program details for min/max execution
Copyright © 2019 Arm TechCon, All rights reserved. 20
FuSa Development with MDK
Verification and validation during the development process
Arm offers a complete set of software tools that support development processes
• Arm Compiler with qualification kit and long-term support & maintenance
• IDE and Debuggers with scripting and features that simplify code and test development
• Simulation models for robust regression testing at function and module level
• Flexible debug adapters with test I/O pins for test automation with hardware
Safety Ready
Innovative safety
features for automotive Software tools Systematic
applications certification
Copyright © 2019
#ArmTechCon
Copyright © 2019 Arm TechCon, All rights reserved. 25