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DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

EE6008 – Microcontroller based system design

Year: IV Semester : VII
UNIT – I Introduction to PIC Microcontroller
PART – A
1. What is Microcontroller?
A device which contains the microprocessor with integrated peripherals like memory, serial ports, parallel ports,
timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called microcontroller.
2. What are the differences between a Microcontroller and Microprocessor?
Microprocessor Microcontroller
It is termed as general purpose digital computer. It is termed as special purpose digital controller.
It contains the CPU, memory, addressing circuits and It possesses all features of microprocessor and
interrupt handling circuit. additionally it includes timers, parallel and serial I/O
and the internal RAM and ROM.
It has one or two types of bit handling instructions. It has many bit handling instructions.
3. What is PIC Microcontroller?
PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip
microcontrollers. These devices have been very successful in 8-bit microcontrollers. The main reason is that
Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the
microcontroller to suit customers' requirements.
4. Draw the CPU architecture of PIC Microcontroller.
The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates
instruction fetch and the operation on data/accessing of variables simultaneously.

CPU Architecture of PIC microcontroller

5. What is Special Purpose register file?
The special purpose register file contains input and output ports as well as the control registers used to establish
each bit of a port as either an input or an output. It contains registers that provide the data input and data output
to the variety of resources on the chip, such as the timers, the serial ports and the ADC. It has registers that
contain control bits for selecting the mode of operation of a chip resource as well as enabling or disabling its
operation. It has registers containing status bits, which denote the state of one of these chip resources.
6.Give the register file structure of PIC Microcontroller.

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6. Draw the architecture of PIC 16C74A

7. What is ‘W’ register in PIC Microcontroller?

W, the working register, is used by many instructions as the source of an operand. This is similar to accumulator in 8051. It may also
serve as the destination for the result of the instruction execution. It is an 8 - bit register.

8. Give the status register of PIC Microcontroller. .(Nov/Dec 2016)

The STATUS register is an 8-bit register that stores the status of the processor. This also stores carry, zero and digit
carry bits.

STATUS - address 03H, 83H

9. What is program counter stack?

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Program Counter Stack

An independent 8-level stack is used for the program counter. As the program counter is 13bit, the stack is
organized as 8x13bit registers. When an interrupt occurs, the program counter is pushed onto the stack. When
the interrupt is being serviced, other interrupts remain disabled. Hence, other 7 registers of the stack can be
used for subroutine calls within an interrupt service routine or within the mainline program.
10. Draw the general block diagram of Harvard architecture.

11. What are the types of instruction set used in PIC microcontroller?
There are three types of instruction set used in PIC microcontroller.
1. Bit oriented instruction 2. Byte oriented instruction 3. Literal instructions.
12. What is bit and byte oriented instruction?
The byte oriented instructions that require two parameters (For example, movf f, F(W)) expect the f to be
replaced by the name of a special purpose register (e.g., PORTA) or the name of a RAM variable (e.g., NUM1),
which serves as the source of the operand. 'f' stands for file register. The F(W) parameter is the destination of the
result of the operation. It should be replaced by:F, if the destination is to be the source register.
W, if the destination is to be the working register (i.e., Accumulator or W register).
The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to be replaced by the name of a
special purpose register or the name of a RAM variable. The 'b' parameter is to be replaced by a bit number
ranging from 0 to 7.
For example:
Z equ 2
btfsc STATUS, Z

Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS register and will skip the next
instruction if Z bit is clear.

13. What are the addressing modes of PIC? .(Nov/Dec 2016)

Addressing is defined as how the operands are specified in the instruction. Direct addressing and indirect
addressing mode.
Indirectly addressing the memory used in FSR and INDF instruction. Here the operand is specified indirectly in
the instruction.
14.What do you mean by direct addressing mode and indirect addressing mode ?
It uses 7 bits of the instruction and the 8th bit from RP. It directly give the address where the data is present.ie, the
address of the operand is given in the instruction.
15.What is instruction pipelining?
It allows the CPU to fetch and execute at the same time while executing one instruction, CPU will fetch next
instruction to be executed.

PART-B
1. Explain with neat diagram the architecture of PIC16C6x and PIC16C7x microcontroller. (Nov/Dec 2016)
ARCHITECTURAL OVERVIEW

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The high performance of the PIC16CXX family can be attributed to a number of architectural features com-monly found
in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are
accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann
architecture where pro-gram and data may be fetched from the same memory using the same bus. Separating program
and data bus-ses further allows instructions to be sized differently than 8-bit wide data words. Instruction opcodes are
14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches
a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instruc-tions (Example 3-1).
Consequently, all instructions exe-cute in a single cycle (200 ns @ 20 MHz) except for program branches.
The PIC16C61 addresses 1K x 14 of program memory. The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 of
program memory, and the PIC16C63/R63/65/65A/R65 devices address 4K x 14 of program memory. The PIC16C66/67
address 8K x 14 program memory. All program memory is internal.

The PIC16CXX can directly or indirectly address its register files or data memory. All special function reg-isters
including the program counter are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical)
instruction set that makes it possible to carry out any operation on any register using any addressing mode. This
symmetrical nature and lack of “special optimal situations” makes programming with the PIC16CXX simple yet efficient,
thus significantly reducing the learning curve.
The PIC16CXX device contains an 8-bit ALU and work-ing register (W). The ALU is a general purpose arithme-tic unit.
It performs arithmetic and Boolean functions between data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, sub-traction, shift, and logical operations. Unless otherwise mentioned,
arithmetic operations are two's comple-ment in nature. In two-operand instructions, typically one operand is the working
register (W register), the other operand is a file register or an immediate con-stant. In single operand instructions, the
operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending upon the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero
(Z) bits in the STATUS register. Bits C and DC operate as a borrow and digit borrow out bit, respec-tively, in subtraction.
See the SUBLW and SUBWF instructions for examples.

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2. Explain with neat diagram the block diagram of PIC16C6x and PIC16C7x microcontroller

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3. With a neat diagram discuss in detail about memory organization of a PIC microcontroller.

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4. Explain in detail the register file structure and addressing modes of PIC microcontroller.
REGISTER FILE STRUCTURE
In PIC Microcontrollers the Register File consists of two parts namely
a) General Purpose Register File
b) Special Purpose Register File
a) General Purpose Register File:
The general purpose register file is another name for the microcontroller’s RAM . Data can be written to each 8-bit
location updated and retrieved any number of times.
b) Special Purpose Register File:
The special function register file consists of input, output ports and control registers used to configure each 8-bit port
either as input or output. It contains registers that provide the data input and data output to a chip resources like Timers,
Serial Ports and Analog to Digital converter and also the registers that contains control bits for selecting the mode of
operation and also enabling or disabling its operation.

ADDRESSING MODES.
The PIC microcontrollers support only TWO addressing modes .They are
(i) Direct Addressing Mode
(ii) Indirect Addressing mode
Direct Addressing Mode :
In direct addressing mode 7 bits (0-6) of the instruction identify the register file address and the 8 th bit of the
register file address register bank select bit(RP0).

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The above diagram explains the method of accessing register file address 13H by direct addressing method.
Indirect Addressing Mode
In the indirect addressing mode the 8-bit register file address is first written into a Special Function Register(SFR)
which acts as a pointer to any address location in the register file.A subsequent direct access of INDF will actually
access the register file using the content of FSR as a pointer to the desired location of the operand.

5. Explain the instruction set of PIC microcontroller. (Nov/Dec 2016)

Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one
or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary lists
byte-oriented, bit-ori-ented, and literal and control operations. Table 14-1 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file reg-ister designator and 'd' represents a destination desig-nator.
The file register designator specifies which file register is to be used by the instruction.
The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed
in the W register. If 'd' is one, the result is placed in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the
operation, while 'f' represents the number of the file in which the bit is located.
For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. The instruction set is
highly orthogonal and is grouped into three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

All instructions are executed within one single instruction cycle, unless a conditional test is true or the pro-gram counter
is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle
executed as a NOP. One instruc-tion cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4
MHz, the normal instruction execution time is 1 μs. If a conditional test is true or the program counter is changed as a
result of an instruc-tion, the instruction execution time is 2 μs.
: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

13 8 7 6 0
OPCO f (FILE
DE d #)

d = 0 for
destination W
d = 1 for
destination f
= 7-bit file register
f address
Bit-oriented file register operations
13 10 9 7 6 0
OPCO b (BIT f (FILE
DE #) #)

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b = 3-bit

bit address = 7bit

file register
f Address
Literal and control
operations
General
13 8 7 0
OPCO k
DE (literal)

= 8-bit immediate
k value
CALL and GOTO
instructions only
1 1
13 1 0 0
OPCOD
E k (literal)

= 11-bit
k immediate value

PIC16CXX INSTRUCTION SET

Mnemon Cycle 14-Bit Note
ic, Description s Opcode Status s
Operand Affecte
s MS d
b LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2

ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
1,2,
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
1,2,
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff
ffff 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff
ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff
ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff
ffff
000
NOP - No Operation 1 00 0000 0xx0 0

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RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2

RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2

BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3

LITERAL AND CONTROL OPERATIONS

C,DC,
ADDLW k Add literal and W 1 11 111x kkkk kkkk Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWD 010 T P
T - Clear Watchdog Timer 1 00 0000 0110 0 O ,D
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
100
RETFIE - Return from interrupt 2 00 0000 0000 1
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETUR 100
N - Return from Subroutine 2 00 0000 0000 0
001 T P
SLEEP - Go into standby mode 1 00 0000 0110 1 O ,D
C,DC,
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
if assigned to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.

6. Explain in detail the concept of pipelining of instructions in PIC microcontroller.

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and execute are pipelined
such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to

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the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change
(e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction
is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and
written during Q4 (destination write).
CLOCK/INSTRUCTION CYCLE

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and execute are pipelined
such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to
the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change
(e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction
is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and
written during Q4 (destination write).
CLOCK/INSTRUCTION CYCLE
Q Q Q Q
1 2 Q3 Q4 1 Q2 Q3 Q4 Q1 2 Q3 Q4

OSC1

Q1

Q2 Internal
Q3 Phase
Clock

Q4
P
PC C PC+1 PC+2
(Program
counter)
OSC2/CLKOU
T

(RC mode)
Fetch
INST (PC)
Execute Fetch INST
INST (PC-1) (PC+1)
Execute Fetch INST
INST (PC) (PC+2)

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Execute INST
(PC+1)

INSTRUCTION PIPELINE
FLOW
Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

MOV
1. LW 55h Fetch 1 Execute 1

MOV POR Execute

2. WF TB Fetch 2 2

CAL SUB
3. L _1 Fetch 3 Execute 3

PORTA, BIT3 (Forced

4. BSF NOP) Fetch 4 Flush
Fetch Execute
5. Instruction @ address SUB_1 SUB_1 SUB_1

All instructions are single cycle, except for any program branches. These take two cycles
since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.

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