PIC microcontroller

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PIC microcontrollers in DIP and QFN packages

16-bit 28-pin PDIP PIC24 microcontroller next to a metric ruler

PIC is a family of Harvard architecture microcontrollers made by Microchip Technology,
derived from the PIC1640[1] originally developed by General Instrument's
Microelectronics Division. The name PIC initially referred to "Programmable Interface
Controller".[2][3]
PICs are popular with both industrial developers and hobbyists alike due to their low
cost, wide availability, large user base, extensive collection of application notes,
availability of low cost or free development tools, and serial programming (and reprogramming with flash memory) capability.
Microchip announced on February 2008 the shipment of its six billionth PIC processor.[4]

Contents
[hide]

1 Core architecture
o 1.1 Data space (RAM)
o 1.2 Code space
o 1.3 Word size
o 1.4 Stacks
o 1.5 Instruction set
o 1.6 Performance

1.7 Limits
1.8 Compiler development
2 Family core architectural differences
o 2.1 Baseline core devices
o 2.2 Mid-range core devices
o 2.3 PIC17 high end core devices
o 2.4 PIC18 high end core devices
o 2.5 PIC24 and dsPIC 16-bit microcontrollers
o 2.6 PIC32 32-bit microcontrollers
3 Device variants and hardware features
o 3.1 Variants
o 3.2 Trends
4 History
5 Development tools
o 5.1 Commercially supported
o 5.2 Open source
6 Device programmers
o 6.1 Microchip programmers
o 6.2 Third-party programmers
7 Debugging
o 7.1 Software emulation
o 7.2 In-circuit debugging
o 7.3 In-circuit emulators
8 PIC clones
9 PICKit 2 open source structure and clones
10 8/16/32-bit PIC microcontroller product families
11 See also
12 References

13 External links

o
o

[edit] Core architecture

The PIC architecture is characterized by the following features:

Separate code and data spaces (Harvard architecture) for devices other than
PIC32, which has a Von Neumann architecture.
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock cycles), with one delay cycle
on branches and skips
One accumulator (W0), the use of which (as source operand) is implied (i.e. is not
encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math
and other functions.[2]
A hardware stack for storing return addresses

A fairly small amount of addressable data space (typically 256 bytes), extended
through banking
Data space mapped CPU, port, and peripheral registers
The program counter is also mapped into the data space and writable (this is used
to implement indirect jumps).

There is no distinction between memory space and register space because the RAM
serves the job of both memory and registers, and the RAM is usually just referred to as
the register file or simply as the registers.

[edit] Data space (RAM)

PICs have a set of registers that function as general purpose RAM. Special purpose
control registers for on-chip hardware resources are also mapped into the data space. The
addressability of memory varies depending on device series, and all PIC devices have
some banking mechanism to extend addressing to additional memory. Later series of
devices feature move instructions which can cover the whole addressable space,
independent of the selected bank. In earlier devices, any register move had to be achieved
via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register"
(INDF) are used. A register number is written to the FSR, after which reads from or
writes to INDF will actually be to or from the register pointed to by FSR. Later devices
extended this concept with post- and pre- increment/decrement for greater efficiency in
accessing sequentially stored data. This also allows FSR to be treated almost like a stack
pointer (SP).
External data memory is not directly addressable except in some high pin count PIC18
devices.

[edit] Code space

The code space is generally implemented as ROM, EPROM or flash ROM. In general,
external code memory is not directly addressable due to the lack of an external memory
interface. The exceptions are PIC17 and select high pin count PIC18 devices.[5]

[edit] Word size

The word size of PICs can be a source of confusion. All PICs handle (and address) data in
8-bit chunks, so they should be called 8-bit microcontrollers. However, the unit of
addressability of the code space is not generally the same as the data space. For example,
PICs in the baseline and mid-range families have program memory addressable in the
same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the
PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs
from the instruction width of 16 bits.

In order to be clear, the program memory capacity is usually stated in number of (single
word) instructions, rather than in bytes.

[edit] Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware
stack is not software accessible on earlier devices, but this changed with the 18 series
devices.
Hardware support for a general purpose parameter stack was lacking in early series, but
this greatly improved in the 18 series, making the 18 series architecture more friendly to
high level language compilers.

[edit] Instruction set

A PIC's instructions vary from about 35 instructions for the low-end PICs to over 80
instructions for the high-end PICs. The instruction set includes instructions to perform a
variety of operations on registers directly, the accumulator and a literal constant or the
accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered
register, but bi-operand arithmetic operations always involve W (the accumulator) ;
writing the result back to either W or the other operand register. To load a constant, it is
necessary to load it into W before it can be moved into another register. On the older
cores, all register moves needed to pass through W, but this changed on the "high end"
cores.
PIC cores have skip instructions which are used for conditional execution and branching.
The skip instructions are: 'skip if bit set', and, 'skip if bit not set'. Because cores before
PIC18 had only unconditional branch instructions, conditional jumps are implemented by
a conditional skip (with the opposite condition) followed by an unconditional branch.
Skips are also of utility for conditional execution of any immediate single following
instruction.
The PIC architecture has no (or very meager) hardware support for automatically saving
processor state when servicing interrupts. The 18 series improved this situation by
implementing shadow registers which save several important registers during an
interrupt.
In general, PIC instructions fall into 5 classes:
1. Operation on W with 8-bit immediate ("literal") operand. E.g. movlw (move literal
to W), andlw (AND literal with W). One instruction peculiar to the PIC is retlw,
load immediate into W and return, which is used with computed branches to
produce lookup tables.

2. Operation with W and indexed register. The result can be written to either the W
register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).
3. Bit operations. These take a register number and a bit number, and perform one of
4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to
perform conditional branches. The usual ALU status flags are available in a
numbered register so operations such as "branch on carry clear" are possible.
4. Control transfers. Other than the skip instructions previously mentioned, there are
only two: goto and call.
5. A few miscellaneous zero-operand instructions, such as return from subroutine,
and sleep to enter low-power mode.

[edit] Performance
The architectural decisions are directed at the maximization of speed-to-cost ratio. The
PIC architecture was among the first scalar CPU designs,[citation needed] and is still among the
simplest and cheapest. The Harvard architecturein which instructions and data come
from separate sourcessimplifies timing and microcircuit design greatly, and this
benefits clock speed, price, and power consumption.
The PIC instruction set is suited to implementation of fast lookup tables in the program
space. Such lookups take one instruction and two instruction cycles. Many functions can
be modelled in this way. Optimization is facilitated by the relatively large program space
of the PIC (e.g. 4096 x 14-bit words on the 16F690) and by the design of the instruction
set, which allows for embedded constants. For example, a branch instruction's target may
be indexed by W, and execute a "RETLW" which does as it is named - return with literal
in W.
Execution time can be accurately estimated by multiplying the number of instructions by
two cycles; this simplifies design of real-time code. Similarly, interrupt latency is
constant at three instruction cycles. External interrupts have to be synchronized with the
four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal
interrupts are already synchronized. The constant interrupt latency allows PICs to achieve
interrupt driven low jitter timing sequences. An example of this is a video sync pulse
generator.

[edit] Limits
The PIC architectures have several limits:

Only one accumulator

A small instruction set
Operations and registers are not orthogonal; some instructions can address RAM
and/or immediate constants, while others can only use the accumulator
Memory must be directly referenced in arithmetic and logic operations, although
indirect addressing is available via 2 additional registers
Register-bank switching is required to access the entire RAM of many devices

The following limitations have been addressed in the PIC18, but still apply to earlier
cores:

Conditional skip instructions are used instead of conditional jump instructions

used by most other architectures
Indexed addressing mode is very rudimentary
Stack:
o The hardware call stack is so small that program structure must often be
flattened
o The hardware call stack is not addressable, so pre-emptive task switching
cannot be implemented
o Software-implemented stacks are not efficient, so it is difficult to generate
reentrant code and support local variables
Program memory is not directly addressable, and thus space-inefficient and/or
time-consuming to access. (This is true of most Harvard architecture
microcontrollers.)

With paged program memory, there are two page sizes to worry about: one for CALL and
GOTO and another for computed GOTO (typically used for table lookups). For example,
on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048
instruction words. For computed GOTOs, where you add to PCL, the page size is 256
instruction words. In both cases, the upper address bits are provided by the PCLATH
register. This register must be changed every time control transfers between pages.
PCLATH must also be preserved by any interrupt handler.[6]

[edit] Compiler development

These properties have made it difficult to develop compilers that target PIC
microcontrollers. While several commercial compilers are available, in 2008, Microchip
finally released their C compilers, C18 and C30, for their line of 18f 24f and 30/33f
processors. By contrast, Atmel's AVR microcontrollerswhich are competitive with PIC
in terms of hardware capabilities and price, but feature a more traditional instruction set
have long been supported by the GNU C Compiler.
Also, because of these properties, PIC assembly language code can be difficult to
comprehend. Judicious use of simple macros can make PIC assembly language much
more palatable, but at the cost of a reduction in performance. For example, the original
Parallax PIC assembler ("SPASM") has macros which hide W and make the PIC look like
a two-address machine. It has macro instructions like "mov b, a" (move the data from
address a to address b) and "add b, a" (add data from address a to data in address b). It
also hides the skip instructions by providing three operand branch macro instructions
such as "cjne a, b, dest" (compare a with b and jump to dest if they are not equal).

[edit] Family core architectural differences

[edit] Baseline core devices

These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two
level deep call stack. They are represented by the PIC10 series, as well as by some PIC12
and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the
remaining bytes are general purpose RAM. If banked RAM is implemented, the bank
number is selected by the high 3 bits of the FSR. This affects register numbers 1631;
registers 015 are global and not affected by the bank select bits.
The ROM address space is 512 words (12 bits each), which may be extended to 2048
words by banking. CALL and GOTO instructions specify the low 9 bits of the new code
location; additional high-order bits are taken from the status register. Note that a CALL
instruction only includes 8 bits of address, and may only specify addresses in the first half
of each 512-word page.
The instruction set is as follows. Register numbers are referred to as "f", while constants
are referred to as "k". Bit numbers (07) are selected by "b". The "d" bit selects the
destination: 0 indicates W, while 1 indicates that the result is written back to source
register f.
12-bit PIC instruction set
Opcode (binary) Mnemonic
Description
0000 0000 0000 NOP
No operation
0000 0000 0010 OPTION
Load OPTION register with contents of W
0000 0000 0011 SLEEP
Go into standby mode
0000 0000 0100 CLRWDT
Reset watchdog timer
0000 0000 01ff TRIS f
Move W to port control register (f=1..3)
0000 001 fffff
0000 010 xxxxx
0000 011 fffff
0000 10d fffff
0000 11d fffff
0001 00d fffff
0001 01d fffff
0001 10d fffff
0001 11d fffff
0010 00d fffff
0010 01d fffff
0010 10d fffff
0010 11d fffff
0011 00d fffff

MOVWF f Move W to f
CLRW
Clear W to 0 (a.k.a CLR x, W)
CLRF f
Clear f to 0 (a.k.a. CLR f, F)
SUBWF f, d Subtract W from f (d = f W)
DECF f, d Decrement f (d = f 1)
IORWF f, d Inclusive OR W with F (d = f OR W)
ANDWF f, d AND W with F (d = f AND W)
XORWF f, d Exclusive OR W with F (d = f XOR W)
ADDWF f, d Add W with F (d = f + W)
MOVF f, d Move F (d = f)
COMF f, d Complement f (d = NOT f)
INCF f, d
Increment f (d = f + 1)
DECFSZ f, d Decrement f (d = f 1) and skip if zero
RRF f, d
Rotate right F (rotate right through carry)

RLF f, d
Rotate left F (rotate left through carry)
SWAPF f, d Swap 4-bit halves of f (d = f<<4 | f>>4)
0011 11d fffff INCFSZ f, d Increment f (d = f + 1) and skip if zero
0011 01d fffff
0011 10d fffff

BCF f, b
0101 bbb fffff BSF f, b
0110 bbb fffff BTFSC f, b
0111 bbb fffff BTFSS f, b
0100 bbb fffff

1000 kkkkkkkk
1001 kkkkkkkk
1010 kkkkkkkkk
1100 kkkkkkkk
1101 kkkkkkkk
1110 kkkkkkkk
1111 kkkkkkkk

RETLW k
CALL k
GOTO k
MOVLW k
IORLW k
ANDLW k
XORLW k

Bit clear f (Clear bit b of f)

Bit set f (Set bit b of f)
Bit test f, skip if clear (Test bit b of f)
Bit test f, skip if set (Test bit b of f)
Set W to k and return
Save return address, load PC with k
Jump to address k (9 bits!)
Move literal to W (W = k)
Inclusive or literal with W (W = k OR W)
AND literal with W (W = k AND W)
Exclusive or literal with W (W = k XOR W)

[edit] Mid-range core devices

These devices feature a 14-bit wide code memory, and an improved 8 level deep call
stack. The instruction set differs very little from the baseline devices, but the increased
opcode width allows 128 registers and 2048 words of code to be directly addressed. The
mid-range core is available in the majority of devices labeled PIC12 and PIC16.
The first 32 bytes of the register space are allocated to special-purpose registers; the
remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high
16 registers (0x700x7F) are global, as are a few of the most important special-purpose
registers, including the STATUS register which holds the RAM bank select bits. (The
other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the
PC high preload register PCLATH, and the master interrupt control register INTCON.)
The PCLATH register supplies high-order instruction address bits when the 8 bits
supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL
instruction, is not sufficient to address the available ROM space.

Opcode (binary)
00 0000 0000 0000
00 0000 0000 1000
00 0000 0000 1001
00 0000 0110 0010
00 0000 0110 0011
00 0000 0110 0100
00 0000 0110 01ff

14-bit PIC instruction set

Mnemonic
Description
NOP
No operation
RETURN
Return from subroutine, W unchanged
RETFIE
Return from interrupt
OPTION
Write W to OPTION register
SLEEP
Go into standby mode
CLRWDT Reset watchdog timer
TRIS f
Write W to tristate register f

00 0000 1 fffffff
00 0001 0 xxxxxxx
00 0001 1 fffffff
00 0010 d fffffff
00 0011 d fffffff
00 0100 d fffffff
00 0101 d fffffff
00 0110 d fffffff
00 0111 d fffffff
00 1000 d fffffff
00 1001 d fffffff
00 1010 d fffffff
00 1011 d fffffff
00 1100 d fffffff
00 1101 d fffffff
00 1110 d fffffff
00 1111 d fffffff

MOVWF f Move W to f
CLRW
Clear W to 0 (W = 0)
CLRF f
Clear f to 0 (f = 0)
SUBWF f, d Subtract W from f (d = f W)
DECF f, d Decrement f (d = f 1)
IORWF f, d Inclusive OR W with F (d = f OR W)
ANDWF f, d AND W with F (d = f AND W)
XORWF f, d Exclusive OR W with F (d = f XOR W)
ADDWF f, d Add W with F (d = f + W)
MOVF f, d Move F (d = f)
COMF f, d Complement f (d = NOT f)
INCF f, d
Increment f (d = f + 1)
DECFSZ f, d Decrement f (d = f 1) and skip if zero
RRF f, d
Rotate right F (rotate right through carry)
RLF f, d
Rotate left F (rotate left through carry)
SWAPF f, d Swap 4-bit halves of f (d = f<<4 | f>>4)
INCFSZ f, d Increment f (d = f + 1) and skip if zero

BCF f, b
BSF f, b
01 10 bbb fffffff BTFSC f, b
01 11 bbb fffffff BTFSS f, b
01 00 bbb fffffff
01 01 bbb fffffff

10 0 kkkkkkkkkkk
10 1 kkkkkkkkkkk
11 00xx kkkkkkkk
11 01xx kkkkkkkk
11 1000 kkkkkkkk
11 1001 kkkkkkkk
11 1010 kkkkkkkk
11 110x kkkkkkkk
11 111x kkkkkkkk

Bit clear f (Clear bit b of f)

Bit set f (Set bit b of f)
Bit test f, skip if clear (Test bit b of f)
Bit test f, skip if set (Test bit b of f)

CALL k
GOTO k

Save return address, load PC with k

Jump to address k (11 bits)

MOVLW k
RETLW k
IORLW k
ANDLW k
XORLW k
SUBLW k
ADDLW k

Move literal to W (W = k)
Set W to k and return
Inclusive or literal with W (W = k OR W)
AND literal with W (W = k AND W)
Exclusive or literal with W (W = k XOR W)
Subtract W from literal (W = k W)
Add literal to W (W = k + W)

[edit] PIC17 high end core devices

The 17 series never became popular and has been superseded by the PIC18 architecture.
It is not recommended for new designs, and availability may be limited.
Improvements over earlier cores are 16-bit wide opcodes (allowing many new
instructions), and a 16 level deep call stack. PIC17 devices were produced in packages
from 40 to 68 pins.

The 17 series introduced a number of important new features:

a memory mapped accumulator

read access to code memory (table reads)
direct register to register moves (prior cores needed to move registers through the
accumulator)
an external program memory interface to expand the code space
an 8-bit x 8-bit hardware multiplier
a second indirect register pair
auto-increment/decrement addressing controlled by control bits in a status register
(ALUSTA)

[edit] PIC18 high end core devices

Microchip introduced the PIC18 architecture in 2000. [3] Unlike the 17 series, it has
proven to be very popular, with a large number of device variants presently in
manufacture. In contrast to earlier devices, which were more often than not programmed
in assembly, C has become the predominant development language [4].
The 18 series inherits most of the features and instructions of the 17 series, while adding
a number of important new features:

much deeper call stack (31 levels deep)

the call stack may be read and written
conditional branch instructions
indexed addressing mode (PLUSW)
extending the FSR registers to 12 bits, allowing them to linearly address the entire
data address space
the addition of another FSR register (bringing the number up to 3)

The auto increment/decrement feature was improved by removing the control bits and
adding four new indirect registers per FSR. Depending on which indirect file register is
being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or
form the effective address by adding W to FSR.
In more advanced PIC18 devices, an "extended mode" is available which makes the
addressing even more favorable to compiled code:

a new offset addressing mode; some addresses which were relative to the access
bank are now interpreted relative to the FSR2 register
the addition of several new instructions, notable for manipulating the FSR
registers.

These changes were primarily aimed at improving the efficiency of a data stack
implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items

may be easily indexedallowing more efficient re-entrant code. Microchip's MPLAB

C18 C compiler chooses to use FSR2 as a frame pointer.

[edit] PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips,[7] which entered mass
production in late 2004. They are Microchip's first inherently 16-bit microcontrollers.
PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include
digital signal processing capabilities in addition.
Architecturally, although they share the PIC moniker, they are very different from the 8bit PICs. The most notable differences are:[8]

they feature a set of 16 working registers (W0-W15)

they fully support a stack in RAM, and do not have a hardware stack
bank switching is not required to access RAM or special function registers
data stored in program memory can be accessed directly using a feature called
Program Space Visibility
interrupt sources may be assigned to distinct handlers using an interrupt vector
table

Some features are:

hardware MAC (multiply-accumulate)

barrel shifting
bit reversal
(1616)-bit single-cycle multiplication and other DSP operations
hardware divide assist (19 cycles for 16/32-bit divide)
hardware support for loop indexing
Direct memory access

dsPICs can be programmed in C using a variant of gcc.

[edit] PIC32 32-bit microcontrollers

In November 2007 Microchip introduced the new PIC32MX family of 32-bit
microcontrollers. The initial device line-up is based on the industry standard MIPS32
M4K Core[5]. The device can be programmed using the Microchip MPLAB C Compiler
for PIC32 MCUs, a variant of the GCC compiler. The first 18 models currently in
production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the
same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices allowing the
use of common libraries, software and hardware tools.
The PIC32 architecture brings a number of new features to Microchip portfolio,
including:

The highest execution speed 80 MIPS (120+[9] Dhrystone MIPS @ 80 MHz)

The largest flash memory: 512 kByte
One instruction per clock cycle execution
The first cached processor
Allows execution from RAM
Full Speed Host/Dual Role and OTG USB capabilities
Full JTAG and 2 wire programming and debugging
Real-time trace

[edit] Device variants and hardware features

PIC devices generally feature:

Sleep mode (power savings).

Watchdog timer.
Various crystal or RC oscillator configurations, or an external clock.

[edit] Variants
Within a series, there are still many device variants depending on what hardware
resources the chip features.

General purpose I/O pins.

Internal clock oscillators.
8/16/32 Bit Timers.
Internal EEPROM Memory.
Synchronous/Asynchronous Serial Interface USART.
MSSP Peripheral for IC and SPI Communications.
Capture/Compare and PWM modules.
Analog-to-digital converters (up to ~1.0 MHz).
USB, Ethernet, CAN interfacing support.
External memory interface.
Integrated analog RF front ends (PIC16F639, and rfPIC).
KEELOQ Rolling code encryption peripheral (encode/decode)
And many more.

[edit] Trends
The first generation of PICs with EPROM storage are almost completely replaced by
chips with Flash memory. Likewise, the original 12-bit instruction set of the PIC1650 and
its direct descendants has been superseded by 14-bit and 16-bit instruction sets.
Microchip still sells OTP (one-time-programmable) and windowed (UV-erasable)
versions of some of its EPROM based PICs for legacy support or volume orders. The
Microchip website lists PICs that are not electrically erasable as OTP despite the fact that
UV erasable windowed versions of these chips can be ordered.

[edit] History
The original PIC was built to be used with General Instruments' new 16-bit CPU, the
CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8bit PIC was developed in 1975 to improve performance of the overall system by
offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to
perform its tasks, and although the term wasn't used at the time, it shares some common
features with RISC designs.
In 1985 General Instruments spun off their microelectronics division, and the new
ownership canceled almost everything which by this time was mostly out-of-date. The
PIC, however, was upgraded with internal EPROM to produce a programmable channel
controller, and today a huge variety of PICs are available with various on-board
peripherals (serial communication modules, UARTs, motor control kernels, etc.) and
program memory from 256 words to 64k words and more (a "word" is one assembly
language instruction, varying from 12, 14 or 16 bits depending on the specific PIC micro
family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally
thought that PIC stands for Peripheral Interface Controller, although General
Instruments' original acronym for the initial PIC1640 and PIC1650 devices was
"Programmable Interface Controller".[2] The acronym was quickly replaced with
"Programmable Intelligent Computer".[3]

Various older (EPROM) PIC microcontrollers

The Microchip 16C84 (PIC16x84), introduced in 1993 [6] was the first[citation needed]
Microchip CPU with on-chip EEPROM memory. This electrically-erasable memory
made it cost less than CPUs that required a quartz "erase window" for erasing EPROM.

[edit] Development tools

[edit] Commercially supported

Microchip provides a freeware IDE package called MPLAB, which includes an

assembler, linker, software simulator, and debugger. They also sell C compilers for the
PIC18 and dsPIC which integrate cleanly with MPLAB. Free student versions of the C
compilers are also available with all features. But for the free versions, optimizations will
be disabled after 60 days.[10]
Several third parties make C,[11] BASIC[12] and Pascal[13] language compilers for PICs,
many of which integrate to MPLAB and/or feature their own IDE. A fully featured
compiler for the PICBASIC language to program PIC microcontrollers is available from
meLabs, Inc.
A blockset[14] for Matlab/Simulink allows one to generate C and binary files from a
Simulink model. Most common peripherals have a blockset and you do not need to write
the configuration code.

[edit] Open source

The following development tools are available for the PIC family under the GPL or other
free software or open sources licenses.

FlashForth is a native Forth operating system for the PIC18F and the dsPIC30F
series. It makes the PIC a standalone computer with an interpreter, compiler,
assembler and multitasker.
FreeRTOS is a mini real time kernel ported to the PIC18, PIC24, dsPIC and
PIC32 architectures.
GNU Compiler Collection and the GNU Binutils have been ported to the PIC24,
dsPIC30F and dsPIC33F in the form of Microchip's MPLAB C30 compiler and
MPLAB ASM30 assembler.
GPSIM is an Open Source simulator for the PIC microcontrollers featuring
hardware modules that simulate specific devices that might be connected to them,
such as LCDs.
GPUTILS is a set of PIC utilities comprising an assembler, a disassembler, a
linker and an object file viewer.
Great Cow Basic (GCBasic) The syntax of Great Cow BASIC is based on that of
QBASIC/FreeBASIC. The assembly code produced can be assembled and run on
almost all 10, 12, 16 and 18 series PIC chips.
Ktechlab is a free IDE for programming PIC Microcontroller. It allows one to
write the program in C, Assembly, Microbe (a BASIC-like language) and using
FlowChart Method.
JAL [7] stands for Just Another Language. It is a Pascal-like language that is
easily mastered. The compiler supports a few Microchip (16c84, 16f84, 12c508,
12c509, 16F877) and SX microcontrollers. The resulting assembly language can
then be viewed, modified and further processed as if you were programming
directly in assembler.
JAL is now replaced with JALV2, a much superior open source compiler, that can
run on Windows, Linux and Mac OS. JALV2 supports 10F,12F,16F and 18F

series PICS. There is a set of libraries which are again open source maintained by
jallib
MIOS is a real-time operating system written in PIC assembly, optimized for
MIDI processing and other musical control applications. There is a C wrapper for
higher level development. Currently it runs on the MIDIbox Hardware Platform.
picforth is a Unix hosted Forth compiler written in gforth and generates code for
the Microchip PIC 16F87x and 16F88 microcontrollers family. It includes two
kinds of cooperative schedulers.
PiKdev runs on Linux and is a simple graphic IDE for the development of PICbased applications. It currently supports assembly language. Non Open Source C
language (Currently free 1/22/07) is also supported for PIC 18 devices. PiKdev is
developed in C++ under Linux and is based on the KDE environment.
Piklab is a forked version of PiKdev and is managed as SourceForge Project.
Piklab adds to Pikdev by providing support for programmers and debuggers.
Currently, Piklab supports the JDM, PIC Elmer, K8048, HOODMICRO, ICD1,
ICD2, PICkit1, PICKkit2, and PicStart+ as programming devices and has
debugging support for ICD2 in addition to using the simulator, GPSim.[15]
Pic Micro Pascal (PMP) is a free Pascal language compiler and IDE. It is intended
to work with the Microchip MPLAB, using its device definition files, assembler
and linker. It supports PIC10 to PIC18 devices.
SDCC is a C compiler supporting 8-bit PIC micro controllers (PIC16, PIC18).
Currently, throughout the SDCC website, the words, "Work is in progress", are
frequently used to describe the status of SDCC's support for PICs.

[edit] Device programmers

A development board for low pin-count MCU, from Microchip

Devices called "programmers" are traditionally used to get program code into the target
PIC. Most PICs that Microchip currently sell feature ICSP (In Circuit Serial
Programming) and/or LVP (Low Voltage Programming) capabilities, allowing the PIC to
be programmed while it is sitting in the target circuit. ICSP programming is performed
using two pins, clock and data, while a high voltage (12V) is present on the Vpp/MCLR
pin. Low voltage programming dispenses with the high voltage, but reserves exclusive
use of an I/O pin and can therefore be disabled to recover the pin for other uses (once
disabled it can only be re-enabled using high voltage programming).

There are many programmers for PIC microcontrollers, ranging from the extremely
simple designs which rely on ICSP to allow direct download of code from a host
computer, to intelligent programmers that can verify the device at several supply
voltages. Many of these complex programmers use a pre-programmed PIC themselves to
send the programming commands to the PIC that is to be programmed. The intelligent
type of programmer is needed to program earlier PIC models (mostly EPROM type)
which do not support in-circuit programming.
Many of the higher end flash based PICs can also self-program (write to their own
program memory). Demo boards are available with a small bootloader factory
programmed that can be used to load user programs over an interface such as RS-232 or
USB, thus obviating the need for a programmer device. Alternatively there is bootloader
firmware available that the user can load onto the PIC using ICSP. The advantages of a
bootloader over ICSP is the far superior programming speeds, immediate program
execution following programming, and the ability to both debug and program using the
same cable.

[edit] Microchip programmers

Microchip PICSTART Plus programmer

There are many programmers/debuggers available directly from Microchip.
Current Microchip programmers (as of 1/2010)[16]

PICKit 3 (USB interface)

PICStart Plus (RS232 serial interface) : intelligent.
MPLAB ICD 3 (USB 2.0 interface)
MPLAB PM3 (RS232 serial and USB interface)
MPLAB REAL ICE (USB 2.0 interface) : ICSP programming only

Legacy Microchip programmers

PICKit 2 (USB interface)

MPLAB ICD2 (RS232 serial and USB 1.0 interface) : ICSP programming only
PICKit 1 (USB interface)
PRO MATE II (RS232 serial interface) : intelligent.

[edit] Third-party programmers

There are programmers available from other sources, ranging from plans to build your
own, to self-assembly kits and fully tested ready-to-go units. Some are simple designs
which require a PC to do the low-level programming signalling (these typically connect
to the serial or parallel port and consist of a few simple components), while others have
the programming logic built into them (these typically use a serial or USB connection,
are usually faster, and are often built using PICs themselves for control). For a directory
of PIC related tools and websites, see PIC microcontroller at the Open Directory Project.
These are some common programmer types:

Simple serial port ICSP programmers

o These generally rely on driving the PIC's Vss line negative to get the
necessary voltage differences from programming. Hence they are compact
and cheap but great care is needed if using them for in circuit
programming.
Simple parallel port ICSP programmers
o Simple to understand but often have much higher part counts and
generally require external power supplies.
Intelligent programmers (some use USB port)
o Generally faster and more reliable (especially on laptops which tend to
have idiosyncrasies in the way they implement their ports) but far more
complex to build (in particular they tend to use a PIC in the programmer
which must itself be programmed somehow).

Here are some programmers available:

Usbpicprog
PICPgm - PIC Development Programmer for Windows and Linux. Supports 10F,
12F, 16F, 18F and dsPIC devices and a lot of different programmer hardware like
JDM, Tait, AN589, ...
usbpicprog, an open source USB PIC programmer usbpicprog
Open Programmer, another open source USB programmer for PICmicro and I2C
EEPROM, using HID class OpenProgrammer
home-made ICSP JDM Pic
DIY PIC and EEPROM programmer with ICSP support. PCB files, photos and
detailed information are also provided.

PIC PRESTO that supports ICSP, ISP, JTAG, I2C, SPI, Microwire interfaces,
works on USB and complies with programming specifications
home-made ICSP with external powersupply based on JDM: BobProg
(Romanian)

The major problem of home-made or very simple programmers is that these programmers
do not comply with programming specifications and this can cause premature loss of data
in the flash or EEPROM[citation needed].

[edit] Debugging
[edit] Software emulation
MPLAB (which is a free download) includes a software emulator for PICs. However,
software emulation of a microcontroller will always suffer from limited simulation of the
device's interactions with its target circuit.
Proteus VSM is a commercial software product developed by Labcenter Electronics
which allows simulation of many PICmicro devices along with a wide array of peripheral
devices. This method can help bridge the gap between the limited peripheral support
offered by the MPLAB simulator and traditional in-circuit debugging/emulating. The
product interfaces directly with MPLAB to offer a schematic display of signals and
peripheral devices.
KTechLab is a free and open source circuit simulator for KDE which features simulating
some types of PIC microcontrollers besides many other analog and digital parts.
Piklab is a free and open source IDE for developing PIC software on KDE. Piklab is able
to simulate and debug PIC software using another free and open source tool called gpsim
as a backend.
Real Pic Simulator is a commercial software developed by Digital Electro Soft. It is the
most powerful simulation engine in terms of simulated instructions per second.

[edit] In-circuit debugging

Later model PICs feature an ICD (in-circuit debugging) interface, built into the CPU
core. ICD debuggers (MPLAB ICD2 and other third party) can communicate with this
interface using three lines. This cheap and simple debugging system comes at a price
however, namely limited breakpoint count (1 on older pics 3 on newer PICs), loss of
some IO (with the exception of some surface mount 44-pin PICs which have dedicated
lines for debugging) and loss of some features of the chip. For small PICs, where the loss
of IO caused by this method would be unacceptable, special headers are made which are
fitted with PICs that have extra pins specifically for debugging.

[edit] In-circuit emulators

Microchip offers three full in circuit emulators: the MPLAB ICE2000 (parallel interface,
a USB converter is available); the newer MPLAB ICE4000 (USB 2.0 connection); and
most recently, the REAL ICE. All of these ICE tools can be used with the MPLAB IDE
for full source-level debugging of code running on the target.
The ICE2000 requires emulator modules, and the test hardware must provide a socket
which can take either an emulator module, or a production device.
The REAL ICE connects directly to production devices which support in-circuit
emulation through the PGC/PGD programming interface, or through a high speed
connection which uses two more pins. According to Microchip, it supports "most" flashbased PIC, PIC24, and dsPIC processors.[17]
The ICE4000 is no longer directly advertised on Microchip's website, and the purchasing
page states that it is not recommended for new designs.

[edit] PIC clones

Ubicom (formerly Scenix) produces the SX family of microcontrollers. These are

baseline core PIC clones that run much faster than the original. As of November
2005 Parallax is the exclusive supplier of the SX.
OpenCores has a PIC16F84 core written in Verilog.
Holtek HT48FXX Flash I/O type series
ANGSTREM produces 8-bit 4 MIPS (at 8 MHz) microcontroller An15E03
(18781 in Russian) which is pin-compatible with PIC16F84, but has
original arcitecture.

[edit] PICKit 2 open source structure and clones

PICKit 2 has been an interesting PIC programmer from Microchip. It can program all
PICs and debug most of the PICs (as of May-2009, only the PIC32 family is not
supported for MPLAB debugging). Ever since its first releases, all software source code
(firmware, PC application) and hardware schematic are open to the public. This makes it
relatively easy for an end user to modify the programmer for use with a non-Windows
operating system such as Linux or Mac OS. In the mean time, it also creates lots of DIY
interest and clones. This open source structure brings many features to the PICKit 2
community such as Programmer-to-Go, the UART Tool and the Logic Tool, which have
been contributed by PICKit 2 users. Users have also added such features to the PICKit 2
as 4MB Programmer-to-go capability, USB buck/boost circuits, RJ12 type connectors
and others.

[edit] 8/16/32-bit PIC microcontroller product families

These links take you to product selection matrices at the manufacturer's site.
8-bit microcontrollers

PIC10
PIC12
PIC14
PIC16
PIC17
PIC18

16-bit microcontrollers

PIC24F
PIC24H

32-bit microcontrollers

PIC32

16-bit digital signal controllers

dsPIC30
dsPIC33F

The F in a name generally indicates the PICmicro uses flash memory and can be erased
electronically. A C generally means it can only be erased by exposing the die to
ultraviolet light (which is only possible if a windowed package style is used). An
exception to this rule is the PIC16C84 which uses EEPROM and is therefore electrically
erasable.
The PIC's "code protection" features are not at all perfect; To some extent, the
weaknesses repeat themselves across the entire line of devices. But it should also be
acknowledged that Microchip has pushed out targeted revisions to the code protection
system as hacks have become widely known. Flylogic Engineering has documented some
of this ongoing back-and-forth on their website.

[edit] See also

PIC16x84
Arduino
BASIC Atom
BASIC Stamp
Dwengo
OOPic

PICAXE
TI MSP430

[edit] References
1. ^ "PICmicro Family Tree", PIC16F Seminar Presentation
http://www.microchip.com.tw/PDF/2004_spring/PIC16F%20seminar
%20presentation.pdf
2. ^ a b "MOS DATA 1976", General Instrument 1976 Databook
3. ^ a b "1977 Data Catalog", Micro Electronics from General Instrument
Corporation http://www.rhoent.com/pic16xx.pdf
4. ^ Microchip Technology (27 February 2008). "Microchip Technology Delivers
Six Billionth PIC Microcontroller". Press release.
http://www.microchip.com/stellent/idcplg?
IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en534302.
5. ^ "AN869: External Memory Interfacing Techniques for the PIC18F8XXX".
http://ww1.microchip.com/downloads/en/AppNotes/00869b.pdf. Retrieved 24
August 2009.
6. ^ "PIC Paging and PCLATH"
7. ^ [1]
8. ^ "PIC24H Family Overview".
http://ww1.microchip.com/downloads/en/DeviceDoc/70166A.pdf. Retrieved 23
September 2007.
9. ^ "32-bit PIC MCUs". http://www.microchip.com/en_US/family/pic32/.
Retrieved 13 October 2010.
10. ^ "MPLAB C Compiler for PIC18 MCUs".
http://www.microchip.com/stellent/idcplg?
IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en010014.
11. ^ "Massmind: PIC Micro Controller C/C++ Languages".
http://techref.massmind.org/techref/microchip/language/cs.htm.
12. ^ "Oshon Software Project". http://oshonsoft.com.
13. ^ "mikroElectronika Compilers". http://www.mikroe.com/en/compilers/.
14. ^ "dsPIC blockset for simulink". http://www.kerhuel.eu/RTWdsPIC.
15. ^ "Piklab Homepage". SourceForge.net. 14 November 2007.
http://piklab.sourceforge.net/. Retrieved 16 August 2008.
16. ^ "Microchip Development Tools Showcase".
http://www.microchip.com/stellent/idcplg?
IdcService=SS_GET_PAGE&nodeId=81. Retrieved 4 January 2010.
17. ^ "MPLAB REAL ICE In-Circuit Emulator Product Overview".
http://ww1.microchip.com/downloads/en/DeviceDoc/51630a.pdf. Retrieved 23
September 2007.