ACS725 Datasheet

ACS725
Automotive-Grade, Galvanically Isolated Current Sensor IC

with Common-Mode Field Rejection in a Small Footprint SOIC8 Package
FEATURES AND BENEFITS DESCRIPTION

• AEC-Q100 qualified The Allegro™ ACS725 current sensor IC is an economical and
• Differential Hall sensing rejects common-mode fields precise solution for AC or DC current sensing in industrial,
• 1.2 mΩ primary conductor resistance for low power loss automotive, commercial, and communications systems. The
and high inrush current withstand capability small package is ideal for space-constrained applications
• Integrated shield virtually eliminates capacitive coupling while also saving costs due to reduced board area. Typical
from current conductor to die, greatly suppressing output applications include motor control, load detection and
noise due to high dv/dt transients management, switched-mode power supplies, and overcurrent
• Industry-leading noise performance with greatly fault protection.
improved bandwidth through proprietary amplifier and
The device consists of a precise, low-offset, linear Hall
filter design techniques
sensor circuit with a copper conduction path located near the
• High-bandwidth 120 kHz analog output for faster
surface of the die. Applied current flowing through this copper
response times in control applications
conduction path generates a magnetic field which is sensed
• Filter pin allows user to filter the output for improved
by the integrated Hall IC and converted into a proportional
resolution at lower bandwidth
voltage. The current is sensed differentially in order to reject
• Patented integrated digital temperature compensation
common-mode fields, improving accuracy in magnetically
circuitry allows for near closed loop accuracy over
noisy environments. The inherent device accuracy is optimized
temperature in an open-loop sensor
through the close proximity of the magnetic field to the Hall
• Small footprint, low-profile SOIC8 package suitable for
transducer. A precise, proportional voltage is provided by the
space-constrained applications
low-offset, chopper-stabilized BiCMOS Hall IC, which is
• Filter pin simplifies bandwidth limiting for better
programmed for accuracy after packaging. The output of the
resolution at lower frequencies
device has a positive slope when an increasing current flows
Continued on the next page…
through the primary copper conduction path (from pins 1 and
2, to pins 3 and 4), which is the path used for current sensing.
TÜV America
Certificate Number: The internal resistance of this conductive path is 1.2 mΩ typical,
U8V 18 02 54214 041
CB 14 11 54214 031
providing low power loss.
CB Certificate Number:
US-32848-UL The terminals of the conductive path are electrically isolated
from the sensor leads (pins 5 through 8). This allows the
PACKAGE: 8-Pin SOIC (suffix LC) ACS725 current sensor IC to be used in high-side current sense
applications without the use of high-side differential amplifiers
or other costly isolation techniques.
Not to scale Continued on the next page…
1 8
IP+ VCC
+IP ACS725 The ACS725 outputs an
analog signal, VIOUT , that
2 7 changes, proportionally,
IP+ VIOUT
with the bidirectional AC
IP
CBYPASS or DC primary sensed
current, IP , within the
3 6 0.1 µF
IP– FILTER specified measurement
–IP range. The FILTER pin
CF CLOAD can be used to decrease
4 5 the bandwidth in order
GND 1 nF to optimize the noise
IP–
performance.
Typical Application
ACS725-DS, Rev. 17 May 16, 2022
MCO-0000160
ACS725 with Common-Mode Field Rejection in a Small Footprint SOIC8 Package
FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

• 3.3 V, single supply operation The ACS725 is provided in a small, low-profile surface-mount
• Output voltage proportional to AC or DC current SOIC8 package. The leadframe is plated with 100% matte tin, which
• Factory-trimmed sensitivity and quiescent output voltage for is compatible with standard lead (Pb) free printed circuit board
improved accuracy assembly processes. Internally, the flip-chip device is considered
• Chopper stabilization results in extremely stable quiescent Pb-free. However, the solder bump connections are available in a
output voltage Pb-free or high-temperature Pb-based option. Part numbers followed
• Nearly zero magnetic hysteresis by -S are manufactured with tin-silver-based solder bumps, making
• Ratiometric output from supply voltage these parts Pb-free compliant without the use of RoHS exemptions.
Part numbers followed by -T are manufactured with Pb-based solder
bumps using allowed RoHS exemptions.
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
SELECTION GUIDE
Sens(Typ)
IPR TA
Part Number at VCC = 3.3 V Packing
(A) (°C)
(mV/A)
-S VARIANT [1]
ACS725LLCTR-05AB-S ±5 264
ACS725LLCTR-10AU-S 10 264
–40 to 150 Tape and Reel, 3000 pieces per reel
ACS725LLCTR-30AB-S-H [2] ±30 44
ACS725LLCTR-50AB-S ±50 26.4
-T VARIANT [3]
ACS725LLCTR-05AB-T ±5 264
ACS725LLCTR-10AU-T 10 264
–40 to 150 Tape and Reel, 3000 pieces per reel
ACS725LLCTR-30AB-T-H [2] ±30 44
ACS725LLCTR-50AB-T ±50 26.4
[1] -S denotes the lead-free construction with tin-silver-based solder bumps.

[2] -H denotes 100% cold calibration at the Allegro factory for improved accuracy.
[3] -T denotes Pb-contained construction with Pb-based solder bumps. Operating performance of -T and -S devices are identical. -T devices are RoHS-compliant using al-
lowed exemptions provided in Annex III and IV of Directive 2011/65/EU [Exemptions 7(a), 15, 15(a), as applicable].
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SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Supply Voltage VCC 6 V
Reverse Supply Voltage VRCC –0.1 V
Output Voltage VIOUT VCC + 0.5 V
Reverse Output Voltage VRIOUT –0.1 V
Operating Ambient Temperature TA Range L –40 to 150 °C
Junction Temperature TJ(max) 165 °C
Storage Temperature Tstg –65 to 165 °C
ISOLATION CHARACTERISTICS
Characteristic Symbol Notes Rating Unit
Tested ±5 pulses at 2/minute in compliance to IEC 61000-4-5
Dielectric Surge Strength Test Voltage [1] VSURGE 6000 V
1.2 µs (rise) / 50 µs (width).
Agency type-tested for 60 seconds per UL standard 60950-
Dielectric Strength Test Voltage [1] VISO 1 (edition 2). Production tested at VISO for 1 second, in 2400 VRMS
accordance with UL 60950-1 (edition 2).
Maximum approved working voltage for basic (single) 420 Vpk or VDC
Working Voltage for Basic Isolation [1] VWVBI
isolation according UL 60950-1 (edition 2) 297 Vrms
Clearance Dcl Minimum distance through air from IP leads to signal leads 4.2 mm
Minimum distance along package body from IP leadds to
Creepage Dcr 4.2 mm
signal leads
Comparative Tracking Index CTI Material Group II 400 to 599 V
[1] Certification pending.
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Mounted on the Allegro 85-0140 evaluation board with
800 mm2 of 4 oz. copper on each side, connected to pins
Package Thermal Resistance
RθJA 1 and 2, and to pins 3 and 4, with thermal vias connecting 23 °C/W
(Junction to Ambient)
the layers. Performance values include the power
consumed by the PCB.
Package Thermal Resistance
RθJL Mounted on the Allegro ASEK725 evaluation board. 5 °C/W
(Junction to Lead)
*Additional thermal information available on the Allegro website.
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VCC
VCC
Master Current To All Subcircuits

Supply Programming
Control
POR
Hall
Current EEPROM and CBYPASS
Temperature
Drive Sensor Control Logic 0.1 µF
IP+ Offset
Control
Sensitivity
IP+ Control
Dynamic Offset
+
Cancellation
– – VIOUT
RF(int)
+
IP–
IP–
GND CF FILTER
Functional Block Diagram
Pinout Diagram and Terminal List Table
Terminal List Table

IP+ 1 8 VCC
Number Name Description
IP+ 2 7 VIOUT
1, 2 IP+ Terminals for current being sensed; fused internally
IP– 3 6 FILTER
3, 4 IP– Terminals for current being sensed; fused internally
IP– 4 5 GND
5 GND Signal ground terminal
6 FILTER Terminal for external capacitor that sets bandwidth
Package LC, 8-Pin SOICN 7 VIOUT Analog output signal
Pinout Diagram 8 VCC Device power supply terminal
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COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA , VCC = 3.3 V, CF = 0, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage VCC 3 3.3 3.6 V
Supply Current ICC VCC = 3.3 V, output open – 10 14 mA
Output Capacitance Load CL VIOUT to GND – – 10 nF
Output Resistive Load RL VIOUT to GND 4.7 – – kΩ
Primary Conductor Resistance RIP TA = 25°C – 1.2 – mΩ
Internal Filter Resistance [2] RF(int) – 1.8 – kΩ
Common Mode Field Rejection Ratio CMFRR Uniform external magnetic field – 40 – dB
Primary Hall Coupling Factor G1 TA = 25°C – 11 – G/A
Secondary Hall Coupling Factor G2 TA = 25°C – 2.8 – G/A
Hall plate Sensitivity Matching Sensmatch TA = 25°C – ±1 – %
Rise Time tr IP = IP(max), TA = 25°C, CL = 1 nF – 3 – μs
Propagation Delay tpd IP = IP(max), TA = 25°C, CL = 1 nF – 2 – μs
Response Time tRESPONSE IP = IP(max), TA = 25°C, CL = 1 nF – 4 – μs
Bandwidth BW Small signal –3 dB; CL = 1 nF – 120 – kHz
Input referenced noise density; µA(rms)/
Noise Density IND – 200 –
TA = 25°C, CL = 1 nF √Hz
Input referenced noise: CF = 4.7 nF,
Noise IN – 27 – mA(rms)
CL = 1 nF, BW = 18 kHz, TA = 25°C
Nonlinearity ELIN Through full range of IP –1.5 – +1.5 %
SENS_RAT_
Sensitivity Ratiometry Coefficient VCC = 3.0 to 3.6 V, TA = 25°C – 1.3 – –
COEF
QVO_RAT_
Zero Current Output Ratiometry Coefficient VCC = 3.0 to 3.6 V, TA = 25°C – 1 – –
COEF
VOH RL = 4.7 kΩ – VCC – 0.3 – V
Saturation Voltage [3]
VOL RL = 4.7 kΩ – 0.3 – V
Output reaches 90% of steady-state
Power-On Time tPO – 80 – μs
level, TA = 25°C, IP = IPR(max) applied
Shorted Output to Ground Current Isc(gnd) TA = 25°C – 3.3 – mA
Shorted Output to VCC Current Isc(vcc) TA = 25°C – 45 – mA
[1] Device may be operated at higher primary current levels, IP , ambient temperatures, TA , and internal leadframe temperatures, provided the Maximum Junction Tempera-
ture, TJ(max), is not exceeded.
[2] R
F(int) forms an RC circuit via the FILTER pin.
[3] The sensor IC will continue to respond to current beyond the range of I until the high or low saturation voltage; however, the nonlinearity in this region will be worse than
P
through the rest of the measurement range.
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xLLCTR-05AB PERFORMANCE CHARACTERISTICS: TA Range L, valid at TA = – 40°C to 150°C, VCC = 3.3 V, unless otherwise specified
Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit
NOMINAL PERFORMANCE
Current Sensing Range IPR –5 – 5 A
Sensitivity Sens IPR(min) < IP < IPR(max) – 264 – mV/A
VCC ×
Zero Current Output Voltage VIOUT(Q) Unidirectional; IP = 0 A – – V
0.5
ACCURACY PERFORMANCE
IP = IPR(max); TA = 25°C to 150°C –2.5 ±0.9 2.5 %
Total Output Error [2] ETOT
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
TOTAL OUTPUT ERROR COMPONENTS [3] ETOT = ESENS + 100 x VOE/(Sens x IP)
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.9 1.5 %
Sensitivity Error Esens
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –15 ±5 15 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±15 30 mV
LIFETIME DRIFT CHARACTERISTICS
Sensitivity Error Lifetime Drift Esens_drift –3 ±1 3 %
Total Output Error Lifetime
Etot_drift –3 ±1 3 %
Drift
[1] Typical values with ± are 3 sigma values

[2] Percentage of IP , with IP = IPR(max).
[3] A single part will not have both the maximum/minimum sensitivity error and maximum/minimum offset voltage, as that would violate the maximum/minimum total output
error specification. Also, 3 sigma distribution values are combined by taking the square root of the sum of the squares. See Application Information section.
NOMINAL PERFORMANCE
VCC ×
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±0.8 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.8 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±4 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±15 30 mV
Drift

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xLLCTR-10AU PERFORMANCE CHARACTERISTICS: TA Range L, valid at TA = – 40°C to 150°C, VCC = 3.3 V, unless otherwise specified
NOMINAL PERFORMANCE
Current Sensing Range IPR 0 – 10 A
VCC ×
0.1
IP = IPR(max); TA = 25°C to 150°C –2.5 ±0.9 2.5 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –2 ±0.9 2 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –15 ±5 15 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±15 30 mV
Drift

NOMINAL PERFORMANCE
VCC ×
0.1
IP = IPR(max); TA = 25°C to 150°C –2 ±0.8 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.8 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±4 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

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NOMINAL PERFORMANCE
VCC ×
Zero Current Output Voltage VIOUT(Q) Bidirectional; IP = 0 A – – V
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±0.8 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.8 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±4 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

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NOMINAL PERFORMANCE
VCC ×
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±0.7 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.7 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±3 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

xLLCTR-30AB-H PERFORMANCE CHARACTERISTICS: TA Range L, valid at TA = – 40°C to 150°C, VCC = 3.3 V, unless otherwise specified
NOMINAL PERFORMANCE
VCC ×
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±0.7 2 %
IP = IPR(max); TA = –40°C to 25°C –2 ±1.5 2 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.7 1.5 %
IP = IPR(max); TA = –40°C to 25°C –1.5 ±1 1.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±3 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –10 ±6 10 mV
Drift

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NOMINAL PERFORMANCE
VCC ×
0.1
IP = IPR(max); TA = 25°C to 150°C –2 ±0.8 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±0.8 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±4 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

NOMINAL PERFORMANCE
VCC ×
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±1 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±1 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±3 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

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NOMINAL PERFORMANCE
Sensitivity Sens IPR(min) < IP < IPR(max) – 26.4 – mV/A
VCC ×
0.5
IP = IPR(max); TA = 25°C to 150°C –2 ±1 2 %
IP = IPR(max); TA = –40°C to 25°C –6 ±4 6 %
IP = IPR(max); TA = 25°C to 150°C –1.5 ±1 1.5 %
IP = IPR(max); TA = –40°C to 25°C –5.5 ±4 5.5 %
IP = 0 A; TA = 25°C to 150°C –10 ±3 10 mV
Offset Voltage VOE
IP = 0 A; TA = –40°C to 25°C –30 ±5 30 mV
Drift

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CHARACTERISTIC PERFORMANCE
ACS725 TYPICAL FREQUENCY RESPONSE
ACS725 Frequency Response

5
Magnitude [dB]
-5
-10
10 1 10 2 10 3 10 4 10 5
Frequency [Hz]
50
0
Phase [°]
-50
-100
-150
10 1 10 2 10 3 10 4 10 5
Frequency [Hz]
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APPLICATION INFORMATION
Estimating Total Error vs. Sensed Current Here, ESENS and VOE are the ±3 sigma values for those error
terms. If there is an average sensitivity error or average offset
The Performance Characteristics tables give distribution (±3 voltage, then the average Total Error is estimated as:
sigma) values for Total Error at IPR(max); however, one often
wants to know what error to expect at a particular current. This 100 × VOEAVG
ETOTAVG (IP) = ESENSAVG +
can be estimated by using the distribution data for the compo- Sens × IP
nents of Total Error, Sensitivity Error, and Offset Voltage. The
±3 sigma value for Total Error (ETOT) as a function of the sensed The resulting total error will be a sum of ETOT and ETOT_AVG.
current (IP) is estimated as: Using these equations and the 3 sigma distributions for Sensitiv-
ity Error and Offset Voltage, the Total Error vs. sensed current
(IP) is below for the ACS725LLCTR-20AB. As expected, as one
2
ETOT (IP) = ESENS +

2
( 100 × VOE
Sens × IP ) goes towards zero current, the error in percent goes towards infin-
ity due to division by zero.
8
Total Error (% of Current Measured)
4 -40ºC + 3σ
-40ºC – 3σ
2
25ºC + 3σ
0
25ºC – 3σ
-2
85ºC + 3σ
-4 85ºC – 3σ
-6
-8
0 5 10 15 20
Current (A)
Figure 1: Predicted Total Error as a Function of the Sensed Current for the ACS725LLCTR-20AB
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Thermal Rise vs. Primary Current ASEK724/5 Evaluation Board Layout

Self-heating due to the flow-off current should be considered dur- Thermal data shown in Figure 2 was collected using the
ing the design of any current sensing system. The sensor, printed ASEK724/5 Evaluation Board (TED-85-0740-003). This board
circuit board (PCB), and contacts to the PCB will generate heat includes 1500 mm2 of 2 oz. copper (0.0694 mm) connected to
as current moves through the system. pins 1 and 2, and to pins 3 and 4, with thermal vias connecting
the layers. Top and bottom layers of the PCB are shown below in
The thermal response is highly dependent on PCB layout, copper
Figure 3.
thickness, cooling techniques, and the profile of the injected cur-
rent. The current profile includes peak current, current “on-time”,
and duty cycle. While the data presented in this section was
collected with direct current (DC), these numbers may be used
to approximate thermal response for both AC signals and current
pulses.
The plot in Figure 2 shows the measured rise in steady-state die
temperature of the ACS725 versus DC input current at an ambi-
ent temperature, TA, of 25 °C. The thermal offset curves may be
directly applied to other values of TA.
Figure 3: Top and Bottom Layers

Figure 2: Self Heating in the LA Package for ASEK724/5 Evaluation Board
Due to Current Flow
Gerber files for the ASEK724/5 evaluation board are available for
The thermal capacity of the ACS725 should be verified by the download from our website. See the technical documents section
end user in the application’s specific conditions. The maximum of the ACS725 device webpage.
junction temperature, TJ(MAX) (165°C), should not be exceeded.
Further information on this application testing is available in
the DC and Transient Current Capability application note on the
Allegro website.
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DEFINITIONS OF ACCURACY CHARACTERISTICS
Sensitivity (Sens). The change in sensor IC output in response to Accuracy Across

a 1 A change through the primary conductor. The sensitivity is the Increasing
Temperature
product of the magnetic circuit sensitivity (G / A) (1 G = 0.1 mT) VIOUT (V)
Accuracy at
and the linear IC amplifier gain (mV/G). The linear IC ampli- 25°C Only
fier gain is programmed at the factory to optimize the sensitivity
Ideal VIOUT
(mV/A) for the full-scale current of the device. Accuracy Across
Temperature
Nonlinearity (ELIN). The nonlinearity is a measure of how linear
the output of the sensor IC is over the full current measurement Accuracy at
25°C Only
range. The nonlinearity is calculated as:
VIOUT(IPR(max)) – VIOUT(Q) IPR(min) VIOUT(Q) +IP (A)
ELIN = 1– • 100(%)
2 • VIOUT(IPR(max)/2) – VIOUT(Q) –IP (A)
where VIOUT(IPR(max)) is the output of the sensor IC with the

maximum measurement current flowing through it and
Full Scale IP
VIOUT(IPR(max)/2) is the output of the sensor IC with half of the IPR(max)
maximum measurement current flowing through it.
0A
Zero Current Output Voltage (VIOUT(Q)). The output of the
sensor when the primary current is zero. For a unipolar supply Accuracy at
voltage, it nominally remains at 0.5 × VCC for a bidirectional 25°C Only
Decreasing
device and 0.1 × VCC for a unidirectional device. For example, in Accuracy Across VIOUT (V)
Temperature
the case of a bidirectional output device, VCC = 3.3 V translates
into VIOUT(Q) = 1.65 V. Variation in VIOUT(Q) can be attributed to Figure 4: Output Voltage versus Sensed Current
the resolution of the Allegro linear IC quiescent voltage trim and
thermal drift.
+ETOT
Offset Voltage (VOE). The deviation of the device output from
its ideal quiescent value of 0.5 × VCC (bidirectional) or 0.1 × VCC
(unidirectional) due to nonmagnetic causes. To convert this volt-
age to amperes, divide by the device sensitivity, Sens. Across Temperature
Total Output Error (ETOT). The difference between the cur-
rent measurement from the sensor IC and the actual current (IP), 25°C Only
relative to the actual current. This is equivalent to the difference

between the ideal output voltage and the actual output voltage,
divided by the ideal sensitivity, relative to the current flowing
through the primary conduction path: –IP +IP
VIOUT_ideal(IP) – VIOUT (IP)

ETOT (IP) = • 100 (%)
Sensideal(IP) • IP
The Total Output Error incorporates all sources of error and is a

function of IP . At relatively high currents, ETOT will be mostly
due to sensitivity error, and at relatively low currents, ETOT will
be mostly due to Offset Voltage (VOE ). In fact, at IP = 0, ETOT
approaches infinity due to the offset. This is illustrated in Figure –ETOT
4 and Figure 5. Figure 4 shows a distribution of output voltages

versus IP at 25°C and across temperature. Figure 5 shows the cor-
responding ETOT versus IP . Figure 5: Total Output Error versus Sensed Current
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Sensitivity Ratiometry Coefficient (SENS_RAT_COEF). The Zero Current Output Ratiometry Coefficient (QVO_RAT_
coefficient defining how the sensitivity scales with VCC. The COEF). The coefficient defining how the zero current output
ideal coefficient is 1, meaning the sensitivity scales proportion- voltage scales with VCC. The ideal coefficient is 1, meaning the
ally with VCC. A 10% increase in VCC results in a 10% increase output voltage scales proportionally with VCC, always being
in sensitivity. A coefficient of 1.1 means that the sensitivity equal to VCC/2. A coefficient of 1.1 means that the zero current
increases by 10% more than the ideal proportionality case. This output voltage increases by 10% more than the ideal proportion-
means that a 10% increase in VCC results in an 11% increase in ality case. This means that a 10% increase in VCC results in an
sensitivity. This relationship is described by the following equa- 11% increase in the zero current output voltage. This relationship
tion: is described by the following equation:
(VCC – 3.3 V) • SENS_RAT_COEF (VCC – 3.3 V) • QVO_RAT_COEF
Sens(VCC ) = Sens(3.3 V) 1 + VIOUTQ(VCC ) = VIOUTQ(3.3 V) 1 +
3.3 V 3.3 V
This can be rearranged to define the sensitivity ratiometry coef- This can be rearranged to define the zero current output ratiom-
ficient as: etry coefficient as:
Sens(VCC ) 3.3 V VIOUTQ(VCC ) 3.3 V
SENS_RAT_COEF = –1 • QVO_RAT_COEF = –1 •
Sens(3.3 V) (VCC – 3.3 V) VIOUTQ(3.3 V) (VCC – 3.3 V)
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DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISTICS
Power-On Time (tPO). When the supply is ramped to its operat- V

ing voltage, the device requires a finite time to power its internal VCC
components before responding to an input magnetic field. VCC(typ.)
Power-On Time, tPO , is defined as the time it takes for the output
90% VIOUT VIOUT
voltage to settle within ±10% of its steady state value under an
applied magnetic field, after the power supply has reached its
minimum specified operating voltage, VCC(min), as shown in the
chart at right.
VCC(min.)
tPO
t1 t2
t1= time at which power supply reaches

minimum specified operating voltage
t2= time at which output voltage settles

within ±10% of its steady state value
under an applied magnetic field
0
t
Figure 6: Power-On Time (tPO)
Rise Time (tr). The time interval between a) when the sensor IC
reaches 10% of its full scale value, and b) when it reaches 90% (%) Primary Current
of its full scale value. The rise time to a step response is used to
derive the bandwidth of the current sensor IC, in which ƒ(–3 dB) 90
VIOUT
= 0.35 / tr. Both tr and tRESPONSE are detrimentally affected by
eddy current losses observed in the conductive IC ground plane.
Rise Time, tr
Propagation Delay (tpd ). The propagation delay is measured
as the time interval a) when the primary current signal reaches 20
10
20% of its final value, and b) when the device reaches 20% of its 0
output corresponding to the applied current. Propagation Delay, tpd t
Figure 7: Rise Time (tr) and Propagation Delay (tpd)
Response Time (tRESPONSE). The time interval between a) when

the primary current signal reaches 90% of its final value, and b) (%) Primary Current
when the device reaches 90% of its output corresponding to the
applied current. 90
VIOUT
Response Time, tRESPONSE
0
t
Figure 8: Response Time (tRESPONSE)
18
955 Perimeter Road
PACKAGE OUTLING DRAWING
For Reference Only – Not for Tooling Use

(Reference MS-012AA)
Dimensions in millimeters – NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
8°
4.90 ±0.10 0°
8
0.25
0.17
NNNNNNN
3.90 ±0.10 6.00 ±0.20 PPT-AAA
A LLLLL
1.04 REF
1
1 2
1.27 B Standard Branding Reference View
0.40 N = Device part number
P = Package Designator
T = Device temperature range
0.25 BSC A = Amperage
L = Lot number
Belly Brand = Country of Origin
SEATING PLANE
Branded Face
GAUGE PLANE
8X C
1.75 MAX
0.10 C
SEATING
PLANE A Terminal #1 mark area
0.51 0.25 B Branding scale and appearance at supplier discretion

0.31 0.10
1.27 BSC C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances.
0.65 1.27 Package Outline 0.65 1.27

8 8
1.27 5.60 7.35 4.20 7.35
1.75 1.575
1 2 1 2
Slot in PCB to maintain
C PCB Layout Reference View 1 4.2 mm creepage once
C PCB Layout Reference View 2
part is on PCB
For PCB assemblies that cannot support a slotted design,
the above stretched footprint may be used.
Figure 9: Package LC, 8-Pin SOICN
19
955 Perimeter Road
Revision History
Number Change Pages Responsible Date
– Initial Release All A. Latham January 19, 2015
Added ACS725LLCTR-20AU-T to Selection Guide and Performance
2, 6-8,
1 Characteristics charts, and corrected Sensitivity Error; A. Latham September 28, 2015
10
added xLLCTR-20AU Characteristic Performance charts.
Added ACS725LLCTR-30AU-T to Selection Guide and Performance
2 2, 8 A. Latham December 11, 2015
Characteristics charts.
Added ACS725LLCTR-50AB-T to Selection Guide and Performance
3 2, 9 W. Bussing March 17, 2017
Characteristics charts.
4 Added AEC-Q100 qualified status 1 W. Bussing June 28, 2017
Added ACS725LLCTR-05AB-T and ACS725LLCTR-10AB-T to Selection Guide
5 2, 5 M. McNally November 15, 2017
and Performance Characteristics charts.
6 Updated Clearance and Creepage rating values 3 W. Bussing January 10, 2018
Added Dielectric Surge Strength Test Voltage characteristic 2
7 W. Bussing January 23, 2018
Added Common Mode Field Rejection Ratio characteristic 5
8 Updated PCB Layout References in Package Outline Drawing 20 W. Bussing March 19, 2018
9 Added Typical Frequency Response plots 16 W. Bussing June 22, 2018
Added “Thermal Rise vs. Primary Current” and “ASEK724/5 Evaluation Board
10 18 W. Bussing July 3, 2018
Layout” to the Applications Information section
Added ACS725LLCTR-30AB-T-H to Selection Guide and Performance
11 2, 9, 15 M. McNally July 30, 2018
Characteristic charts.
12 Updated certificate numbers 1 V. Mach December 13, 2018
13 Updated TUV certificate mark 1 M. McNally June 3, 2019
Added ACS725LLC-20AB-T-H to Selection Guide and Performance Characteristics
2, 8
14 charts W. Bussing December 20, 2019
Removed Characteristic Plots 12-17
15 Updated Functional Block Diagram 4 K. Hampton February 1, 2021
16 Updated Comparative Tracking Index to Isolation Characteristics table 3 E. Shorman July 7, 2021
Added -S lead-free part variants; removed ACS725LLCTR-20AB-T-H part variant;
17 merged Selection Guides into one table and added footnote; minor editorial 1–4, 9 K. Hampton May 16, 2022
updates
Copyright 2022, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
20
955 Perimeter Road

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ACS725

Automotive-Grade, Galvanically Isolated Current Sensor IC

FEATURES AND BENEFITS DESCRIPTION

Not to scale Continued on the next page…

FEATURES AND BENEFITS (continued) DESCRIPTION (continued)

[1] -S denotes the lead-free construction with tin-silver-based solder bumps.

ABSOLUTE MAXIMUM RATINGS

*Additional thermal information available on the Allegro website.

Master Current To All Subcircuits

Functional Block Diagram

Pinout Diagram and Terminal List Table

Terminal List Table

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

[1] Typical values with ± are 3 sigma values

ACS725 Frequency Response

ETOT (IP) = ESENS +

Thermal Rise vs. Primary Current ASEK724/5 Evaluation Board Layout

Figure 3: Top and Bottom Layers

DEFINITIONS OF ACCURACY CHARACTERISTICS

Sensitivity (Sens). The change in sensor IC output in response to Accuracy Across

where VIOUT(IPR(max)) is the output of the sensor IC with the

relative to the actual current. This is equivalent to the difference

VIOUT_ideal(IP) – VIOUT (IP)

The Total Output Error incorporates all sources of error and is a

4 and Figure 5. Figure 4 shows a distribution of output voltages

DEFINITIONS OF DYNAMIC RESPONSE CHARACTERISTICS

Power-On Time (tPO). When the supply is ramped to its operat- V

t1= time at which power supply reaches

t2= time at which output voltage settles

Figure 7: Rise Time (tr) and Propagation Delay (tpd)

Response Time (tRESPONSE). The time interval between a) when

Response Time, tRESPONSE

PACKAGE OUTLING DRAWING

For Reference Only – Not for Tooling Use

0.51 0.25 B Branding scale and appearance at supplier discretion

0.65 1.27 Package Outline 0.65 1.27

1.27 5.60 7.35 4.20 7.35

Figure 9: Package LC, 8-Pin SOICN

Copyright 2022, Allegro MicroSystems.

For the latest version of this document, visit our website:

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Response Time (tRESPONSE). The time interval between a) when