Lab Workbook Design Analysis and Floorplanning

Design Analysis and Floorplanning

2018.3

Abstract
This lab introduces how to floorplan a design using Pblocks in the Vivado® IDE.
This lab should take approximately 45 minutes.

Objectives
After completing this lab, you will be able to:
 Perform early timing analysis and analyze results
 Highlight critical timing paths
 Hierarchically highlight placement results
 Examine connectivity
 Floorplan hierarchical instances

Introduction
The design analysis features enable early detection of potential design issues, exploration of al-
ternate devices, and floorplanning.
You can target alternate devices and choose the optimal device by analyzing device utilization
statistics. By running Design Rule Checks (DRCs), you can quickly resolve constraint conflicts that
would otherwise cause implementation errors. Logic can be explored in the Netlist, Hierarchy,
and Schematic views. A quick estimation of timing performance can be performed to assess de-
sign feasibility and identify potential problem areas. You can view, modify, or create constraints
in the design. You can analyze the design hierarchical connectivity and data flow as well as iden-
tify critical logic connectivity and clock domains.
Timing and placement results can be examined by using the various analysis capabilities in the
Vivado IDE. Placement can be highlighted by module. Timing paths can be highlighted and ex-
amined. These analysis capabilities can help identify problem logic or can be used to drive floor-
planning efforts.
A small sample design consisting of a RISC processor, FFTs, gigabit transceivers and two USB
port modules is used throughout this lab. A small design is used intentionally to allow the lab to
be run with minimal hardware requirements and enable timely completion of the labs, as well as
to minimize the shipped data size. It may not be the best candidate for performance improve-
ment through floorplanning, as typically the best results are seen with larger devices.

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Lab Workbook Design Analysis and Floorplanning

This lab is intended to provide an introduction to various analysis, floorplanning and implemen-
tation features of the Vivado IDE. Do not put too much emphasis on specific aspects of this de-
sign. Focus on the processes and functionality of the Vivado IDE and how they might relate to
your specific designs.

General Flow
Step 1: Step 2: Step 3:
Step 4:
Analyzing Highlighting Exploring
Floor-
Post-Impl. Module Design Con-
planning
Results Placement nectivity

Analyzing the Post-Implementation Timing Results Step 1

Here you will open the project with the Vivado Design Suite. You will also analyze
the implemented design.

2-1. [Linux users]: Launch VirtualBox from the Start menu and start the
Ubuntu_VM virtual machine.

3-2. [Linux users]: Copy the files from the shared Windows folder to your
training directory using the following Linux command:
[host]$ source /media/sf_training/setup_TopicCluster.sh
floorplanning
If you do not recall how to perform these tasks, refer to the "Board, OS, COM,
and IP Address Tasks" section in the Lab Reference Guide.

4-3. Launch the Vivado Design Suite.

If you do not recall how to perform this task, refer to the "Launching the Vivado
Design Suite" section under Vivado Design Suite Operations in the Lab Reference
Guide.
5-4. Open the Vivado Design Suite project named project_cpu_hdl.xpr located in
the directory below.
[Windows users]: Browse to the C:\training\floorplanning\lab\KC7xx directory.
[Linux users]: Browse to the /home/xilinx/training/floorplanning/
lab/KC7xx directory.

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Lab Workbook Design Analysis and Floorplanning

If you do not recall how to perform this task, refer to the "Opening a Vivado De-
sign Suite Project" section under Vivado Design Suite Operations in the Lab Ref-
erence Guide.

6-5. Open the implemented design.

If you do not recall how to perform this task, refer to the "Opening the Imple-
mented Design" section under Vivado Design Suite Operations in the Lab Refer-
ence Guide.

You can analyze timing results from the implementation to drive the
floorplanning effort. You can also use the path sorting and selection techniques
available in the Timing Results window with the STA report data.

7-6. Explore the implementation timing results.

8-7-1. Select Reports > Timing > Report Timing.
9-8-2. Click OK to run the timing report with default settings.
The Report Timing window opens with the timing results.
10-9-3. Select path 101 under Constrained Paths > PhyClk0 in the Timing Results window.
11-10-4. Right-click the selected path and select Mark > Mark (Default Color).

Imported timing results sort the timing paths on a constraint-by-constraint basis. When
you select paths in the Timing Results view, the Path Properties view shows the details of
the timing path.
Because the placement and routing information is loaded in to memory, the path is
highlighted in the Device view. This visualization makes it easy to understand how to
take appropriate floorplanning steps to improve the timing.

12-11-5. Select the Device View if required. Disable the Show Cell Connections ( ) if needed.
After the Mark command is used, the red and green stars show the timing path start and
endpoints.
After the Mark command is run, the green mark shows the timing path start point, and
the red mark shows the timing path endpoint. The yellow mark shows the instances in
the timing path, such as LUT.
13-12-6. Press Shift and select all of the paths in PhyClk0. Do not select paths from the other
timing group.
14-13-7. Right-click and select Schematic.

The Schematic view shows all of the instances on the selected paths.

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Design Analysis and Floorplanning Lab Workbook

15-14-8. Right-click and select Select Leaf Cell Parents in the Schematic view to select the
smallest parent modules that contain all of the instances in the selected paths.
Notice that the corresponding logic modules are selected in the Netlist view.
16-15-9. Select the Device tab to switch to the Device view.

Note how the same timing-critical paths are highlighted.

17-16-10. Click the Close X to close the Schematic view.
18-17-11. Click View > Unmark All to clear the selection.
19-18-12. Click View > Unselect All to clear the selection.
20-19-13. Keep the Timing window open.

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Lab Workbook Design Analysis and Floorplanning

Highlighting Module-Level Placement Step 21

You can determine a floorplanning strategy by examining previous
implementation results. You can also analyze module placement and guide
Pblock locations by understanding how the logic was implemented without
floorplanning.

22-20. Highlight the modules with cycling colors to easily view placement.
23-21-14. Select both usbEngine0 and usbEngine1 in the Netlist view by using the Shift or
Ctrl key.
24-22-15. Right-click and select Highlight Leaf Cells > Cycle Colors.
25-23-16. Select the Device tab to view the highlighting.
The primitives in each module are highlighted in a different color.

Figure 5-1: Highlighting Module Placement

Notice the wide dispersal of the primitives. Scroll around and change the zoom level.
Notice that many of the instances are block RAMs. These might benefit from floorplan-
ning to improve timing.
26-24. Simplify the device view.
27-25-17. Click the Settings icon in the top-right corner of the Device window.
28-26-18. Uncheck the box next to Cells in the Layers tab.

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Design Analysis and Floorplanning Lab Workbook

Various elements of the netlist or elements of the device can be hidden to make the De-
vice window easier to interpret.

29-27-19. Click the Settings icon in the Device window again, if required.
30-28-20. Check the box next to Cells to get the placement back.
31-29-21. Click View > Unselect All, or press <F12>.

Exploring Design Connectivity Step 32

The Vivado IDE has extensive logic expansion, selection, and highlighting
capabilities. These capabilities can be used to validate modules that are suitable
to floorplan. For example, logic modules that connect to logic throughout the
device may not be suitable for floorplanning, while tightly grouped and self-
contained modules are suitable.
You can alleviate routing congestion and timing inconsistency by floorplanning
logic outside of the critical logic areas, thus preventing logic from migrating into
the critical areas.

33-30. Visualize the I/O connectivity.

34-31-22. Click the Routing Resources icon to hide the routing resources in the Device
window.

35-32-23. Click the Settings icon in the top-right corner of the Device window.
36-33-24. Click the General Tab.
37-34-25. Click and enable the Show I/O Nets if it is not already selected.
Green lines show the connectivity from the placed logic to the I/O pins.

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Lab Workbook Design Analysis and Floorplanning

Note: If the Routing Resources icon is enabled, you will not be able to see the Show
I/O Nets icon.

Figure 5-2: Device View with I/O Connectivity

Notice that the I/O lines on the bottom left of the chip cross to the right side of the chip.
38-35-26. Inspect the Netlist view.
39-36-27. Click Collapse All in the Netlist view.
40-37-28. Press the Shift key and select usbEngine0 and usbEngine1.
41-38-29. Right-click and select Show Connectivity.

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Design Analysis and Floorplanning Lab Workbook

Notice that the interface nets that connect usbEngine0 and usbEngine1 to the rest of the
design are highlighted. The I/O nets are shown in green.

Figure 5-3: Using the Show Connectivity Command

42-39-30. Right-click in the Device window and select Show Connectivity again to select
all of the logic objects that these nets connect to.
43-40-31. Right-click In the Device window and select Show Connectivity once again to
highlight all of the nets that fanout from those selected logic objects.
You can use the Show Connectivity command to highlight or select a cone of logic from
any source net or logic object.
44-41-32. Click View > Unselect All, or press <F12>.

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Lab Workbook Design Analysis and Floorplanning

Floorplanning Timing-Critical Hierarchy Step 45

Floorplanning a timing-critical hierarchy can improve timing performance. The
usbEngine1 and usbEngine0 could go in the corners on the left-hand side. Many
Pblocks were created to view the connectivity. Running all the Pblocks through
implementation will hurt timing. Instead, floorplan just the timing-critical
hierarchies.

46-42. Place a Pblock for usbEngine0 to enable timing-critical hierarchy.

47-43-33. Select the Device tab.
48-44-34. Ensure that the I/O nets in the Device window are being shown by clicking the
Settings on the top-right corner and check the Show I/O Nets option.
Note: You may need to disable the Routing Resources icon.
49-45-35. Click the Collapse All icon in the Netlist window and select usbEngine0.

50-46-36. Click Draw Pblock in the Device view window.

The cursor turns to a cross in the device window.
51-47-37. Draw a rectangle in the Device window starting from the bottom left corner to
the center.
52-48-38. Uncheck the DSP48 and RAMB18 grids in the New Pblock dialog box.
53-49-39. Click OK.

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Design Analysis and Floorplanning Lab Workbook

54-50-40. Click No in the Assign Cells to Pblock dialog box to disallow the clearance of the
location constraints that fall outside of the Pblock.

Figure 5-4: Floorplanning usbEngine0 Instance

55-51. Create a Pblock for usbEngine1 in the top left.

56-52-41. Select usbEngine1 and create a similar Pblock in the top left by following the
previous instructions.
Do not overlap the Pblocks.
57-53-42. Click No in the Assign Cells to Pblock dialog box to disallow the clearance of the
location constraints that fall outside of the Pblock.

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Lab Workbook Design Analysis and Floorplanning

The end result should look like the following figure.

Figure 5-5: Timing-Critical Blocks

58-54. Save the floorplan constraints to a new constraints set.

59-55-43. Select File > Constraints > Save to save the constraints, and click OK in the Out
of Date Design dialog box.
60-56-44. Click OK in the dialog box to save the constraints to the top_full.xdc file.
61-57-45. Expand the constrs_2 constraint set in the Sources window, double-click the
top_full.xdc file, and review the newly added Pblock constraints.

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Design Analysis and Floorplanning Lab Workbook

62-58. Set the implementation strategy to Flow_RuntimeOptimized.

With the floorplanning of the usbEngine blocks completed, you are now
ready to rerun the implementation.
63-59-46. Click Settings under the Flow Navigator and go to Implementation.
64-60-47. Select Flow_RuntimeOptimized from the Strategy drop-down list.
65-61-48. Click OK.

66-62. Run implementation and examine the timing report.

67-63-49. Select Run Implementation in the Flow Navigator under Implementation.
68-64-50. Click OK to run synthesis.
It may take 5-10 minutes to complete the implementation run. The Implementation
Completed dialog box displays when the run is finished.
69-65-51. Select Open Implemented Design and click OK.
70-66-52. Select the Device view if required.
71-67-53. Select usbEngine0 and usbEngine1 in the Netlist window.
72-68-54. Right-click and select Highlight Leaf Cells > Cycle Colors.
Review the highlighted leaf cells in the Pblock.
73-69-55. Review the Timing Summary report at the bottom.
Note that the timing has improved with floorplanning.
74-70. Run the Report design Analysis and review the report.
The Report design Analysis provides timing data on critical path characteris-
tics and the complexity of the design to help you identify and analyze prob-
lem areas that are subject to timing closure issues and routing congestion.
75-71-56. Select Reports > Report Design Analysis.
The Report Design Analysis window opens with the default options.

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Lab Workbook Design Analysis and Floorplanning

76-72-57. Select Complexity in the Report Design Analysis dialog box.

Figure 5-6: Report Design Analysis Dialog Box

The report_design_analysis command currently has two modes of operation: tim-

ing and complexity. Selecting both the Timing (default mode) and Complexity options
runs the command in both modes.
77-73-58. View the Tcl command to run the report_design_analysis command from
the Command section in the dialog box.
78-74-59. Click OK.
79-75-60. Select Setup Path Characteristics in the Design Analysis report and review the
results.
In Timing mode, the command returns critical path data and report characteristics of
each path. Setup checks are reported since max delay type is selected.
80-76-61. Select Complexity Characteristics in the Design Analysis report.
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Design Analysis and Floorplanning Lab Workbook

In Complexity mode, the command performs complex analysis of the current design and
reports the rent exponent, which is a measure of complexity (a higher rent indicates
higher complexity), the average fanout, and the total primitives used in the design.

81-77. Close the implemented design.

82-78. Close the project.

83-79. Close the Vivado Design Suite.

Summary
Here you used the Vivado IDE to explore and analyze the implemented design and then floor-
planned the timing critical hierarchy.
After running the design through the synthesis and implementation tools, you:
 Viewed implementation results and examined timing results.
 Analyzed critical path objects in the schematic and selected the parent modules of those
path objects.
 Highlighted module placement and displayed the connectivity of the modules using the
Show Connectivity command.
 Analyzed placement and routing of critical timing paths.

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Lab Workbook Design Analysis and Floorplanning

Answers
Since there were no questions in this lab, this section is intentionally left blank.

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