ELEC 204 Digital Design – Midterm Exam 2 – 14.05.

2022
Dr. Ertuğrul Başar
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NAME & SURNAME:
NUMBER:
DEPARTMENT:
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All books and notes are closed. Exam duration: 120 minutes
Points: 1) 25 (7+5+6+7) 2) 25 (10+5+5+5) 3) 25 (12+8+5) 4) 25 (15+5+5)
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Question 1 (Combinational Logic Circuits): Please solve the following four parts independently.
(1.a) For the following combinational circuit composed of four full adders (FA), where 𝐴 𝑖 and 𝐵𝑖 stand for the adder inputs
while 𝐶𝑖 and 𝑆𝑖 stand for the carry and sum outputs, respectively, for the 𝑖th adder in the circuit. i) Explain the operation of
this circuit when 𝑀 is HIGH and LOW. ii) Determine (𝑆3 , 𝑆2 , 𝑆1 , 𝑆0 ) and (𝐶4 , 𝐶3 , 𝐶2 , 𝐶1 ) when 𝑀 = 0, 𝐀 = (0110) and 𝐁 =
(1011). iii) Repeat part ii) for 𝑀 = 1, 𝐀 = (1100) and 𝐁 = (0110).

2  i) If M=1, the circuit performs subtraction. (Bi⊕1 = Bi 1' + Bi'1 = Bi') Output = Ai + Bi' + 1
If M=0, the circuit performs addition. (B i⊕0 = Bi 0' + Bi'0 = Bi) Output = Ai + Bi
2.5  ii) 2.5  iii)
M=0 M=1
A3A2A1A0 0 1 1 0 A3A2A1A0 1 1 0 0
B3B2B1B0 1 0 1 1 B3'B2'B1'B0' 1 0 0 1
S3S2S1S0 0 0 0 1 S3S2S1S0 0 1 1 0
C4C3C2C1 1 1 1 0 C4C3C2C1 1 0 0 1
(1.b) For the 4-bit comparator given below, plot three output waveforms that are active HIGH, for the inputs shown.

A>B

A=B 5 

A<B

(1.c) Implement the function 𝐹 defined by the following truth table using an 8-to-1 line multiplexer (you can use the MUX as
a box).

𝐴 𝐵 𝐶 𝐷 𝐹
0 0 0 0 1
1
F=1
0 0 0 1 1
0 0 1 0 0
0
F=0
0 0 1 1 0
0 1 0 0 1 3 
D'
F=D'
0 1 0 1 0
0 1 1 0 1 D'
F=D'
0 1 1 1 0
1 0 0 0 0
0
F=0
1 0 0 1 0
1 0 1 0 1
1
F=1
1 0 1 1 1
1 1 0 0 0 D
1 1 0 1 1 F=D
1 1 1 0 0
D
F=D
1 1 1 1 1

1  2 
(1.d) Design (and draw the logic diagram of) a combinational circuit with three inputs, 𝑥, 𝑦, and 𝑧, and three outputs, 𝐴, 𝐵,
and 𝐶. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6,
or 7, the binary output is two less than the input.

x y z A B C
0 0 0 0 0 1 A = Σ (3,6,7)
0 0 1 0 1 0 0.5 
B = Σ (1,2,4,5)
0 1 0 0 1 1
0 1 1 1 0 0 C = Σ (0,2,5,7)
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1 A B C

0.5 

or
1  1  1 
(X ⊕ Z) '

3 
Question 2 (Combinational Logic Circuits): In this question, Select Bits Input Bits Outputs
you will design a digital circuit that calculates the output 𝐷 with (𝑆1 𝑆0 ) = (00) (𝐴1 𝐴0 ), (𝐵1 𝐵0 ) 𝐷0 = 𝐴0 or 𝐵0
the select bits 𝑆1 𝑆0 and the input bits 𝐀 = (𝐴1 𝐴0 ) and 𝐁 = 𝐷1 = 𝐴1 or 𝐵1
(𝐵1 𝐵0 ) . The circuit operates according to the below table. (𝑆1 𝑆0 ) = (01) (𝐴1 𝐴0 ), (𝐵1 𝐵0 ) 𝐷0 = 𝐴0 and 𝐵0
𝐷1 = 𝐴1 and 𝐵1
(2.a) Obtain optimized Boolean expressions for the circuit that (𝑆1 𝑆0 ) = (10) (𝐴1 𝐴0 ), (𝐵1 𝐵0 ) 𝐷0 = 𝐴0 xor 𝐵0
implements this table. 𝐷1 = 𝐴1 xor 𝐵1
(𝑆1 𝑆0 ) = (11) (𝐴1 𝐴0 ), (𝐵1 𝐵0 ) 𝐷0 = 𝐴0 xnor 𝐵0
𝐷1 = 𝐴1 xnor 𝐵1
 

 
3 
                                       𝐷0 = ∑(1,2,3,7,9,10,12,15)   1 
S1 S0 A0 B0 D0  
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1 3 
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
            
 

𝐷0 = 𝑆0′ 𝐴′0 𝐵0 + 𝑆1′ 𝑆0′ 𝐴0 + 𝑆0′ 𝐴0 𝐵0′ + 𝑆0 𝐴0 𝐵0 + 𝑆1 𝑆0 𝐴′0 𝐵0 ′  2 

Alternatively, you can obtain 𝑆1′ 𝐴0 𝐵0 or 𝑆1′ 𝑆0′ 𝐵0 instead of 𝑆1′ 𝑆0′ 𝐴0 from K-map.

𝐷0 = 𝑆0′ 𝐴′0 𝐵0 + 𝑆1′ 𝐴0 𝐵0 + 𝑆0′ 𝐴0 𝐵0′ + 𝑆0 𝐴0 𝐵0 + 𝑆1 𝑆0 𝐴′0 𝐵0 ′ 

𝐷0 = 𝑆0′ 𝐴′0 𝐵0 + 𝑆1′ 𝑆0′ 𝐵0 + 𝑆0′ 𝐴0 𝐵0′ + 𝑆0 𝐴0 𝐵0 + 𝑆1 𝑆0 𝐴′0 𝐵0 ′ 
 

Since 𝐷1 is the same operation with inputs 𝐴1 and 𝐵1 , we can obtain the simplified Boolean expressing for 𝐷1 by replacing
𝐴0 , 𝐵0 → 𝐴1 , 𝐵1
𝐷1 = 𝑆0′ 𝐴1′ 𝐵1 + 𝑆1′ 𝑆0′ 𝐴1 + 𝑆0′ 𝐴1 𝐵1′ + 𝑆0 𝐴1 𝐵1 + 𝑆1 𝑆0 𝐴1′ 𝐵1 ′  1 
or 

𝐷0 = 𝑆0′ 𝐴1′ 𝐵1 + 𝑆1′ 𝐴1 𝐵1 + 𝑆0′ 𝐴1 𝐵1′ + 𝑆0 𝐴1 𝐵1 + 𝑆1 𝑆0 𝐴1′ 𝐵1 ′ 

𝐷0 = 𝑆0′ 𝐴1′ 𝐵1 + 𝑆1′ 𝑆0′ 𝐵1 + 𝑆0′ 𝐴1 𝐵1′ + 𝑆0 𝐴1 𝐵1 + 𝑆1 𝑆0 𝐴1′ 𝐵1 ′ 
 
(2.b) Present a circuit diagram (using AND and OR gates and inverters only) that implements this circuit in the optimized
way. (For simplicity, you can only draw the circuit that provides 𝐷0)
You can only draw the circuit for 𝑫 𝟎  

1 

1 

1 

1 

1 
 
(2.c) Implement the same circuit using 4-to-1line multiplexers (for this specific implementation, you can use the MUX as a
box and also direcly use XOR and XNOR gates).

2 𝑆1   𝑆0   𝐷0  𝐷1 

0  0  𝐴0 + 𝐵0   𝐴1 + 𝐵1  

0  1  𝐴0 . 𝐵0   𝐴1 . 𝐵1  

common   1  0  𝐴0 ⨁𝐵0   𝐴1 ⨁𝐵1 

selection  
bits  1  1  𝐴0 ⊕ 𝐵0   𝐴1 ⊕ 𝐵1  
1
2

 
(2.d) Assess the complexities of the circuits you obtained in (2.b) and (2.c) (in terms of the total number of gates used).
The first implementation requires total of 2x(5+1)=12 gates to obtain 𝐷0 and 𝐷1. 2

The second implementation requires 8 gates and 2 4x1 Multiplexers. 1

A single 4x1 MUX requires 5 gates as seen in figure below ➔ So the second implementation requires 8+2x5=18 gates to
obtain 𝐷0 and 𝐷1.    2
 

Figure 1 : A 4x1 MUX Layout

Note: Alternative Form for 2a

Alternative Boolean Expression
𝐷0 = 𝑆1′ 𝑆0′ (𝐴0 + 𝐵0 ) + 𝑆1′ 𝑆0 (𝐴0 . 𝐵0 ) + 𝑆1 𝑆0′ (𝐴0 ⨁𝐵0 ) + 𝑆1 𝑆0 (𝐴0 ⨁𝐵0 )′
= 𝑆1′ 𝑆0′ 𝐴0 + 𝑆1′ 𝑆0′ 𝐵0 + 𝑆1′ 𝑆0 𝐴0 𝐵0 + 𝑆1 𝑆0 ′𝐴0 𝐵0′ + 𝑆1 𝑆0 ′𝐴0 ′𝐵0 + 𝑆1 𝑆0 𝐴0 𝐵0 + 𝑆1 𝑆0 𝐴0 ′𝐵0 ′
This expression is not simplified, so you can only get partial credits if you leave it like that.
Midterm 2 - Q3
10 Mayıs 2022 Salı 15:19

Digital Design Sayfa 1

Digital Design Sayfa 2
Question 4 (Sequential Logic Design): A sequential circuit has three flip-flops A, B, C;
one input 𝑥; and one output 𝑦. The state diagram of this circuit is shown below. The
circuit is to be designed by treating the unused states as don’t-care conditions and
considering D flip-flops. Note: 𝑄(𝑡 + 1) = 𝐷
(4.a) Obtain the state transitions table and simplified flip-flop input equations.

𝟕 

Present State Next State

𝑨 B C 𝑥 𝑨 (t+1) B (t+1) C (t+1) 𝒚
0 0 0 0 0 1 1 0
0 0 0 1 1 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 1 0 0 1
        
0 1 0 0 0 1 0 0
0 1 0 1 0 0 0 1  
0 1 1 0 0 0 1 0
 
0 1 1 1 0 1 0 1
1 0 0 0 0 1 0 0  
1 0 0 1 0 1 1 1
 
1 0 1 0 x x x x
1 0 1 1 x x x x  
1 1 0 0 x x x x  
1 1 0 1 x x x x
1 1 1 0 x x x x  
1 1 1 1 x x x x  

  𝐷𝐴   𝐷𝐵   𝐷𝐶  
  

𝐴 (𝑡 + 1) = 𝐷𝐴 (𝐴, 𝐵, 𝐶, 𝑥) = ∑(1,3) 

𝐵 (𝑡 + 1) = 𝐷𝐵 (𝐴, 𝐵, 𝐶, 𝑥) = ∑(0,4,7,8,9) 
𝑑(𝐴, 𝐵, 𝐶, 𝑥) = ∑(10,19,12,13,14,15) 
𝐶 (𝑡 + 1) = 𝐷𝐶 (𝐴, 𝐵, 𝐶, 𝑥) = ∑(0,2,6,9) 
 
𝑦 = ∑(1,3, 5,7) 
 

𝟐  𝟐 

                                                      
𝐷𝐴 = 𝐴′ 𝐵′ 𝑥                                                                        𝐷𝐵 = 𝐴 + 𝐶 ′ 𝑥 ′ + 𝐵𝐶𝑥 
 

𝟐  𝟐 

        
                                         𝐷𝐶 = 𝐴𝑥 + 𝐶𝑥 ′ + 𝐴′𝐵′𝑥′                                                                 𝑦 = 𝐴′𝑥 
 
(4.b) Draw the logic diagram of the circuit.
𝟓 
(4.c) Determine the effect of the unused states by considering that the circuit is at an unused state (consider this for all unused
states).
3 unused states => 101, 110, 111 using 𝐷𝐴 , 𝐷𝐵 , 𝐷𝐶 and y expressions above we obtain

𝟓