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ELECTRONIC ENGINEERING 3
BHM 2333
ASSIGNMENT 01 : COMBINATION LOGIC
DESIGN
NAME : MUHAMMAD SYUKRI BIN MOHD HAFIDZ
ID : HA22003 SESSION : YEAR 2 SEM II LECTURER : EN. ZULKIFLI MD. YUSOF DUE DATE : 1 MAY 2024 TABLE OF CONTENT
i. INTRODUCTION ii. CONTEXT
1.0 IDENTIFICATION NUMBER
- TRUTH TABLE
2.0 KARNAUGH MAP & BOOLEAN EXPRESSION
2.1 CIRCUIT CONFIGURATION o W OUTPUT (AND-OR) o X OUTPUT (AND-OR & NAND-NAND) o Y OUTPUT (AND-OR & OR-AND) o Z OUTPUT (AND-OR & NOR-NOR)
3.0 COMBINATION LOGIC CIRCUIT
- 4 VARIABLE OUTPUT (W-X-Y-Z) CIRCUIT
4.0 INTRODUCTION Combination Logic Circuit Design are memoryless digital logic circuits whose output at any instant in time depends only on the combination of its input. As in this report, by using identification number as reference, designing a Combination Logic Circuits is possible. To design this Combination Logic Circuit, 4 variables of input, A, B, C, and D is acquired from individual identification number, thus the result is that we can obtained 4 variables of output, W, X, Y, and Z.
CONTEXT This Combinational Logic Circuits are made up from basic logic AND, OR, NAND, NOR and NOT gates that are “combined” or connected to produce more complicated switching circuits. These logic gates are the building blocks of combinational logic circuits.
An example of a combinational circuit is a decoder, which converts the binary code data present at its input into several different output lines, one at a time producing an equivalent decimal code at its output.
There are three main ways of specifying the function of a combinational logic circuit:
Boolean Algebra – This forms the algebraic expression showing the operation of the logic circuit for each input variable either True or False that results in a logic “1” output. Truth Table – A truth table defines the function of a logic gate by providing a concise list that shows all the output states in tabular form for each possible combination of input variable that the gate could encounter. Logic Diagram – This is a graphical representation of a logic circuit that shows the wiring and connections of each individual logic gate, represented by a specific graphical symbol, that implements the logic circuit. 1.0 IDENTIFICATION NUMBER 0 3 0 1 1 2 0 4 0 2 8 3 0 3 A 1 B 2 C 4 D E 8 F
TRUTH TABLE DEC W X Y Z A B C D . 0 0 0 0 0 = 0 0 1 1 1 0 0 0 1 = 1 0 1 1 2 0 0 1 0 = 1 1 0 0 3 0 0 1 1 = 1 0 1 0 4 0 1 0 0 = 1 1 0 1 5 0 1 0 1 = x x x X 6 0 1 1 0 = x x x x 7 0 1 1 1 = x x x x 8 1 0 0 0 = 1 1 1 1 9 1 0 0 1 = x x x x A 1 0 1 0 = 0 0 0 1 B 1 0 1 1 = 0 0 1 0 C 1 1 0 0 = 0 1 0 0 D 1 1 0 1 = 1 1 1 0 E 1 1 1 0 = 1 0 0 0 F 1 1 1 1 = 0 0 0 0
KARNAUGH-REFERENCE POSITION C̄ C̄ C C D̄ D D D̄ Ā 0 1 3 2 B̄ Ā 4 5 7 6 B A 12 13 15 14 B A 8 9 11 10 B̄ 2.0 KARNAUGH-MAP (K-MAP) & BOOLEAN EXPRESSION
W OUTPUT Y OUTPUT CD CD 00 01 11 10 00 01 11 10 AB AB 00 0(0) 1(1) 1(3) 1(2) 00 1(0) 1(1) 1(3) 0(2) 01 1(4) x(5) x(7) x(6) 01 0(4) x(5) x(7) x(6) 11 0(12) 1(13) 0(15) 1(14) 11 0(12) 1(13) 0(15) 0(14) 10 1(8) x(9) 0(11) 0(10) 10 1(8) x(9) 1(11) 0(10)
