Datasheet

®
RT7237A
2A, 18V, 340kHz Synchronous Step-Down Converter

General Description Features
The RT7237A is a high efficiency, monolithic synchronous z ±1.5% High Accuracy Reference Voltage
step-down DC/DC converter that can deliver up to 2A z 4.5V to 18V Input Voltage Range
output current from a 4.5V to 18V input supply. The z 2A Output Current
RT7237A's current mode architecture and external z Integrated N-MOSFET Switches
compensation allow the transient response to be z Current Mode Control
optimized over a wide input range and loads. Cycle-by- z Fixed Frequency Operation : 340kHz
cycle current limit provides protection against shorted z Output Adjustable from 0.8V to 15V
outputs, and soft-start eliminates input current surge during z Stable with Low ESR Ceramic Output Capacitors
start-up. The RT7237A also provides under voltage z Up to 95% Efficiency
protection and thermal shutdown protection. The low z Adjustable Soft-Start
current (<3μA) shutdown mode provides output z Cycle-by-Cycle Current Limit
disconnection, enabling easy power management in z Input Under Voltage Lockout
battery-powered systems. The RT7237A is available in z Output Under Voltage Protection
an SOP-8 (Exposed Pad) package. z Thermal Shutdown Protection
z RoHS Compliant and Halogen Free
Applications
z Wireless AP/Router
z Set-Top-Box
z Industrial and Commercial Low Power Systems
z LCD Monitors and TVs
z Green Electronics/Appliances
z Point of Load Regulation of High-Performance DSPs
Simplified Application Circuit
VIN VIN BOOT

CIN RT7237A CBOOT
L
SW VOUT
Chip Enable
EN R1
SS FB COUT
CSS CC RC R2
GND COMP
CP
Copyright © 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS7237A-01 September 2012 www.richtek.com

1
RT7237A
Ordering Information Marking Information
RT7237A RT7237AxGSP : Product Number
Package Type RT7237Ax x : H or L or N
SP : SOP-8 (Exposed Pad-Option 2) GSPYMDNN
YMDNN : Date Code
Lead Plating System
G : Green (Halogen Free and Pb Free)
H : UVP Hiccup Pin Configurations
L : UVP Latch-Off
N : UVP Disabled (TOP VIEW)
Note : 8
BOOT SS
Richtek products are : VIN 2 7 EN
GND
SW 3 6 COMP
` RoHS compliant and compatible with the current require- 9
GND 4 5 FB
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes. SOP-8 (Exposed Pad)
Functional Pin Description

Pin No. Pin Name Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1μF or greater ceramic
1 BOOT
capacitor from BOOT to SW pin.
Supply Voltage Input, 4.5V to 18V. Must bypass with a suitable large ceramic
2 VIN
capacitor.
3 SW Switch Node. Connect this pin to an external L-C filter.
4, Ground. The exposed pad must be soldered to a large PCB and connected to
GND
9 (Exposed Pad) GND for maximum power dissipation.
Feedback Input. It is used to regulate the output of the converter to a set value
5 FB
via an external resistive voltage divider.
Compensation Node. COMP is used to compensate the regulation control
6 COMP loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
Enable Input. A logic high enables the converter; a logic low forces the IC into
7 EN
shutdown mode reducing the supply current to less than 3μA.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
8 SS from SS to GND to set the soft-start period. A 0.1μF capacitor sets the
soft-start period to 13.5ms.
www.richtek.com DS7237A-01 September 2012

2
RT7237A
Function Block Diagram
VIN
Internal
Regulator Oscillator
Current Sense
Shutdown V V Slope Comp Amplifier
A CC
Comparator Foldback + VA
RSENSE
1.2V + Control -
-
0.4V + BOOT
Lockout -
Comparator UV S Q 150mΩ
5kΩ Comparator SW
EN - +
R Q 130mΩ
1.8V + -
Current GND
Comparator
VCC
6µA
0.8V +
SS +EA
-
FB COMP

3
RT7237A
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- −0.3V to 20V
z Switch Voltage, SW ------------------------------------------------------------------------------------------------ −0.3V to (VIN + 0.3V)
z VBOOT − VSW ---------------------------------------------------------------------------------------------------------- −0.3V to 6V
z Other Pins Voltage ------------------------------------------------------------------------------------------------- −0.3V to 20V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W
z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C
z Junction Temperature ----------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 4.5V to 18V
z Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Shutdown Supply Current VEN = 0V -- 0.5 3 μA
Quiescent Supply Current VEN = 3V, VFB = 0.9V -- 0.8 1.2 mA
Reference Voltage VREF 4.5V ≤ VIN ≤ 18V 0.788 0.8 0.812 V
Error Amplifier
GEA ΔIC = ±10μA -- 940 -- μA/V
Transconductance
High Side Switch
RDS(ON)1 -- 150 -- mΩ
On-Resistance
Low Side Switch
RDS(ON)2 -- 130 -- mΩ
On-Resistance
High Side Switch Leakage
VEN = 0V, VSW = 0V -- 0 10 μA
Current
High Side Switch Current
Min. Duty Cycle, VBOOT − VSW = 4.8V -- 4 -- A
Limit
COMP to Current Sense
GCS -- 3.7 -- A/V
Transconductance
Oscillator Frequency fOSC1 300 340 380 kHz
Short Circuit Oscillation
fOSC2 VFB = 0V -- 100 -- kHz
Frequency
Maximum Duty Cycle DMAX VFB = 0.7V -- 93 -- %
Minimum On-Time tON -- 100 -- ns

4
RT7237A
Parameter Symbol Test Conditions Min Typ Max Unit
EN Input Threshold Logic-High VIH 2 -- 18
V
Voltage Logic-Low VIL -- -- 0.4
Input Under Voltage Lockout
VUVLO VIN Rising 3.8 4.2 4.5 V
Threshold
Input Under Voltage Lockout
ΔVUVLO -- 320 -- mV
Hysteresis
Soft-Start Current ISS VSS = 0V -- 6 -- μA
Soft-Start Period tSS CSS = 0.1μF -- 13.5 -- ms
Thermal Shutdown TSD -- 150 -- °C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

5
RT7237A
Typical Application Circuit
VIN 2 1
VIN BOOT
4.5V to 18V CIN CBOOT L
10µF x 2 RT7237A 0.1µF 10µH
VOUT
SW 3
Chip Enable 3.3V
7 EN R1
75k
8 SS COUT
FB 5 22µF x 2
CSS CC RC
3.3nF R2
0.1µF 4, 9 (Exposed Pad) 6 13k 24k
GND COMP
CP
Open
Table 1. Suggested Components Selection

V OUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF) L (μH) COUT (μF)
8 27 3 27 3.3 22 22 x 2
5 62 11.8 20 3.3 15 22 x 2
3.3 75 24 13 3.3 10 22 x 2
2.5 25.5 12 9.1 3.3 6.8 22 x 2
1.5 10.5 12 4.7 3.3 3.6 22 x 2
1.2 12 24 3.6 3.3 3.6 22 x 2
1 3 12 3 3.3 3.6 22 x 2

6
RT7237A
Typical Operating Characteristics
Efficiency vs. Output Current Output Voltage vs. Input Voltage
100 3.320
90
3.315
80 VIN = 4.5V
Output Voltage (V)

VIN = 12V 3.310
70 VIN = 17V
Efficiency (%)
60 3.305
50 3.300
40
3.295
30
3.290
20
10 3.285
VOUT = 3.3V VOUT = 3.3V, IOUT = 1A
0 3.280
0.01 0.1 1 10 4 6 8 10 12 14 16 18
Output Current (A) Input Voltage (V)
Reference Voltage vs. Temperature Output Voltage vs. Output Current

0.85 3.38
0.84 3.36
0.83
Reference Voltage (V)
3.34
Output Voltage (V)
VIN = 4.5V
0.82 VIN = 4.5V
VIN = 12V
0.81 VIN = 17V 3.32 VIN = 12V
VIN = 17V
0.80 3.30
0.79 3.28
0.78
3.26
0.77
3.24
0.76
VOUT = 3.3V, IOUT = 1A RT7237AH, VOUT = 3.3V
0.75 3.22
-50 -25 0 25 50 75 100 125 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Temperature (°C) Output Current (A)
Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature

380 380
370 370
Switching Frequency (kHz)1
Switching Frequency (kHz)1
360 360
VIN = 4.5V
350 350 VIN = 12V
VIN = 17V
340 340
330 330
320 320
310 310
IOUT = 0.5A IOUT = 0.5A
300 300
4 6 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

7
RT7237A
Current Limit vs. Temperature Load Transient Response

6
5
VOUT
(200mV/Div)
Current Limit (A)
VIN = 12V
3 VIN = 17V
1 IOUT
(1A/Div)
High Side Switch, VOUT = 3.3V VIN = 12V, VOUT = 3.3V, IOUT = 0.5A to 2A
0
-50 -25 0 25 50 75 100 125 Time (100μs/Div)
Temperature (°C)
Load Transient Response Output Ripple Voltage
VOUT
(5mV/Div)
VOUT
(200mV/Div)
VSW
(5V/Div)
IOUT IL
(1A/Div) (1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (100μs/Div) Time (2.5μs/Div)
Power On from VIN Power Off from VIN
VIN VIN
(5V/Div) (5V/Div)
VOUT VOUT
(2V/Div) (2V/Div)
IL IL
(2A/Div) (2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div) Time (10ms/Div)

8
RT7237A
Power On from EN Power Off from EN
VIN VIN
(5V/Div) (5V/Div)
VOUT VOUT
(2V/Div) (2V/Div)
IL IL
(1A/Div) (1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div) Time (10ms/Div)

9
RT7237A
Application Information
Output Voltage Setting Soft-Start
The resistive divider allows the FB pin to sense the output The RT7237A provides soft-start function. The soft-start
voltage as shown in Figure 1. function is used to prevent large inrush current while
VOUT converter is being powered-up. The soft-start timing can
be programmed by the external capacitor between SS and
R1 GND. An internal current source ISS (6μA) charges an
FB external capacitor to build a soft-start ramp voltage. The
RT7237A R2 VFB voltage will track the internal ramp voltage during soft-
GND start interval. The typical soft start time is calculated as
follows :
0.8 × CSS
Figure 1. Output Voltage Setting Soft-Start time tSS = , if CSS capacitor
ISS
0.8 × 0.1μ
The output voltage is set by an external resistive voltage is 0.1μF, then soft-start time = ≒ 13.5ms
6μ
divider according to the following equation :
VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ Chip Enable Operation
⎝ R2 ⎠
The EN pin is the chip enable input. Pulling the EN pin
Where VREF is the reference voltage (0.8V typ.).
low (<0.4V) will shut down the device. During shutdown
mode, the RT7237A quiescent current drops to lower than
External Bootstrap Diode 3μA. Driving the EN pin high (>2V, <18V) will turn on the
Connect a 0.1μF low ESR ceramic capacitor between the device again. For external timing control, the EN pin can
BOOT pin and SW pin. This capacitor provides the gate also be externally pulled high by adding a REN resistor
driver voltage for the high side MOSFET. and CEN capacitor from the VIN pin (see Figure 3).
It is recommended to add an external bootstrap diode EN
REN
between an external 5V and BOOT pin for efficiency VIN EN
improvement when input voltage is lower than 5.5V or duty CEN

RT7237A
ratio is higher than 65% .The bootstrap diode can be a GND

low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the Figure 3. Enable Timing Control
RT7237A. Note that the external boot voltage must be
lower than 5.5V An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2.5V
5V is available, as shown in Figure 4. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
EN pin. MOSFET Q1 will be under logic control to pull
BOOT
down the EN pin.
RT7237A 0.1µF
SW REN
100k
VIN EN
Figure 2. External Bootstrap Diode EN Q1 RT7237A
GND
Figure 4. Digital Enable Control Circuit


10
RT7237A
Under Voltage Protection Clamp Mode
For the RT7237AN, it provides inductor current clamp
Hiccup Mode
mode. In shutdown condition, the RT7237AN can be reset
For the RT7237AH, it provides Hiccup Mode Under Voltage
by removing short condition.
Protection (UVP). When the VFB voltage drops below 0.4V,
Clamp Mode
the UVP function will be triggered to shut down switching
operation. If the UVP condition remains for a period, the
RT7237AH will retry automatically. When the UVP VOUT
(2V/Div)
condition is removed, the converter will resume operation.
The UVP is disabled during soft-start period.
Hiccup Mode
I SW
VOUT (1A/Div)
(2V/Div)
Time (5ms/Div)
Figure 7. Clamp Mode
I SW Over Temperature Protection

(1A/Div) The RT7237A features an Over Temperature Protection
IOUT = Short
(OTP) circuitry to prevent from overheating due to
Time (25ms/Div) excessive power dissipation. The OTP will shut down
Figure 5. Hiccup Mode Under Voltage Protection switching operation when junction temperature exceeds
Latch-Off Mode 150°C. Once the junction temperature cools down by
approximately 20°C, the converter will resume operation.
For the RT7237AL, it provides Latch-Off Mode Under
To maintain continuous operation, the maximum junction
Voltage Protection (UVP). When the FB voltage drops
temperature should be lower than 125°C.
below half of the feedback reference voltage, VFB, UVP
will be triggered and the RT7237AL will shutdown in Latch- Inductor Selection
Off Mode. In shutdown condition, the RT7237AL can be
The inductor value and operating frequency determine the
reset by EN pin or power input VIN.
ripple current according to a specific input and output
Latch-Off Mode voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥

V V
⎣ f ×L ⎦ ⎣ VIN ⎦
VOUT
(2V/Div) Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
the highest efficiency operation. However, it requires a
I SW
large inductor to achieve this goal.
(1A/Div) For the ripple current selection, the value of ΔIL = 0.24(IMAX)
IOUT = Short
will be a reasonable starting point. The largest ripple
Time (25μs/Div)
current occurs at the highest VIN. To guarantee that the
Figure 6. Latch-Off Mode Under Voltage Protection

11
RT7237A
ripple current stays below the specified maximum, the The output ripple, ΔVOUT , is determined by :
ΔVOUT ≤ ΔIL ⎡⎢ESR + ⎤

inductor value should be chosen according to the following 1
equation : ⎣ 8fCOUT ⎦⎥
⎡ VOUT ⎤ ⎡ VOUT ⎤ The output ripple will be the highest at the maximum input
L =⎢ ⎥ × ⎢1 − ⎥
⎣ f × Δ IL(MAX) ⎦ ⎣ VIN(MAX) ⎦ voltage since ΔIL increases with input voltage. Multiple
The inductor's current rating (caused a 40°C temperature capacitors placed in parallel may be needed to meet the
rising from 25°C ambient) should be greater than the ESR and RMS current handling requirement. Higher values,
maximum load current and its saturation current should lower cost ceramic capacitors are now becoming available
be greater than the short circuit peak current limit. Please in smaller case sizes. Their high ripple current, high voltage
see Table 2 for the inductor selection reference. rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
Table 2. Suggested Inductors for Typical capacitors are used at input and output. When a ceramic
Application Circuit capacitor is used at the input and the power is supplied
Component Dimensions by a wall adapter through long wires, a load step at the
Series
Supplier (mm)
output can induce ringing at the input, VIN. At worst, a
TDK VLF10045 10 x 9.7 x 4.5
sudden inrush of current through the long wires can
TDK SLF12565 12.5 x 12.5 x 6.5
potentially cause a voltage spike at VIN large enough to
TAIYO
NR8040 8x8x4 damage the part.
YUDEN
Thermal Considerations
CIN and COUT Selection
For continuous operation, do not exceed the maximum
The input capacitance, C IN, is needed to filter the
operation junction temperature 125°C. The maximum
trapezoidal current at the source of the high side MOSFET.
power dissipation depends on the thermal resistance of
To prevent large ripple current, a low ESR input capacitor
IC package, PCB layout, the rate of surroundings airflow
sized for the maximum RMS current should be used. The
and temperature difference between junction to ambient.
approximate RMS current equation is given :
The maximum power dissipation can be calculated by
V VIN
IRMS = IOUT(MAX) OUT −1 following formula :
VIN VOUT
This formula has a maximum at VIN = 2VOUT, where PD(MAX) = (TJ(MAX) − TA ) / θJA
IRMS = IOUT / 2. This simple worst case condition is Where T J(MAX) is the maximum operation junction
commonly used for design because even significant temperature , TA is the ambient temperature and the θJA is
deviations do not offer much relief. the junction to ambient thermal resistance.
Choose a capacitor rated at a higher temperature than For recommended operating conditions specification, the
required. Several capacitors may also be paralleled to maximum junction temperature is 125°C. The junction to
meet size or height requirements in the design. ambient thermal resistance θJA is layout dependent. For
For the input capacitor, two 10μF low ESR ceramic SOP-8 (Exposed Pad) package, the thermal resistance
capacitors are suggested. For the suggested capacitor, θJA is 75°C/W on the standard JEDEC 51-7 four-layers
please refer to Table 3 for more details. thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
The selection of COUT is determined by the required ESR
to minimize voltage ripple. P D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable. P D(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
Loop stability can be checked by viewing the load transient (70mm2copper area PCB layout)
response as described in a later section.

12
RT7237A
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to increase
thermal performance by the PCB layout copper design.
The thermal resistance θJA can be decreased by adding
copper area under the exposed pad of SOP-8 (Exposed (a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
Pad) package.
As shown in Figure 8, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 8.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 8.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 8.e) (b) Copper Area = 10mm2, θJA = 64°C/W
reduces the θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed T J(MAX) and thermal
resistance θJA. The Figure 9 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
(c) Copper Area = 30mm2 , θJA = 54°C/W
2.2
Four-Layer PCB
2.0
1.8
Power Dissipation (W)
1.6 Copper Area

70mm2
1.4
50mm2
1.2 30mm2
1.0 10mm2
Min.Layout
0.8
0.6
(d) Copper Area = 50mm2 , θJA = 51°C/W
0.4
0.2
0.0
0 25 50 75 100 125
Ambient Temperature (°C)
Figure 9. Derating Curve of Maximum Power Dissipation

(e) Copper Area = 70mm2 , θJA = 49°C/W
Figure 8. Thermal Resistance vs. Copper Area Layout

Design

13
RT7237A
Layout Consideration ` SW node is with high frequency voltage swing and
Follow the PCB layout guidelines for optimal performance should be kept at small area. Keep analog components
of the RT7237A. away from the SW node to prevent stray capacitive noise
pick-up.
` Keep the traces of the main current paths as short and
wide as possible. ` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
` Put the input capacitor as close as possible to the device
components near the RT7237A.
pins (VIN and GND).
` An example of PCB layout guide is shown in Figure 10
for reference.
GND VIN SW GND VIN The feedback components

must be connected as close
CBOOT REN to the device as possible.
Input capacitor must CSS
CIN CC
be placed as close
BOOT 8 SS
to the IC as possible.
VIN 2 7 EN CP RC
L GND
VOUT SW 3 6 COMP
9 R1
GND 4 5 FB
R2
VOUT
COUT
GND
SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 10. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT

Location Component Supplier Part No. Capacitance (μF) Case Size
CIN MURATA GRM31CR61E106K 10 1206
CIN TDK C3225X5R1E106K 10 1206
CIN TAIYO YUDEN TMK316BJ106ML 10 1206
COUT MURATA GRM31CR60J476M 47 1206
COUT TDK C3225X5R0J476M 47 1210
COUT MURATA GRM32ER71C226M 22 1210
COUT TDK C3225X5R1C22M 22 1210

14
RT7237A
Outline Dimension
H
A
EXPOSED THERMAL PAD Y

(Bottom of Package)
J X B
C
I
D
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 4.000 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.510 0.013 0.020
F 1.194 1.346 0.047 0.053
H 0.170 0.254 0.007 0.010
I 0.000 0.152 0.000 0.006
J 5.791 6.200 0.228 0.244
M 0.406 1.270 0.016 0.050
X 2.000 2.300 0.079 0.091
Option 1
Y 2.000 2.300 0.079 0.091
X 2.100 2.500 0.083 0.098
Option 2
Y 3.000 3.500 0.118 0.138
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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®

2A, 18V, 340kHz Synchronous Step-Down Converter

Simplified Application Circuit

VIN VIN BOOT

DS7237A-01 September 2012 www.richtek.com

Functional Pin Description

www.richtek.com DS7237A-01 September 2012

DS7237A-01 September 2012 www.richtek.com

Recommended Operating Conditions (Note 4)

www.richtek.com DS7237A-01 September 2012

DS7237A-01 September 2012 www.richtek.com

Table 1. Suggested Components Selection

www.richtek.com DS7237A-01 September 2012

Output Voltage (V)

Reference Voltage vs. Temperature Output Voltage vs. Output Current

Switching Frequency vs. Input Voltage Switching Frequency vs. Temperature

Switching Frequency (kHz)1

DS7237A-01 September 2012 www.richtek.com

Current Limit vs. Temperature Load Transient Response

Load Transient Response Output Ripple Voltage

Time (100μs/Div) Time (2.5μs/Div)

Power On from VIN Power Off from VIN

Time (10ms/Div) Time (10ms/Div)

www.richtek.com DS7237A-01 September 2012

Power On from EN Power Off from EN

Time (10ms/Div) Time (10ms/Div)

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improvement when input voltage is lower than 5.5V or duty CEN

ratio is higher than 65% .The bootstrap diode can be a GND

Figure 2. External Bootstrap Diode EN Q1 RT7237A

Figure 4. Digital Enable Control Circuit

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I SW Over Temperature Protection

ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥

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ΔVOUT ≤ ΔIL ⎡⎢ESR + ⎤

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1.6 Copper Area

Ambient Temperature (°C)

Figure 9. Derating Curve of Maximum Power Dissipation

Figure 8. Thermal Resistance vs. Copper Area Layout

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GND VIN SW GND VIN The feedback components

Figure 10. PCB Layout Guide

Table 3. Suggested Capacitors for CIN and COUT

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EXPOSED THERMAL PAD Y

Dimensions In Millimeters Dimensions In Inches

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

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