Ele Ii

ELC - 122
BASICS OF COMPUTER
ORGANIZATION
[2 Credits]
Electronics Paper-II
For
First Year B.Sc. Computer Science - Semester-II
New Syllabus as per CBCS Pattern
from June 2019
S. R. Chaudhari Dr. J. A. Bangali

M. Sc., M.Phil. M. Sc., M. Phil, Ph.D.
Vice Principal and Head, Head, Dept. of Electronic Science,
Dept. of Electronic Science, Kaveri College of Science & Commerce,
Modern College, Shivajinagar, Pune - 411038
Pune – 411005.
Prof. (Dr.) M. L. Dongare Prof. (Dr.) P. B. Buchade

M.Sc., D.H.E., Ph.D. M.Sc., M.Phil., Ph.D.
Head, Dept. of Electronic Science, Principal and Head,
Rayat Shikshan Sanstha's, Dept. of Electronic Science,
S. M. Joshi College, Abasaheb Garware College,
Hadapsar, Pune – 411028. Karve Road, Pune - 411004.
Price ` 70.00
N5063
F.Y.B.Sc : Basics of Computer Organisation ISBN 978-93-89686-46-3
First Edition : November 2019
© : Authors
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Preface …
We have great pleasure to present this book on ‘Basics of Computer
Organization’ which is written as per the revised syllabus of Savitribai
Phule Pune University for F.Y.B.Sc. (Computer Science), semester II course
ELC 122 in the subject of Electronics. The authors have sincerely put their
efforts to give complete information of the subject as prescribed in the
syllabus in a simplified manner.
Electronics and computer science go hand in hand. In fact, electronics
is a backbone for understanding computer operations.
This text book has been prepared keeping in mind the need of
subject and syllabus specified by SPPU.
The First Chapter describes Flip-flops, their types, working principles
and their application.
Second chapter gives details of shift registers and counters, basics of
shift registers and counters, their functioning with timing diagram are
elaborated.
Basics of computer system are discussed in detail in chapter three. In
this chapter computer organization, various kinds of bus structures used
in computer, CPU organization, execution of system, stack concept and
input / output interface organization is elaborated.
Chapter four describes memory organization. In this chapter memory
architecture, memory hierarchy, types of memories and management of
memory space is discussed in detail.
After studying all this, students will get a clear understanding of
computer organization. To give something extra to think and to explore
the topic, ‘Think over It’ element is added in this book. As per new choice
based credit based system syllabus of Savitribai Phule Pune University
questions like multiple choice, true/false, short answer, long answer type
questions are included at the end of each unit. Also two sample question
papers as per university guidelines are provided.
We are thankful to the publishers Shri Dineshbhai Furia and Shri
Jignesh Furia and the staff of Nirali Prakashan specially Mr. Ilyas Shaikh,
Mrs. Manasi Pingle, Ms. Chaitali Takle, Mr Ravindra Walodare for the
great efforts they have taken to publish this book in time.
All valuable suggestions from the readers of this book are always
welcome.
AUTHORS
Syllabus …
Unit 1 : Flip-Flops (5 L)
RS Flip-Flop using NAND gate, Clocked RS Flip-Flop, D Latch, J K
Flip-Flop, T Flip-Flop
Unit 2 : Shift Registers and Counters (9 L)
Shift registers - SISO, SIPO, PISO, PIPO shift registers, Ring counter
using D Flip-flop. Counters - Synchronous and Asynchronous type,
3-bit Up, Down and Up-Down counter, Concept of Modulus counters
(Timing Diagram of all above are expected)
Unit 3 : Basics of Computer System (12 L)
Basic Computer organization, Concept of address bus, Data bus,
Control bus. CPU block diagram and explanation of each block,
Register based CPU organization, Concept of Stack and its
organization, I/O organization: Need of interface, Block diagram of
general I/O interface
Unit 4 : Memory Organization (10 L)
Memory architecture, Memory hierarchy, Types of Memories, Data
Read/ Write process, Vertical and Horizontal Memory Expansion, Role
of Cache memory, Virtual memory.
Contents …
1. Flip-Flops 1.1 − 1.18
2. Shift Registers and Counters 2.1 − 2.32
3. Basics of Computer System 3.1 − 3.46
4. Memory Organization 4.1 − 4.36
Model Question Papers P.1 - P.2
✍✍✍
BASICS OF COMPUTER
ORGANIZATION
Electronics (For Computer Science) : Paper-II
N5063
1. Title
2. Pressline
3. Preface
4. Blank
5. Syllabus
6. Blank
7. Contents
8. Blank
Contents …
1. Flip-Flops 1.1 − 1.18
2. Shift Registers and Counters 2.1 − 2.32
3. Basics of Computer System 3.1 − 3.46
4. Memory Organization 4.1 − 4.36
Model Question Papers P.1 - P.2
Note 1
Add 1
✍✍✍
Unit 1…
Flip-Flops
The first electronic flip-flop was invented in 1918
by the British physicists William Eccles and F. W.
Jordan. It was initially called the Eccles–Jordan
trigger circuit and consists of two vacuum tubes
as an electronic component available in that
period. The design was used in 1943 in British
Colossus code breaking computer. Afterwards it
was designed with transistors and were common
in computers even after the introduction of
William Eccles integrated circuits, though flip-flops are made
from logic gates.
Early flip-flops were known as trigger circuits or multivibrators, then
were progressed to clocked flip-flops and counters, then shift registers
were developed.
William Henry Eccles FRS (23 August 1875 – 29 April 1966) was a
British physicist and a pioneer in the development of radio
communication. He was born in Barrow-in-Furness, Lancashire, England.
He was an assistant to Guglielmo Marconi, the Italian radio entrepreneur.
In 1901, he received his doctorate from the Royal College of Science.
Eccles was an advocate of Oliver Heaviside's theory that a conducting
layer of the upper atmosphere could reflect radio waves around the
curvature of the Earth.
Frank Wilfred Jordan (6 October 1881 – 12 January 1941) was a
British physicist who together with William Henry Eccles invented the so-
called "flip-flop" circuit in 1918. This circuit became the basis of electronic
memory as a major part in computers.
1.1 Introduction
• After reading this unit, you will be able to use logic gates to construct
basic latches and can recognize the difference between a latch and a
flip-flop. You can also explain how R-S and J-K flip-flops differ and
know how to apply flip-flops in basic applications.
1.1
F.Y.B.Sc. Electronics (Comp. Sci.) (P-II) 1.2 Flip-Flops
• The cross-coupled gates used to store binary data are known as flip-
flops. There are different types of flip-flops. Flip-flops are basic
building blocks of counters, shift registers and memory devices.
• A flip-flop can store 1-bit of digital information. It is also referred to
as a 1-bit register. A register contains a group of flip-flops, the
number of flip-flops in a register being equal to the number of bits
present in the data. Flip-flops are connected in such a way that binary
number can be entered into the register and retrieved from the same.
1.2 RS Flip-Flop using NAND Gate
• Flip-flop can be obtained using any type of gates, but since NAND
and NOR are the universal gates, we will see flip-flop using NAND
gate.
• Fig. 1.1 shows S-R flip-flop using NAND gates.
S N3 R S Q
N1 Q
0 0 NC
0 1 1
1 0 0
1 1 Forbidden
N2 Q
R N4
(a) S-R flip-flop using NAND gates (b) Truth table

Fig. 1.1
• The circuit uses four NAND gates. N1 and N2 are two inputs whereas
N3 and N4 are used as an inverter. It has two inputs S and R and two
−
outputs Q and Q. The outputs are cross coupled to the input; that is
known as feedback. This cross coupling or feedback is responsible for
memory of the circuit and that is the general feature of all flip-flop
circuits. Since there are two inputs with digital logic, there are four
possible cases for output as discussed below.
• Case (i) S = 0, R = 1 : Then output of N3 is 1 and output of N4 is 0.
Whatever may be the initial output for N2, one input is zero, so
−
Q = 1, for N1 both inputs are 1, so Q becomes 0.
• Case (ii) S = 1, R = 0 : Then output of N3 is 0 and output of N4 is 1.

Whatever may be initial output for N1, one input is 0, so output Q
becomes 1 which is fed back to N2. For N2 both inputs are 1 which
−
make Q = 0.
• Case (iii) S = 0, R = 0 : Outputs of both N3 and N4 will become 1. If
−
previously Q = 0 for N2 one input is 0 which makes Q = 1, that 1 is
fed back to N1, for N1 both inputs are 1 which keep output 0 which is
assumed. If we assume previous output 1, it will remain the same,
that means when S = 0, R = 0 there is no change in the state of the
flip-flop.
• Case (iv) S = 1, R = 1 : For this situation, outputs of N3 and N4 will
become 0, one input of both NAND gates N1 and N2 becomes 0
−
which tries to make Q and Q both 1 but that is contradictory to our
definition. So S = 1, R = 1 is the forbidden condition.
• Note that, N3 and N4 are added only for the convenience, they may
be absent in the Fig. 1.1 (a), they just invert the input. However, if
they are absent, the output Q must be named to the gate whose one
−
input is R and output Q be named to the gate whose one input is S.
Fig. 1.2 shows S-R flip-flop using two NAND gates along with the
truth table.
S
Q
R S Q
0 0 NC
0 1 1
1 0 0
Q 1 1 Forbidden
R
(a) S-R flip-flop using NAND gates (b) Truth table

Fig. 1.2
1.2 Clocked RS Flip-Flop
• In a sequential system, it is required to set or reset the flip-flop in
synchronism with clock pulses. This is achieved in clocked S-R flip-
flop.
• The S-R flip-flop is modified to clocked S-R flip-flop by changing N3
and N4 in Fig. 1.3 (a) to two input NAND gates and by applying the
clock pulses simultaneously to N3 and N4. Fig. 1.3 (a) shows the
clocked S-R flip-flop.
S
N3
N1 Q Sn Rn Qn + 1
0 0 Qn S Q
CLK 1 0 1 CK
0 1 0
R Q
N2 Q 1 1 Forbidden
R N4
(a) Clocked S-R flip-flop (b) Truth table (c) Logic symbol
Fig. 1.3
• If the clock pulse is absent CLK = 0, whatever may be S and R,
outputs of N3 and N4 are 1. If Q = 1 it remains 1 whereas if Q = 0 it
remains 0. The flip-flop does not change the state. The circuit is
equivalent to a latch.
• If the clock pulse is present, CLK = 1. If S = 0, R = 0 then outputs of
N3 and N4 are 1 and the output of the flip-flop does not change.
Hence, after the pulse, output remains same as before the pulse. If we
denote the inputs Sn and Rn before the pulse then output after the
pulse is Qn+1 = Qn and this is indicated in the first row of the truth
table.
• If CLK = 1, Sn = 1 and Rn = 0 then output of N3 is 0, output of N4 is 1,
which make Q = 1. Hence, after the clock pulse, we find Qn+1 = 1.
• If CLK = 1, Sn = 0 and Rn = 1 then we find Qn+1 = 0. This confirms
second and third rows of the truth table.
• If CLK = 1, Sn = 1 and Rn = 1 then outputs of NAND gates N3 and N4
are both 0. Hence, whatever may be previous output one input of N1
and N2 is 0, so that outputs of both N1 and N2 must be 1, but
−
according to our definition, Q and Q must be complement. In
practice, whether N1 input or N2 input rises faster from 0 to 1 and
depending upon circuit parameter we get asymmetric output either
the state Q = 0 or Q = 1. This state is said to be indeterminate,
ambiguous or undefined, and the condition Sn = 1, Rn = 1 is
forbidden and should not be applied. This ambiguity present in the
truth table is overcome by J-K flip-flop.
1.3 JK Flip-Flop
• J-K flip-flop can be obtained from S-R flip-flop along with two AND
−
gates G1 and G2. Data input J and the output Q are applied to G1.
−
Since its output generates S, then S = JQ. Similarly, data input K and
the output Q are applied to G2 and hence R = KQ. Fig. 1.4 shows S-R
flip-flop converted into J-K and its truth table.
(a) J-K flip-flop (b) Truth table

Fig. 1.4
• For two J and K inputs by digital logic there are four possibilities. At
the same time there are two possible states for Q which generate
eight possibilities. The following Table 1.1 has eight rows, from Jn, Kn,
−
Qn and Qn, Sn and Rn are calculated and entered into 5th and 6th
columns of the table. Using these values of Sn and Rn and referring to
the S-R flip-flop, 7th column i.e. Qn + 1 is obtained and finally column
8 follows from column 7.
Table 1.1 : Truth table of Fig. 1.4
Column 1 2 3 4 5 6 7 8
Row Jn Kn Qn – Sn Rn Qn+1
Qn
1 0 0 0 1 0 0 Qn
Qn
2 0 0 1 0 0 0 Qn
3 1 0 0 1 1 0 1
1
4 1 0 1 0 0 0 Qn
5 0 1 0 1 0 0
Qn
6 0 1 1 0 0 1 0
0
7 1 1 0 1 1 0
1 –
8 1 1 1 0 0 1 Qn
0
• Thus, we see that the first three rows of J-K flip-flop truth table are
same as that of S-R flip-flop truth table. When the data inputs J and K
are high, the output gets complemented by the clock pulse. In case of
S-R flip-flop, we cannot apply S = 1, R = 1 but in case of J-K flip-flop,
we can apply J = 1, K = 1.
1.4.1 J-K Flip-Flop With Only NAND Gates
• Fig. 1.4 (a) shows J-K flip-flop which uses AND gates. However, we
can also obtain J-K flip-flop only using NAND gates. Fig. 1.5 shows
J-K flip-flop using only NAND gates. N1 and N2 are two input NAND
gates whereas N3 and N4 are three input NAND gates.
• If J = 0, K = 0, outputs of N3 and N4 are one since one input of N3 and
N4 is 0.
−
• If Q = 0 and Q = 1, for N2 one input is 0, so its output remains 1 and
for N1 both inputs are 1 so gives same output 0 as assumed. Thus,
output remains in the previous state.
J N3
N1 Q
CLK
N2 Q
N4
K
Fig. 1.5 : J-K flip-flop using only NAND gates
• If J = 0, K = 1 and CLK = 1 for N3 one input is 0, so output is 1. For N4
−
if Q = 1 all inputs are 1, so output is 0 then for N2 one input is 0, so Q
becomes 1. For N1 both inputs are 1, so output Q becomes 0. So
output becomes same as J input even if J = 1 and K = 0.
• If J = 1, K = 1 and CLK = 1. If Q = 1 for N4 all inputs are 1, so output
of N4 is 0. For N3 one input is 0 so output is 1. For N2, one input is 0.
−
So Q becomes 1. For N1 both inputs are 1 so output becomes 0 i.e. if
we assume Q = 0 it becomes 1. If we assume Q = 1, it becomes 0.
Thus, when J = 1, K = 1, output becomes complement of previous
state.
• Thus, for all possible values of J and K, the circuit follows the truth
table of J-K flip-flop.
1.4.2 Preset and Clear

• In case of J-K flip-flop when J = 1, K = 1 and clock is applied, output
becomes complement of previous state. But the previous state is
arbitrary, it may be 0 or 1.
• It is possible to assign initial state to the flip-flop.
• We can clear the flip-flop or set the flip-flop by addition of two more
inputs to the flip-flop which are known as preset and clear.
• If NAND gates N1 and N2 of Fig. 1.5 are converted into three input as
shown in Fig. 1.6 we can assign initial state to the flip-flop.
Pr
Pr
J
N3 N1 Q
J Q
CLK
CK
N4 N2 Q K Q
K
Cr
Cr
(a) J-K flip-flop with preset and clear (b) The logic symbol
Fig. 1.6
• If we want to clear the flip-flop, apply Pr = 1, Cr = 0 and CLK = 0.
−
Since Cr is 0 the output of N2 is Q = 1. Since CLK = 0, the output of
N3 is 1 and hence all inputs to N1 are 1 which give Q = 0 as required.
• Similarly, if we want to preset the latch or flip-flop, apply Pr = 0,
Cr = 1, CLK = 0. The preset and clear inputs are called direct or
asynchronous input since they are not in synchronous with the clock
and may be applied before the clock or in between the clock pulses.
Once the state to the flip-flop is assigned, Pr = 1, Cr = 1 must be
maintained, that is for the normal operation of the flip-flop, Pr = 0
and Cr = 0 must not be used since it leads to ambiguous state at the
output.
• Table 1.2 summarises the operation of preset and clear input.

Table 1.2 : Preset and clear requirement
CLK Cr Pr Remark
0 0 1 To clear the flip-flop
0 1 0 To set the flip-flop
1 1 1 For normal operation
∞ 0 0 Not allowed.
1.4.3 The Race Around Condition
• The truth table of Fig. 1.4 (b) of J-K flip-flop assumes that the inputs
are independent of the output. However, because of the feedback
connection at the input there is difficulty with the J-K flip-flop
constructed as shown in Fig. 1.4 or 1.5.
• Consider for example, J = 1, K = 1 and Q = 0. When the clock pulse is
applied, the output becomes Q = 1. This change takes place after a
time interval ∆t equal to the propagation delay through NAND gates
in series. If clock pulse is still there, since J = 1, K = 1 and Q = 1, the
output will become 0.
• Thus, for the duration tp of the clock pulse, the output will oscillate
back and forth between 0 and 1, and at the end of the pulse, the
value of Q may be 0 or 1 i.e. ambiguous. This situation is known as
race around condition. It can be avoided if tp < ∆t. However, in
practice, ∆t is very small.
• There are two possible solutions : One is to convert wide duration
clock pulse into spikes using differentiator circuit and then apply to
clock input or construct another circuit known as master slave J-K
flip-flop.
1.4.4 Concept of Triggering Levels
• In a simple clocked flip-flop when the input of a flip-flop is changed,
output will change as long as clock is high, whether the flip-flop is
S-R or J-K.
• When the clock goes low, the state present at the input will be stored
or latched, in case of S-R flip-flop, whereas in case of J-K flip-flop
output gets complemented.
• Usually, it is necessary to store the input of flip-flop instantaneously
and for that we need a very narrow clock pulse. Such narrow clock
pulse is also required in case of J-K flip-flop to avoid race around
condition.
• The square pulse can be converted into positive and negative going
spikes using R-C differentiator circuit. Fig. 1.7 shows such circuit.
J Q
C
CLK CK
R
K Q
Fig. 1.7 : J-K flip-flop with edge triggering

• The values of R and C are so chosen that RC time constant is much
smaller than the clock pulse width and hence such circuit converts
pulses into positive and negative going spikes.
• The narrow positive spikes enable the internal gates for an instant.
The narrow negative spikes does nothing. Thus, during positive spikes
gate is enabled, flip-flop follows its truth table. This kind of operation
is called edge triggering because flip-flop responds only when the
clock is in transition. In the Fig. 1.7, the triggering occurs on the
positive going edge of the clock. That is why, it is referred to as
positive edge triggering.
• Sometimes, triggering on negative edge is better suited or more
suitable to the application. In this case, an internal inverter can
complement the clock pulse before it reaches to the NAND gate. This
means the trailing/falling edge of the clock activates the gates, this is
known as negative edge triggering. Fig. 1.8 shows the circuit symbol
of positive and negative edge triggered flip-flops.
Pr Pr
J Q J Q
CK CK
K Q K Q
Cr Cr
(a) Positive edge triggering (b) Negative edge triggering
Fig. 1.8 : Edge triggering
1.4.5 Master Slave J-K Flip-Flop

• Fig. 1.9 shows the two S-R flip-flops cascaded with feedback from the
output of the second to the input of the first. The first stage is known
as master whereas the second as slave. Clock pulses are applied to
the master, the same are inverted and then applied to the slave.
Pr
Qm S
J Q
CLK
Qm R
K Q
Cr CK
Master Slave
Fig. 1.9 : A master slave J-K flip-flop
• As seen previously for normal operation, Pr = 1, Cr = 1 must be held.
For Pr = 1, Cr = 1 and CK = 1, the master is enabled and its operation
––
follows the J-K truth table. At the same time, since CK = 0, the slave
remains disabled or cannot change the state. So output Qn does not
change the state during tp and hence the race around difficulty is
removed, after the pulse passes CK = 0, so that the master is inhibited
––
and CK = 1, which causes slave to be enabled.
• If S = 1 and R = 0 then Q = 1 or if S = 0 and R = 1 then Q = 0. Thus,
in case of Master Slave J-K flip-flop, during a clock pulse output Q
does not change but Qm follows J-K logic and at the end of the pulse,
the value of Qm is transferred to Q.
1.4 D Latch
• J-K flip-flop is modified into D (delay) flip-flop by adding an inverter
between J and K input, so that K is always the complement of J. The
input is named as D input.
• Fig. 1.10 shows logic circuit, logic symbol and the truth table of D
type flip-flop.
Pr Pr
D J Q D Q Dn Qn + 1
1 1
CLK CK CK
0 0
K Q Q
Cr Cr
(a) Logic diagram of J-K (b) Logic symbol (c) Truth table converted
into D flip-flop
Fig. 1.10 : D flip-flop
• If Dn is 1 then Jn = 1, Kn = 0 and hence Qn+1 = 1.
• If Dn is 0 then Jn = 0, Kn = 1 and then Qn+1 = 0.
• The output Qn+1 after the pulse equals the input Dn before the pulse
and therefore D flip-flop is used to provide delay. The bit on the D
line is transferred to the output at the next clock pulse and hence
flip-flop functions as 1-bit delay device.
• The S-R flip-flop can also be converted into D type by adding an
inverter between S and R and then there is no ambiguous state since
S = R is not possible.
1.5 T Flip-Flop
• The J-K flip-flop is modified into T by connecting J and K together.
This unit changes the state with each clock pulse, acts as a toggle
switch and hence the name. Fig. 1.11 shows the T-flip-flop.
Pr Pr
T J Q T Q
Tn Qn + 1
CLK CK CK 0 Qn
1 Qn
K Q Q
Cr Cr
(a) J-K converted into T flip-flop (b) Logic symbol (c) Truth table
Fig. 1.11 : J-K flop-flop
−
• When J = K = 1 then Qn+1 = Qn and when J = K = 0, then Qn+1 = Qn.
According to the truth table of J-K flip-flop, T flip-flop is also known
as complementing flip-flop. If T = 1 and the clock pulses as shown in
Fig. 1.12 are applied, the flip-flop behaves as divide by 2 circuit
because it gives 0 to 1 transition at first clock pulse and 1 to 0 at the
next clock pulse i.e. two input pules are required to have one output
pulse. If the clock input square wave has frequency of 10 kHz, the
output at T flip-flop will have frequency 5 kHz. Thus, one flip-flop
does the operation of frequency division by two.
Fig. 1.12 : T flip-flop output
Think Over It
• Can we use two or more master J-K flip-flop cascaded as a shift

register ?
• As in S-R flip-flop S is SET and R is RESET, What is J and K in
J-K Flip Flop? (Hint: The two inputs labelled “J” and “K” are not
shortened abbreviated letters of other words, such as “S” for Set
and “R” for Reset, but are themselves autonomous letters
chosen by its inventor Jack Kilby to distinguish the flip-flop
design from other types.)
• Can we use flip-flop as frequency divider circuit? (Hint: Study
output with timing diagram for input and output corresponding
to truth table.)
Summary
1. A latch is a type of memory storage device that has two stable states.
2. The latch stores 1-bit information.
3. A flip-flop is a bistable device and have two stable states.

4. Flip-flops are also known as latches.
5. A S-R flip-flop has two inputs, S(SET), and R(RESET), and two outputs
− −
Q and Q, Where Q is complemented output.
6. In a sequential system, it is required to set or reset the flip-flop in
synchronism with clock pulses. This is achieved in clocked S-R flip-
flop.
7. The JK flip-flop is similar to the SR Flip-flop but there is no change in
state when the J and K inputs are both LOW.
8. The JK flip-flop is basically an SR flip-flop with feedback, which
enables only one of its two input terminals, either SET or RESET to be
active at any one time thereby eliminating the invalid condition seen
in the SR flip-flop circuit.
9. The Master-Slave flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave having an
inverted clock pulse.
10. PRESET input is used to directly put a “1” in the Q output on the JK
flip-flop.
11. CLEAR input is used to directly put a “0” in the Q output on the JK
flip-flop.
12. Clock signal is a periodic signal and its ON time and OFF time need
not be the same. We can represent the clock signal as a square wave,
when both its ON time and OFF time are same.
13. The flip-flop which have a small bubble in the PRESET or CLEAR
inputs indicate that they are active low.
14. D flip-flop operates with only positive clock transitions or negative
clock transitions. Whereas, D latch operates with enable signal and
can be used as memory device.
15. T flip-flop is the simplified version of JK flip-flop. It is obtained by
connecting the same input ‘T’ to both inputs of JK flip-flop.
16. T flip-flop operates with only positive clock transitions or negative
clock transitions.
17. The output of T flip-flop always toggles for every positive transition
of the clock signal, when input T remains at logic High. Hence, T flip-
flop are used in counters.
Exercise
[A] True or False :
1. Flip-Flop can be used as memory device.
2. Race around condition is overcome in J-K flip-flop.
3. PRESET input is used to directly reset the Q output to 1 in the JK flip-
flop.
4. D flip-flop is also known as direct flip-flop.
5. In counters T flip-flop is used.
6. In Master Slave JK flip-flop, Slave copies state of Master.
7. When J = 1, K = 1 , J-K flip-flop is in toggle mode.
8. It is necessary to store the input of flip-flop instantaneously and for
that we need wide range clock pulse.
9. Trigger pulse is defined as, a pulse that starts a cycle of operation.
−
10. The term CLEAR always means that Q = 0, Q = 1.
11. The J-K flip-flop eliminates the invalid state by toggling when both
inputs are high and the clock transitions.
12. A positive edge-triggered flip-flop changes states with a HIGH-to-
LOW transition on the clock input.
[B] Multiple Choice Questions :
1. The invalid state of an S-R latch occurs when ……
(a) S = 1, R = 0 (b) S = 0, R = 1
(c) S = 1, R = 1 (d) S = 0, R = 0
2. The purpose of the clock input to a flip-flop is to ……
(a) clear the device
(b) set the device
(c) always cause the output to change states
(d) cause the output to assume a state dependent on the controlling
inputs
3. For an edge-triggered D flip-flop, ……
(a) a change in the state of an flip-flop occurs only at a clock pulse
edge
(b) the state that the flip-flop goes to depends on the D inputs
(c) the output follows the input at each clock pulse
(d all the above
4. A flip-flop is in the toggle condition when ……

(a) J = 1, K = 0 (b) J = 1, K = 1
(c) J = 0, K = 0 (d) J = 0, K = 1
5. A basic S-R flip-flop can be constructed by cross-coupling of which
basic logic gates?
(a) AND or OR gates, (b) XOR or XNOR gates
(c) NOR or NAND gates (d) AND or NOR gates
6. If Q = 0, the output is said to be ……
(a) Set (b) Reset
(c) Previous state (d) Current state
7. What is a trigger pulse?
(a) A pulse that starts a cycle of operation
(b) A pulse that reverses the cycle of operation
(c) A pulse that prevents a cycle of operation
(d) A pulse that enhances a cycle of operation
8. On a master-slave flip-flop, when is the master enabled?
(a) when the gate is LOW (b) when the gate is HIGH,
(c) both of the above (d) neither of the above
9. A J-K flip-flop is in a "no change" condition when …… .
(a) J = 1, K = 1 (b) J = 1, K = 0
(c) J = 0, K = 1 (d) J = 0, K = 0
10. D Flip has ……
(a) One input, One output (b) Two input, Two output
(c) One input, Two output (d) Two input, One output
[C] Long Answer Questions:
1. What is a flip-flop ? Explain with diagram and state its use.
2. Explain the working of S-R flip-flop with logic diagram, symbol and
truth table.
3. What is the limitation of S-R flip-flop ? How it is overcome ?
4. Draw the circuit diagram of J-K flip-flop. Explain its action.
5. Explain what is meant by a race around condition in connection with
the J-K flip-flop.
6. State the function of preset and clear. Draw the logic diagram of J-K
flip-flop with preset and clear.
7. Draw a master slave J-K flip-flop system. Explain its operation and
show that it eliminates the race around condition.
8. Show how to convert a J-K flip-flop into D-type. Give its truth table.
9. Draw the logic diagram of S-R flip-flop converted into D-type. Give
its truth table.
10. Draw the logic diagram to convert J-K into T-type. Give its truth table.
11. Explain with suitable waveform that one flip-flop does the frequency
division by 2.
12. Define the terms positive edge triggered flip-flop and negative edge
triggered flip-flop.
13. Draw the circuit symbol of J-K flip-flop with positive edge triggering
and with negative edge triggering.
14. State the function of PRESET and CLEAR input to the flip-flop. Draw
logic diagram of J-K flip-flop with preset and clear inputs.
15. Define the terms positive edge triggered and negative edge triggered
flip-flop. Draw the circuit symbol of J-K flip-flop with negative edge
triggered clock input.
16. What is flip-flop ? What is limitation of S-R flip-flop ?
17. Draw the circuit diagram of J-K flip-flop using NAND gates. Explain
the race condition. How to resolve this problem ?
18. How will you get D and T flip-flops from J-K flip-flop ? Draw logic
diagram and truth table of each.
[D] Short Answer Questions:
1. What is flip-flop?
2. List different types of flip-flop.
3. Define role of R and S inputs in RS flip-flop.
4. Explain truth table of RS flip-flop.
5. What do you mean by SET and RESET output of flip-flop.
6. What is race around condition in RS flip-flop.
7. State major drawback of RS flip-flop.
8. ‘D flip-flop can be used as memory device’, elaborate.
9. How we can convert JK flip-flop into T flip-flop?
10. How D flip-flop can be obtained by using RS flip-flop.
11. Draw logic diagram, symbol and write truth table for T flip-flop.
12. What is meaning of TOGGLE when J=1, K=1 in JK flip-flop.

13. State advantage of PRESET and CLEAR in JK flip-flop.
14. How active low PRESET and Clear are indicated?
15. State application of T flip-flop.
16. Define Edge triggered and Level triggered flip-flop.
17. How edge triggered flip-flop is indicated in symbol.
18. Differentiate between D flip-flop and T flip-flop.
19. Differentiate between RS and JK flip-flop.
20. What is Master Slave flip-flop?
21. Define (i) Clock, (ii) Positive edge trigger, (iii) Negative edge trigger.
Answers
[A] True or False :
(1) True (2) True (3) False
(4) False (5) True (6) True
(7) True (8) False (9) True
1. (a) 2. (c) 3. (a) 4. (b) 5. (c) 6. (b) 7. (a)
8. (b) 9. (d) 10. (a)
University Questions
March 2015
1. Draw the logic diagram of R-S flip-flop using four NAND gates and
explain its working.
2. Show a block diagram representation to obtain T flip-flop using J-K
flip-flop.
3. Explain the working of J-K master-slave flip-flop with the help of
block diagram.
March 2016
1. Explain the working of JK flip-flop using NAND gates.
2. What do you understand by edge triggered flip-flop?
March 2017
1. Draw the logic symbol for positive edge triggered D-Flip-Flop and
negative level triggered RS-Flip-Flop.
2. Explain the working of the following circuit.
A
X
Y
B
Fig. 1.13
3. What is race around condition ? Which Flip-Flop exhibits this
condition ? How can race around condition be eliminated ?
October 2017
1. Show the connections required to convert JK flip-flop to D flip-flop
and T flip-flop. Write the truth table for the same.
March 2018
1. With a neat logic diagram explain the working of clocked R-S flip-
flop.
✍✍✍
Unit 2…
Shift Registers and Counters
Charles Eryl Wynn-Williams (5 March 1903 – 30
August 1979), was a Welsh physicist, noted for his
research on electronic instrumentation for use in
nuclear physics. His work on the scale-of-two
counter contributed to the development of the
modern computer. In 1926, he applied his
electronics skills to construct an amplifier using
thermionic valves (vacuum tubes) for very small
electrical currents. It was realized that such
Charles Eryl Wynn- devices could be used in the detection and
Williams counting of Alpha particles in the nuclear
disintegration experiments then being undertaken
by Rutherford, who encouraged him to devote his attention to the
construction of a reliable valve amplifier and methods of registering and
counting particles.
In 1932, Wynn-Williams published details of his thyratron-based
scale-of-two counter, which allowed particles to be counted at much
higher rates than previously. His devices became crucial unifying elements
in the hardware of the emergent discipline of nuclear physics. In digital
logic and computing, a counter is a device which stores and sometimes
displays the number of times a particular event or process has occurred,
often in relationship to a clock. The most common type is a sequential
digital logic circuit with an input line called the clock and multiple output
lines. The values on the output lines represent a number in the binary or
BCD number system. Each pulse applied to the clock input increments or
decrements the number in the counter.
2.1 Introduction
• A flip-flop can store 1-bit of digital information. It is also referred to
as a 1-bit register. A register contains a group of flip-flops, the
number of flip-flops in a register being equal to the number of bits
present in the data.
2.1
F.Y.B.Sc. Electronics (Comp. Sci.) (P-II) 2.2 Shift Registers & Counters
• Flip-flops are connected in such a way that binary number can be

entered into the register and retrieved from the same. A register
capable of shifting its binary information either to the right or to the
left is called a “Shift register”. In this unit we will discuss basic shift
registers, their use in digital circuit applications.
• One of the most versatile subsystems in digital electronics is the
Counter. Counter is basically constructed using flip-flops and is an
example of sequential circuits. Counters count the number of clock
pulses arriving at its input. The output of the counter is binary or the
BCD equivalent of the number of clock pulses applied at its input.
• Depending upon the nature of the output, one way to classify the
counters is the binary counters and the BCD counters.
• Counters are basically useful to count the clock pulses applied at the
input. Since clock pulses occur at known intervals, therefore counter
can be used as an instrument for measuring time and therefore
period or frequency. In this unit, we will also discuss various kinds of
digital counters. Many physical parameters or events can be
converted into pulses and hence counter can be used to indicate
temperature, vibrations etc. or to count events.
2.2 Shift Registers - SISO, SIPO, PISO, PIPO
Shift Registers
• A flip-flop is basically a one-bit storage cell.
• The group of flip-flop that is used to store binary number is called a
register.
• One flip-flop is required to store one-bit and hence a register used to
store a 8-bit binary number must contain 8 flip-flops.
• The flip-flops must be connected such that the binary number can be
entered (shifted) into the register and can be shifted out. A group of
flip-flops connected to provide these functions is called a shift
register.
• A register is normally used for storing and shifting data (‘1’ and ‘0’)
entered into it from an external source and possesses no
characteristic internal sequence of states like that of a counter.
• The data in the register can be loaded serially or in parallel and can
be shifted out either serially or in parallel, which leads to four basic
types of registers.
• Fig. 2.1 shows symbolically the types of data movement in shift
register operation. The block represents an arbitrary four-bit register
and the arrow indicates the direction and type of data movement.
Serial Serial Serial
data data data
input output input
Parallel data output

(a) Serial in serial out (b) Serial in parallel out
shift register shift register
Parallel data input
Parallel data input
Serial
data
output
Parallel data output
(c) Parallel in serial out (d) Parallel in parallel out
shift register shift register
Fig. 2.1
2.2.1 Serial In Serial Out Shift Register
• This type of shift register accepts digital data serially that is one-bit at
a time on a single line. It produces the stored information on its
output also in serial form.
• Serial in serial out shift registers can be implemented either by using
J-K or D flip-flop. Fig. 2.2 shows a 4-bit serial in serial out shift
register using D flip-flop.
QA QB QC QD
Data D D D D Data
input output
FFA FFB FFC FFD
CLK
Fig. 2.2 : Serial in serial out shift register

• Initially, all flip-flops are reset then the data to be entered can be
applied to the D input starting with LSB or MSB.
• Let the data to be entered is 1001 beginning with LSB. The 1 is put on
st
to the data input line, making D = 1 for FFA. When the 1 clock pulse
is applied, FFA is set thus storing 1. Next 0 is applied to the data
input, making D = 0 for FFA and D = 1 for FFB since QA is connected
to D of FFB.
• When the second clock pulse is applied, the 0 on the data input is
shifted into FFA and 1 that was in FFA is shifted into FFB.
• The next 0 in the binary number is now put on to the data line and a
clock pulse is applied. The 0 is entered into FFA. The 0 stored in FFA is
shifted into FFB and 1 stored in FFB is shifted into FFC.
• The last bit in the binary number is 1, which is now applied to the
data input and a clock pulse is applied. This time, the 1 is entered into
FFA, the 0 stored in FFA is shifted into FFB, the 0 stored in FFB is shifted
into FFC and the 1 stored in FFC is shifted into FFD.
• This completes the serial entry of the four-bit number into the shift
register.
• Thus, before the application of the clock pulse,
QA QB QC QD = 0000
it becomes
QA QB QC QD = 1000 after one clock pulse
= 0100 after two clock pulses
= 0010 after three clock pulses
= 0001 after four clock pulses, i.e. serially out
= 0000 after fifth clock pulses, new data to be entered
• Timing diagram for this serial in serial out shift register function is as
shown in Fig. 2.3 below.
1
Data 0 0
input
1 2 3 4 5
Clk
1
0 0 0 0 0
QA
1
0 0 0 0 0
QB
1
0 0 0 0 0
QC
1
0 0 0 0 0
QD
Fig 2.3 : Timing diagram
• Thus, to shift 4-bit data into 4 flip-flop requires four clock pulses.
• If we want to get the data out of the register, they can be shifted out
serially and taken out at the QD output. After CLK4, in the data entry
operation described above, the right most 1 in the number appears
on the QD outputs.
• When CLK5 is applied, the second bit appears on the QD output. CLK6
shifts the third bit to the output and CLK7 shifts the fourth bit to the
output.
• When the stored bits are being shifted out, a new four-bit number
can be shifted in.
• The shift registers are also available in IC forms. The 7491A is an
example of an IC serial in serial out shift register.
2.2.2 Serial In Parallel Out Shift Register
• In this type of register, data bits are shifted in serially but shifted out
in parallel.
• In order to take parallel output, the output of each stage must be
available.
• Once the data is stored, each bit appears on its respective output line
and all bits are available simultaneously.
• Fig. 2.4 shows the 4-bit serial in parallel out shift register.
Data D QA D QB D QC D QD
input
FFA FFB FFC FFD
CLK
QA QB QC QD
Fig. 2.4 : Serial in parallel out shift register

• In this shift register, we can send the bits serially from the Data input
of left most D flip-flop. Hence, this input is also called as serial input.
• For every positive edge triggering of clock signal, the data shifts from
one stage to the next.
• In this case, we can access the outputs of each D flip-flop in parallel.
So, we will get parallel outputs from this shift register with serial input
bit data.
• The IC 74164 is eight-bit serial in parallel out shift register.
• Fig. 2.5 shows timing diagram for serial in parallel shift register
operation.
t1 t2 t3 t4 t5 t6 t7 t8
CLK
Data 1 0 1 1
input
QA 1 0 1 1
QB 1 0 1
QC 1 0
QD 1
Fig. 2.5
• As shown in timing diagram data input is serially at first flip-flop FFA,
1011, which appears at output at same time i.e. parallel output after
clock cycle t4.
• The IC 74164 is eight-bit serial in parallel out shift register.
2.2.3 Parallel In Serial Out Register

• In this case, data bits are entered simultaneously into their respective
stages.
• Once the data is completely stored in the register, it can be shifted
serially out, one-bit at a time using clock pulses.
• Fig. 2.6 shows the four-bit parallel in serial out shift register.
Parallel input
DA = 1 DB = 0 DC = 0 DD = 1
Enable
PE
G1 G2 G3 G4
S S S S
Logic 0 DIN QA DIN QB DIN QC DIN QD Serial
output
Q Q Q Q
R R R R
Reset
Clock
Fig. 2.6 : A four-bit parallel in serial out shift register
• There are four data inputs DA, DB, DC, DD and a parallel enable line
which allows four bits of data to be entered in parallel into the
register.
• When PE line is high, gates G1 through G4 are enabled which allow
each data bits to be applied to the D inputs of respective flip-flops.
• When a clock pulse is applied, the flip-flops with a 1 data bit will set
and those with 0 data bit will reset.
• Thus, it stores the data word in one clock cycle i.e. storing all four bits
simultaneously.
• When the PE line is low, parallel data input gates G1 through G4 are
disabled.
• Fig. 2.7 shows timing diagram for parallel in serial output shift
register.
CLK
0 0 1 1 1
Parallel input DA
data DB 0 1 0 1 0
DC 1 1 1 0 1
DD
1 0 0 1 1
PE
output
Serial
0 1 1 0 0 1
QD
Fig. 2.7
• At next clock pulse parallel in data 1001 is at output QD.
• As shown in timing diagram parallel data input is 1100 which appears
as serial output at QD, as soon as the parallel data is uploaded then
for each clock cycle serial data is out.
• The IC 74165 is an example of parallel in serial out on an IC shift
register.
2.2.4 Parallel In Parallel Out Register
• In parallel in parallel out shift register, data bits are entered
simultaneously as well as taken out simultaneously.
• Fig. 2.8 shows parallel in parallel out shift register.
D3 D2 D1 D0
D Q
Q33 D Q
Q32 D Q
Q31 D Q
Q30
CK CK CK CK
CLK
Q3 Q2 Q1 Q0
Fig. 2.8 : Parallel in parallel out shift register
• The data to be entered is applied to the data inputs of the respective
flip-flop.
• After applying the clock pulse data gets stored in the respective flip-
flop and also appears at the output from where it can be read
simultaneously.
• Fig. 2.9 shows timing diagram for parallel in parallel output shift
register.
CLK
D3 0
1 1 1 1
D2
Input
0 1 0 1 0
D1 1 1 1 0 1
D0 0
0 0 0 1
Q3 0 1 0
Output
Q2 0 0 1
Q1 0 1 1
Q0 0 0 0
Fig. 2.9
• As shown in timing diagram parallel input data is at D3, D2, D1, D0 i.e.
1010 and corresponding parallel output data is at Q3, Q2, Q1, Q0 at
the end of third clock pulse.
• The IC 74195/198 is an example of parallel in parallel out shift
register.
2.3 Ring Counter Using D Flip-Flop
• A shift register can be modified into a counter by connecting the
serial output back to the serial input. It is known as the ring counter
because it exhibits a specified sequence of states.
• A logic diagram for a four-bit ring counter is shown in Fig. 2.10.
Pr
D QA D QB D QC D QD
FFA FFB FFC FFD
CLK
Cr
Fig. 2.10 : 4-bit ring counter
• Instead of counting in binary mode, the ring counter rotates the bit
among the flip-flop.
•
st
To begin with, a 1 is preset into the 1 flip-flop and the remaining
flip-flops are cleared.
•
st
When 1 clock pulse is applied, 1 is shifted from QA to QB.
•
nd
When 2 clock pulse is applied, 1 is further transferred from QB to QC
and so on.
• 1 is always retained in the counter and simply shifted around the ring
advancing one stage for each clock pulse.
• Table 2.1 shows the ring counter sequence.
Table 2.1 : Ring counter sequence
Clock
QA QB QC QD
pulse
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
Fig. 2.11 shows the waveforms for 4-bit ring counter.
Fig. 2.11 : 4-bit ring counter waveforms

Uses of Ring Counters:
In case of a ring counter, the stored bit follows a circular path and
hence it is very useful in timing sequence of digital operation.
Hence, it is used to control a sequence of operation, stepper motor
control, state counters, divide by N counter where N is number of clock
pulses.
2.4 Counters - Synchronous and Asynchronous

Type
• Asynchronous counter : A type of counter in which each stage is
clocked from the output of the preceding stage.
• Synchronous counter : A type of counter in which each stage is

clocked by the same pulse.
2.4.1 Asynchronous Counter

• If the output of a counter is proportional to the binary equivalent of
number of clock pulses applied at its input, it is known as binary
counter.
• Fig. 2.12 shows the circuit of 4-bit binary counter.
• As seen, it is obtained by cascading the flip-flops such that output of

previous flip-flop is connected to the clock input of the next flip-flop.
+ VCC
J QA J QB J QC J QD
FFA FFB FFC FFD
CLK
K K K K
CLR
QA QB QC QD
Fig. 2.12 : 4-bit binary counter
• Note that, the output of A flip-flop drives the B flip-flop. B flip-flop

drives the C flip-flop and C flip-flop drives the D flip-flop.
• The J and K inputs of all flip-flops are connected to VCC, i.e. J-K flip-
flop is converted to T type in which each flip-flop changes the state
with a negative transition of its clock input.
• When clock pulse is applied and it goes negative, flip-flop A changes

the state.
• A flip-flop has to change the state to trigger B flip-flop. B has to

change the state before it can trigger C. C has to change the state
before it can trigger D. Hence, the trigger moves through the flip-
flops like a ripple in water.
• The counters in which output of one flip-flop drives the another are
called as ripple counters or asynchronous counters.
• In working of asynchronous counter before application of any

clock pulse, initially all flip-flops are reset to produce the output
DCBA = 0000.
• All flip-flops can be reset by applying clear pulse simultaneously to all
flip-flops.
• When the first clock pulse is applied, flip-flop A changes its state on
the negative going part of the pulse. Flip-flop A output goes from
logic 1 to 0 which is positive change and hence flip-flop B does not
responds to it. Since flip-flop B has not changed its state, flip-flop C
will not change its state and since C has not changed, D will not
change. So at the end of first clock cycle, the output condition is
DCBA = 0001.
• When the second clock pulse is applied, flip-flop A changes its state
at the negative edge of pulse and A flip-flop output goes from 1 to 0,
a negative change. This negative going change triggers the B flip-
flop, therefore, B goes from 0 to 1. This positive going change in B
has no effect on C, since C has not changed, no change in D flip-flop.
So at the end of second clock pulse, the output condition of four flip-
flops is DCBA = 0010.
• When the third clock pulse is applied, flip-flop A changes its state
from 0 to 1; this is positive going change and has no effect on the B
flip-flop. B has not changed and hence C and further D will not
change. So at the end of third clock pulse, the output condition of
four flip-flops is DCBA = 0011.
• Thus, we can see that the output condition of four flip-flops is binary
equivalent of number of clock pulses applied at its input.
• Table 2.2 shows the truth table of 4-bit binary counter.
Table 2.2
Clock pulses D C B A
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0 ← Reset
17 0 0 0 1 ← Recounting
• Since the circuit gives the output which is binary equivalent of
counter.
•
th
At the end of 15 clock pulse, flip-flop's output is DCBA = 1111 and
th
the circuit counts upto maximum of 15. When 16 clock pulse is
applied, A goes from 1 to 0, a negative going change. This causes B
to go from 1 to 0, another negative going change, this forces C to go
from 1 to 0. This negative going change causes D to go from 1 to 0,
so the entire counter resets and the output condition of flip-flop
th
becomes DCBA = 0000. When 17 clock pulse is applied, counter
starts recounting. Fig. 2.13 shows the waveforms associated with 4-bit
binary counter of Fig. 2.12.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Clock
1 2 3 4 5 6 7 8
QA
QB
QC
QD
Fig. 2.13 : Waveforms of 4-bit binary counter
• From the waveforms, we see that the waveform at QA is one half the
frequency of clock, at QB frequency is one fourth of the clock
frequency, at QC one eighth of the clock frequency and at QD one
sixteenth of the clock frequency. Thus, counter is also a frequency
divider.
2.4.2 Synchronous Counter
• The ripple counters are simple to build, but they cannot be operated
by high frequency signal.
• Since each flip-flop has a delay time, in a ripple counter these delay
times are additive and the total settling time for the counter is
approximately the delay time of the total number of flip-flops. If each
flip-flop has a propagation delay of 10 ns, overall delay for 4-bit
counter becomes 40 ns.
• This speed limitation can be overcome by the use of synchronous or
parallel counter.
• Here every flip-flop is triggered by the clock and hence they all make
their transitions simultaneously and hence known as synchronous or
parallel counter.
• Fig. 2.14 shows the logic diagram, truth table and the timing diagram
of mod 8 synchronous counter.
+ VCC
J QA J QB J QC
Clock
FFA G0 FFB G1 FFC
K K K
QA QB QC
(a) Logic diagram
C B A Count
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
0 0 0 0
(b) Truth table
(c) Timing diagram

Fig. 2.14 : Synchronous counter
• The parallel counter is constructed using J-K flip-flop with negative
edge triggering. The flip-flop A changes the state with each negative
transition at the clock input.
• The output of AND gate G0 goes high whenever the clock is high and
QA is high. Thus, flip-flop B changes the state whenever QA is high
and clock goes negative. The output of AND gate G1 goes high when
the clock is high and both QA and QB is high. Thus, flip-flop C changes
its state when both QA and QB is high and clock goes negative.
• From the Fig. 2.14 (c) we see that QA changes the state after every
clock pulse, QB changes the state with every other clock pulse and
flip-flop C changes the state with every fourth clock pulse and hence
the circuit represents mod 8 counter.
• The parallel counter shown in Fig. 2.14 is the basic building block for
building counters of other moduli.
• If we have to build mod 16 parallel counter, we require 4 flip-flops

and one more 4 input AND gate.
• Whereas if we have to construct a mod 7 counter, it is necessary to
eliminate the one state from the natural count sequence of mod 8
counter.
• One way to skip the last state is to use a feedback connection as we
have seen previously and generate the clear pulse to clear the flip-
flop earlier.
• We can also skip the first state. If by some means we prevent flip-flop
A being reset during the transition from count 7 to count 0, without
affecting the operations of B and C, the counter would progress from
count 7 to count 1.
• Thus, count 0 would be skipped and a mod 7 counter would be
formed.
• Fig. 2.15 shows the logic diagram, truth table and waveforms of the
mod 7 synchronous counter.
+ VCC
J QA X J QB Y J QC
Clock
FFA FFB FFC
K K K
(a) Logic diagram of mod 7 synchronous counter

C B A Count
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
0 0 1 1
(b) Truth table
(c) Waveforms
Fig. 2.15 : Mod 7 synchronous counter
• For the logic diagram shown in Fig. 2.15 (a), counter advances by its
natural sequence upto count 7.
• During the count, output of all flip-flops is high and since they are
connected to input of NAND, it will generate low output which in
turn holds K low.
• When the next clock pulse is applied, since J = 1, K = 0 which does
not changes the stage of flip-flop A and hence output of the counter
goes from 111 to 001 state skipping 000 state. In turn the circuit
becomes the mod 7 counter.
• Thus, basically two types of counters can be designed and are also
available in the market. Depending upon the requirement and the
physibility, user has to select the type of the counter.
• The points of difference between synchronous and asynchronous
counters are as given below.
Synchronous (parallel) counter Asynchronous (ripple) counter
1. Every flip-flop is triggered by 1. The clock pulse is applied to
the clock in synchronism. the clock input of first flip-
Therefore, they make their flop only. Each flip-flop is
transitions simultaneously. triggered by the output of
previous flip-flop.
2. Setting time is less and is equal 2. Setting time is more and is
to the delay time of the single equal to the sum of
flip-flop. propagation delay times of
total number of flip-flops.
… (Contd.)
Synchronous (parallel) counter Asynchronous (ripple) counter

3. Speed of operation is more and 3. Speed of operation is limited,
can be activated by high clock the highest clock frequency
frequency. depends on overall delay in
the system.
4. Circuit is complex, more 4. Simple circuit, easy to build,
hardware is required and hence less hardware is required and
it cost more. hence cost is less.
2.5 3-bit Up, Down and Up-Down Counter

2.5.1 3-Bit Up, Down Counter
• The counters we have studied in above are also known as up
counters, since upon receiving the next clock pulse, the content of
counter increases by one. The count sequence of such counters are
0, 1, 2, 3, …, n. Similarly, we can have down counter with n, n − 1,
n − 2 … 0 with corresponding clock pulses. Now we discuss these in
detail.
2.5.1.1 Up Counter
• Fig. 2.16 below shows 3-bit up counter using cascading of three
flip-flops.
High
J Pr Q Q0 J Pr Q Q1 J Pr Q Q2
CLK
K Q K Q K Q
Cr Cr Cr
FF0 FF1 FF2
Fig. 2.16 : 3-bit up counter
• In asynchronous up counter, a clock pulse drives FF0. Output of FF0
drives FF1 which then drives the FF2 flip-flop. All J and K inputs are
connected to Logic 1. Therefore, each flip-flop will toggle with
negative transition at its clock input.
• When the first clock pulse is applied, the FF0 changes state on its
negative edge. Therefore, Q2Q1Q0 = 001.
• On the negative edge of second clock pulse flip-flop FF0 toggles. Its
output changes from 1 to 0. This being negative change, FF1 changes
state. Therefore, Q2Q1Q0 = 010.
• Similarly, the output of flip-flop FF2 changes only when there is
negative transition at its input when fourth clock pulse is applied.
• The output of the flip-flops is a binary number equivalent to the

number of clock pulses received. The output conditions are as shown
in the truth table.
Counter State Q0 Q1 Q2
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
• Timing diagram for up counter is as shown in Fig. 2.17 below.
1 1 2 3 4 5 6 7 8
CLK 0
1
Q0 0
1
Q1
0
1
Q2 0
0 1 2 3 4 5 6 7 8
Fig. 2.17 : Timing diagram
2.5.1.2 Down Counter
• It is sometimes useful to have counter which can count in downward
sequence i.e. the count sequence is n, n − 1, n – 2, …, 1, 0. Upon
receiving the next clock pulse if the content of counter decreases
then it is known as down counter.
+ VCC
Pr Pr Pr
J QA J QB J QC
CLK FFA FFB FFC
K QA K QB K QC
Cr Cr Cr
Fig. 2.18 : 3-bit down counter
• Fig. 2.18 shows the circuit of 3-bit down counter.

• The 3-bit down counter is obtained using 3 flip-flops, the system
clock is still applied at flip-flop A.
– –
• The QA is used to drive flip-flop B and QB is used to drive flip-flop C.
• Initially all flip-flops are reset by applying clear pulse simultaneously
to all flip-flops.
• When the 1st clock pulse is applied, flip-flop A toggles at negative
edge of the pulse and QA becomes 1.
–
• As QA goes from 0 to 1, QA goes from 1 to 0 which is negative change
–
and it triggers flip-flop B causing QB to go from 0 to 1, QB from 1 to 0
which is negative change and it further triggers flip-flop C.
• So at the end of 1st clock pulse, the output condition of three flip-
flops is
QC QB QA = 111
•
nd
When 2 clock pulse is applied at the negative edge, flip-flop A
–
toggles, QA output goes from 1 to 0, QA goes from 0 to 1 which is
positive change and it does not affects flip-flop B. Since flip-flop B
nd
has not changed, C will not change, so at the end of 2 clock pulse,
QC QB QA = 110
• When 3rd clock pulse is applied, the output condition of the flip-flop
will be QC QB QA = 101 and so on i.e. after receiving next clock pulse,
content of counter decreases by one i.e. the down counter.
• Table 2.3 gives the truth table of 3-bit down counter.
Table 2.3
Count QC QB QA – – – ––––––
QC QB QA Count
7 1 1 1 0 0 0 0
6 1 1 0 0 0 1 1
5 1 0 1 0 1 0 2
4 1 0 0 0 1 1 3
3 0 1 1 1 0 0 4
2 0 1 0 1 0 1 5
1 0 0 1 1 1 0 6
0 0 0 0 1 1 1 7
Fig. 2.19 shows the waveforms associated with 3-bit down counter.
1 2 3 4 5 6 7 8
Clock
1 2 3 4
QA
QB
QC
Fig. 2.19 : Waveforms of 3-bit down counter

• Thus, the count sequence - up or down depends upon how the flip-
flops are connected.
• If we connect Q output to the clock input of next, it becomes up
–
counter whereas if we connect Q to clock input of next, it becomes
down counter.
2.5.1.3 Up-Down Counter
• In previous section we have studied separate circuits for up counter
and down counter.
–
• Using some gating circuitry, it is possible to connect either Q or Q at
the clock input of next flip-flop and hence a single circuit can be used
as either up counter or down counter. Such circuit which can be used
as up counter or down counter is known as up-down counter.
• Fig. 2.20 shows the circuit for 3-bit asynchronous up-down counter.
+ VCC
Count up
J QA J QB J QC
Clock
FFA FFB FFC
K QA K QB K QC
Count
down
(a) 3-bit up-down counter

(b) Waveforms of up counter
(c) Waveforms of down counter

Fig. 2.20
• When the count up is held high and count down low, Q output of
previous flip-flop gets connected to the clock input of next flip-flop
and the circuit will behave as the up counter.
–
• Whereas when count up is held low and count down high, Q output
of previous flip-flop gets connected to the clock input of next flip-
flop and the circuit behaves as the down counter and causes the
counter to progress through the count down sequence.
2.6 Concept of Modulus Counters
• The binary ripple counter can be constructed using clocked J-K flip-
flop.
• The total number of counts or discrete states through which the
counter can progress is given by 2n, where n is the total number of
flip-flops. Then it is said to have natural count of 2n.
• A basic binary counter consisting of three flip-flop counts through
eight discrete states is said to have natural count of 8.
• The 4-bit binary counter contains 4 flip-flop counts through 16 states.

• Thus, we can construct counters which count through 2, 4, 8, 16 …
etc. states by using proper number of flip-flops. A 3 flip-flop counter
is often referred to as a modulus 8 counter since it has 8 states.
• The modulus of a counter is the total number of states through which
the counter can progress.
• It is often desirable to construct counters which have moduli other
than 2, 4, 8, …, etc. e.g. we may need to construct a counter having
modulus 3 or 5 or 7.
• A smaller modulus counter can always be constructed from a larger
modulus counter by skipping states. Such counters are said to have a
modified count.
• The number of flip-flops required to construct desired counter is
determined by choosing the lowest natural count which is greater
than the desired modified count.
• For example, mod 7 counter requires 3 flip-flops since lowest natural
count greater than 7 is 8 which requires 3 flip-flops.
• A mod 9 counter requires atleast 4 flip-flops since 16 is the lowest
natural count greater than 9 and requires 4 flip-flops.
• Generally, method used to skip count is to feedback a signal from
some flip-flop to some previous flip-flop. e.g. consider a designing of
mod 7 counter. It requires 3 flip-flops and since only one count is to
be skipped, it would be convenient to let the counter advance
through its natural sequence and then reset it one count early.
• Fig. 2.21 shows the logic diagram, truth table and waveforms of mod
7 counter.
+ VCC
J QA J QB J QC
CLK
FFA FFB FFC
K K K
QC
QB
QA
(a) Logic diagram

QC QB QA Count
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
0 0 0 Reset
(b) Truth table
1 2 3 4 5 6 7
CLK
QA
QB
QC
CLR
(c) Waveforms
Fig. 2.21
• From the truth table of natural 3-bit counter, we know that count 7
(111) occurs only once.
• If QA, QB and QC outputs are connected to 3 input of 3 input NAND
gate, the output of NAND gate goes low only when QA = QB = QC =
1.
• If the output of the NAND gate is connected to the CLR input of each
flip-flop all the flip-flops will be cleared to zero's immediately as the
counter advances to count 7.
• The counter remains in state 7 only momentarily, therefore, it is a
mod 7 counter.
Think Over It
• List practical applications of shift registers and counters.

• The counters are mainly used in counting applications, where
they either measure the time interval between two unknown
time instants or measure the frequency of a given signal, what
will be application of ring counter?
• Refer to Data manual of digital IC’s, find out shift register IC and
their specifications.
Summary
1. The group of flip-flop that is used to store binary number is called a
register.
2. The flip-flops must be connected such that the binary number can be
entered (shifted) into the register and can be shifted out. A group of
flip-flops connected to provide these functions is called a shift
register.
3. A register is normally used for storing and shifting data (1s and 0s)
entered into it from an external source and possesses no
characteristic internal sequence of states like that of a counter.
4. Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and
“OUT” of the register, one bit at a time in either a left or right
direction under clock control.
5. Serial-in to Parallel-out (SIPO) - the register is loaded with serial
data, one bit at a time, with the stored data being available at the
output in parallel form.
6. Parallel-in to Serial-out (PISO) - the parallel data is loaded into the
register simultaneously and is shifted out of the register serially one
bit at a time under clock control.
7. Parallel-in to Parallel-out (PIPO) - the parallel data is loaded
simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.
8. Asynchronous counter : A type of counter in which each stage is
clocked from the output of the preceding stage.
9. Synchronous counter : A type of counter in which each stage is
clocked by the same pulse.
10. A shift register can be modified into a counter by connecting the

serial output back to the serial input. It is known as the ring counter
because it exhibits a specified sequence of states.
11. A digital 1 is always retained in the ring counter which is simply
shifted around the ring advancing one stage for each clock pulse.
12. If the output of a counter is proportional to the binary equivalent of
counter.
13. The counters in which output of one flip-flop drives the another are
called as ripple counters or asynchronous counters.
14. The ripple counters are simple to build, but they cannot be operated
by high frequency signal.
15. A ripple counter has additive delay times. The total settling time for
the counter is approximately the delay time of the total number of
flip-flops used in it.
16. The total number of counts or discrete states through which the
n
counter can progress is given by 2 , where n is the total number of
n
flip-flops. Then it is said to have natural count of 2 .
17. The 4-bit binary counter contains 4 flip-flop counts through 16 states.
18. Up counter and down counter is combined together to obtain an
UP/DOWN counter.
19. Up/down counter counts both up and down, under command of a
control input.
20. The number of flip-flops required to construct desired counter is
determined by choosing the lowest natural count which is greater
than the desired modified count.
21. Application of counters are Frequency counters, Digital clock, Time
measurement, A to D converter, Frequency divider circuits, Digital
triangular wave generator.
Exercise
[A] True or False :
1. A counter circuit is usually constructed of a number of flip-flops
connected in cascade.
2. In, parallel in to parallel out register the parallel data is loaded
simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.
3. Ripple counters are also called synchronous counter.
4. BCD counter is also known as decade counter.

5. There will be 16 natural states in a 4-bit ripple counter.
6. Shift registers are basically a type of register which have the ability to
transfer or shift data.
7. A Parallel in Serial out shift register is used to convert parallel data to
serial data.
8. The speed of ripple counter is limited by the propagation delay of all
flip-flops and gates.
9. Low-frequency applications of asynchronous counters are limited
because of internal propagation delays.
10. In an UP-counter, each flip-flop is triggered by the normal output of
the preceding flip-flop.
11. A decimal counter has 10 states.
12. A ring counter with 5 flip flops will have 5 states of counting.
1. Asynchronous counters are known as ……
(a) ripple counters (b) multiple clock counters
(c) decade counters (d) modulus counters
2. Asynchronous counter differs from an synchronous counter in ……
(a) the number of states in its sequence
(b) the method of clocking
(d) the type of flip-flops used
(d) the value of the modulus
3. A 4-bit binary counter has a maximum modulus of ……
(a) 16 (b) 32
(c) 8 (d) 4
4. The BCD counter is an example of ……
(a) a full-modulus counter (b) a decade counter
(c) a truncated-modulus counter (d) both (b) and (c)
5. A stage in a shift register consists of ……
(a) a flip-flop (b) a word of storage
(c) a byte of storage (d) four bits of storage
6. To serially shift a byte of data into a shift register, there must be ……
(a) one clock pulse
(b) one load pulse
(c) eight clock pulses
(d) one clock pulse for each 1 in the data
7. To parallel load, a byte of data into shift register with a synchronous

load, there must be ……
(a) one clock pulse
(b) one clock pulse for each 1 in the data
(c) eight clock pulse
(d) one clock pulse for each 0 in the data
8. A ripple counter's speed is limited by the propagation delay of ……
(a) each flip-flop (b) all flip-flops and gates
(c) the flip-flops only with gates (d) only circuit gates
9. To operate correctly, starting a ring counter requires ……
(a) clearing all the flip-flops
(b) presetting one flip-flop and clearing all the others
(c) clearing one flip-flop and presetting all the others
(d) presetting all the flip-flops
10. Mod-6 and Mod-12 counters are most commonly used in ……
(a) frequency counters (b) multiplexed displays
(c) digital clocks (d) power consumption meters
11. Synchronous counters eliminate the delay problems encountered
with asynchronous (ripple) counters because the ……
(a) input clock pulses are applied simultaneously to each stage
(b) input clock pulses are applied only to the first and last stages
(c) input clock pulses are applied only to the last stage
(d) input clock pulses are not used to activate any of the counter
stages
12. One of the major drawbacks to the use of asynchronous counters is
that ……
(a) low-frequency applications are limited because of internal
propagation delays
(b) high-frequency applications are limited because of internal
propagation delays
(c) Asynchronous counters do not have major drawbacks and are
suitable for use in high- and low-frequency counting
applications.
(d) Asynchronous counters do not have propagation delays, which
limits their use in high-frequency applications
13. What type of register would shift a complete binary number in one
bit at a time and shift all the stored bits out one bit at a time?
(a) PIPO (b) SISO
(c) SIPO (d) PISO
14. A ripple counter's speed is limited by the propagation delay of ……

(a) each flip-flop (b) all flip-flops and gates
(c) the flip-flops only with gates (d) only circuit gates
15. How many flip-flop circuits are needed to divide by 8 ?
(a) three (b) four
(c) eight (d) sixteen
16. A counter driven by clock can be used to count number of ……
(a) clock cycles (b) digits
(c) propagation delay (d) none of any
17. A mod 8 counter will count ……
(a) from 0 to 7 (b) from 0 to 3
(c) from any number n to n + 4 (d) none of above
18. A counter has modulus of 10. The number of flip-flops are ……
(a) 1 (b) 2
(c) 4 (d) 8
19. In a ripple counter ……
(a) whenever a flip-flop sets to 1,the next higher FF toggles
(b) whenever a flip-flop sets to 0, the next higher FF remains
unchanged
(c) whenever a flip-flop sets to 1, the next higher FF faces race
condition
(d) whenever a flip-flop sets to 0, the next higher FF faces race
condition
20. The number of flip-flops needed for Mod 5 counter are ……
(a) 7 (b) 5
(c) 1 (d) 3
21. A counter is a ……
(a) Combinational circuit
(b) Sequential circuit
(c) Both combinational and sequential circuit
(d) None of above
22. The basic shift register operations are ……
(a) SIPO (b) PISO
(c) SISO (d) All of the above
23. SISO stands for ……
(a) Serial in series out (b) Serial in serial out
(c) Serial in series out (d) Serial in serial out
24. Synchronous counter is more faster than Asynchronous counter ……

(a) Reset pin is high
(b) Common clock applied
(c) Clock pulse applied for only first flip-flop
(d) None of these
1. What is meant by asynchronous counter ? State its limitation.
2. What is meant by synchronous counter ? State its advantages and
disadvantages over asynchronous counter.
3. What do you mean by down counter ? Write the count sequence of
3-bit down counter.
4. Draw the circuit, truth table and waveforms of 4-bit binary counter.
5. Draw the circuit of 3-bit up-down counter. Explain its action.
6. Define the term modulus of a counter. How many flip-flops will be
required to obtain mod 12 counter ?
7. Draw the circuit diagram of a 3-bit synchronous counter. Explain its
operation.
8. State the different applications of the counter.
9. What do you mean by a shift register ? Explain in brief with example.
10. Explain the operation of serial in serial out shift register with suitable
circuit.
11. Draw the circuit diagram and explain the working of parallel in serial
out shift register.
12. Explain the operation of ring counter. State its application.
13. How many flip-flops are required to construct a shift register which
can store decimal 100 ?
14. Describe how we can use shift register to multiply and divide a binary
number.
15. For a 4-bit serial in parallel out shift register, draw a timing diagram
to show shifting of data 0111 into it. Assume that register initially
contains all 0's.
16. State the different applications of shift register.
17. Describe how shift registers are used in time delay generation and in
interfacing applications.
18. Draw the circuit diagram of 3-bit up/down counter. Explain its action
with state table and timing diagram.
19. Compare synchronous and asynchronous counters. State different
applications of counter.
20. What do you mean by modulus of a counter ? Construct mod-7

counter. Show logic diagram, timing diagram and count sequence.
21. For 4-bit shift register, explain the operation of serial in serial out
mode with logic circuit and timing diagram. Assume suitable 4-bit
data.
22. Draw logic diagram of shift register as ring counter. Explain its action.
23. Draw logic diagram of up-down counter. Explain its working.
1. What do you mean by shift register?
2. State different applications of shift register.
3. What is synchronous counter ?
4. Why synchronous counters works at a higher speed?
5. State different modes of operation of shift register.
6. Which type of flip-flop is used at the first stage of shift register?
7. Why synchronous counters are faster in operation?
8. What are four modes of shift register?
9. Draw logic diagram of SISO shift register.
10. What is ring counter ?
11. Define up/down counter.
12. What are the number of states in ring counter?
13. How the counters are normally incremented ?
14. Define ripple counter.
15. State any two major differences between synchronous and
asynchronous counter.
Answers
[A] True or False :
(4) True (5) True (6) True
(7) True (8) False (9) False
1. (d) 2. (b) 3. (a) 4. (b) 5. (a) 6. (d) 7. (a) 8. (a)
9. (b) 10. (c) 11. (a) 12. (b) 13. (b) 14. (a) 15. (b) 16. (a)
17. (a) 18. (c) 19. (b) 20. (d) 21. (b) 22. (c) 23. (b) 24. (b)
March 2015
1. Define counter.
2. What is a shift register? List the types of shift registers. Explain the
working of 3 bit serial in serial out register for shifting the data to the
right.
March 2016
1. Explain the working of 3-bit ring counter.
2. Explain the working of 3-bit asynchronous up counter. Draw the
timing diagram.
3. Find the time required to shift 4-bit data through a 4-bit PISO shift
register if the clock frequency is 1 MHz.
March 2017
1. What do you mean by modulus of a counter ?
2. With neat diagram explain working of 3-bit left shift serial in serial
out shift register.
3. Explain working of 3-bit asynchronous down counter.
October 2017
1. Mention why synchronous counters are faster than asynchronous
counter?
2. With neat logic diagram explain the working of 3-bit parallel in
parallel out shift register.
3. Explain the working of 3-bit synchronous up counter with suitable
logic diagram. Draw the timing diagram for the same.
March 2018
1. Mention any two applications of shift registers.
2. Find the time required to load 8-bit data serially in a register if the
duration of clock pulse is 10 sec.
3. Explain the working of 3-bit asynchronous up counter with suitable
logic diagram. Draw the timing diagram for the same.
4. With the help of neat logic diagram explain the working of 3-bit
serial-in-serial out right shift operation.
✍✍✍
Unit 3…
Basics of Computer System
Frederick Phillips "Fred" Brooks Jr. (born April
19, 1931) is an American computer architect,
software engineer, and computer scientist, best
known for managing the development of IBM's
System/360 family of computers and the OS/360
software support package. He born in Durham,
North Carolina, attended Duke University,
graduating in 1953 with a Bachelor of Science
degree in physics, and he received a Ph.D. in
Fredrick Phillips applied mathematics (computer science) from
“Fred” Brooks Jr. Harvard University in 1956.
He served as the graduate teaching assistant for Ken Iverson at
Harvard's graduate program in "automatic data processing", the first such
program in the world. Few years after leaving IBM he wrote ‘The Mythical
Man-Month’. The seed for the book was planted by IBM's then-CEO
Thomas Watson Jr., who asked in Brooks's exit interview why it was so
much harder to manage software projects than hardware projects. In this
book Brooks made the now-famous statement, "Adding manpower to a
late software project makes it later." This has since come to be known as
Brooks's law. In 2004 in a talk at the Computer History Museum and also
in 2010 interview in Wired magazine, Brooks was asked "What do you
consider your greatest technological achievement?" According to him the
great decision was that to change the IBM 360 series from a 6-bit byte to
an 8-bit byte, thereby enabling the use of lowercase letters. His
contributions to human–computer interaction are described in Ben
Shneiderman's HCI pioneers website.
3.1 Introduction
• Nowadays computer is very essential tool in every applications,
Computer technology made several important impacts on our society
and life. This includes Home applications in personal use, Business,
Education, Health, Medicine, Science and technology, Banking sector,
Entertainment, Industrial applications, Engineering, Defense, Desk top
3.1
F.Y.B.Sc. Electronics (Comp. Sci.) (P-II) 3.2 Basics of Computer System
publishing, Communication, Astronomy, Weather broadcasting and

many more applications where computers are used. Hence, any
professional in any field of computing should not regard the
computer as just a instrument which executes programs by
electronics.
• All students of computing should acquire some understanding and
appreciation of a computer system’s functional components, their
characteristics, their performance, and their interactions.
• Students need to understand computer architecture in order to make
best use of the software tools and computer languages they use to
create programs. Also, reasons for studying computer architecture for
computer graduate student are to select the most cost effective
computer for his personal use or for an organization, an
understanding of the implications of spending more for various
alternatives, such as a larger cache or a higher processor clock rate, is
essential to making the decision.
• Another most important application of processors is application in
embedded systems.
• A designer may program a processor in C language that is embedded
in some real-time or larger system. Debugging the system may
require the use of a logic analyzer that displays the relationship
between interrupt requests from engine sensors and machine level
code. Concepts used in computer architecture are also useful in other
areas also.
• In this unit, we are discussing basic computer organization, concept
of Address Bus, Data Bus, Control Bus, CPU Block Diagram and
Explanation of each block, Register based CPU organization, Concept
of Stack and its organization and I/O organization, Need of interface,
Block diagram of general I/O interface etc .
3.2 Basic Computer Organization
• In describing computers, a distinction is often made between
computer architecture and computer organization.
• Computer architecture refers to those attributes of a system visible to
a programmer or, put another way, those attributes that have a direct
impact on the logical execution of a program.
• Computer organization refers to the operational units and their
interconnections that realize the architectural specifications.
• Examples of architectural attributes include the instruction set, the

number of bits used to represent various data types (e.g., numbers,
characters), I/O mechanisms, and techniques for addressing memory.
• Organizational attributes include those hardware details transparent
to the programmer, such as control signals; interfaces between the
computer and peripherals; and the memory technology used.
3.3 Hardwired and Microprogramming Control
Unit
• CPU consists of register set, ALU and control unit. The register set is
used for storage and ALU for processing or operation. The control
unit controls the operations of the CPU. It is also known as Timing
and Control Unit because it controls the operations by using a master
clock.
• The master clock is applied to all the flip-flops and registers in the
system, including the flip-flops and registers in the control unit.
• The control signals are generated in the control unit and provide
control inputs for the multiplexers in the common bus, control inputs
in registers and micro-operations for the accumulator.
• There are two types of control organisation : hardwired control and
micro-programmed control. In the hardwired organisation, the
control is implemented using flip-flops, gates, decoders and other
digital circuits.
• In the micro-programmed organisation, control information is stored
in the control memory. The control memory is programmed to
initiate the sequence of micro-operations.
• In hardwired control, if the design is to be modified, the complete
wiring among various components is changed. In micro-programmed
control, required changes can be done by simply changing the micro-
program in the control memory. We will discuss both the control
organisations in the following sections.
3.3.1 Hardwired Control Unit
• In this method the control unit is implemented using various digital
circuits. There are three methods of designing the control units :
1. The state table method
2. Sequence counter method
3. Delay element method.
• The first method uses state table and state diagrams for the control
unit. This method minimises the number of gates and flips-flops
used. The second and third method derive a logic circuit from the
flowchart or description of control unit behaviour. This approach is
much easier, but the number of gates and flip-flops may not be
minimum. We will discuss all the three methods below.
3.3.1.1 State Table
• The control unit designed by this method is normally consist of
sequential circuit. A sequential circuit is an interconnection of flip-
flops and gates. A combinational circuits consists of a combination of
gates.
• When a combinational circuit is combined with flip-flops, the circuit is
classified as sequential circuit. The Fig. 3.1 shows a block diagram of a
clocked sequential circuit. The combinational circuit receives the
binary signals from external inputs and from the outputs of flip-flops.
• The outputs of combinational circuits goes to external outputs and to
inputs of the flip-flops. The outputs of flip-flops are applied to
combinational circuit input and determine's the circuit behaviour.
Inputs Combinational
Outputs
logic circuit
Flip-Flops
Clock
Fig. 3.1 : Block diagram of a sequential circuit

• A state table relates outputs and next states as a function of inputs
and present state. A transition from present state to next state is
activated by the presence of clock signal.
• A state diagram represents graphically the behaviour of a sequential
circuit. In a state diagram, a state is represented by circle, and
transition is represented by directed lines connecting the circles.
• Let us consider an example to demonstrate the design of sequential
circuit. A clocked sequential circuit is needed that goes through a
repeated sequence of binary states 00, 01, 10 and 11 when external
input say x = 1. The state of circuit remains unchanged when x = 0.
This circuit is called 2-bit binary counter because, the state sequence
is identical to the count sequence of two binary digits.
• The input x is the control variable that specifies, When the count
should begin. The state diagram is shown in Fig. 3.2.
x=0
00
x=1
x=0 01 11 x=0
x=1 x=1
10
x=0
Fig. 3.2 : State diagram for binary counter
• The diagram shows that the circuit follows a binary count when x = 1.
The state remains unchanged when x = 0. The state following 11 is
00, which causes the count to be repeated.
• The excitation table of a sequential circuit is an extention of state
table. This consists of a list of flip-flop input excitation that will cause
the desired state transition. If we use JK flip-flops, the J and K inputs
are the columns in table.
• Let A and B be two flip-flop outputs and X be input variable. The
table for the required output is derived from JK flip-flop state table.
We denote the inputs of flip-flop A by JA and KA and that of flip-flop
B by JB and KB.
• The Table 3.1 indicates the excitation table. An excitation table is an
extension of state table. The first five columns constitute the state
Table 3.1.
• In the first row, we have a transition for flip-flop A from 0 in the
present state to 0 in the next state. For Q(t) = 0 to Q(t + 1) = 0, it
requires that J = 0 and K = X. Hence JA = 0 and KA = X for first row.
• Similarly, for B from 0 in the present state to 0 in the next state, JB = 0
and KB = X. In second row, the transition of flip-flop B is from 0 in
present state to 1 in next state. It requires JB = 1 and KB = X. This
process continues for each row of the table and for each flip-flop.
Table 3.1 : Excitation table for binary counter

Present State Input Next State Flip-flop Inputs
A B X A B JA KA JB KB
0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0
0 1 1 1 0 1 X X 1
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
• A sequential circuits consists of a number of flip-flops and a
combinational circuit. The output of combinational circuit is given as
input to the number of flip-flops as shown in Fig. 3.1.
• In our example, the input to the flip-flop is JA, KA, JB and KB. The input
to combinational circuit is external input x and the present values of
two slip-flops A and B.
• The Boolean function for combinational circuit can be obtained from
the state table that shows input and output of the circuit. The input
variables are A, B and X. The outputs are JA, KA, JB and KB. The K maps
shown in Fig. 3.3 are obtained from state table.
B B
0 0 0 1 0 x x x x
A 1 x x x x A 0 0 1 0
JA = Bx KA = Bx
B B
0 1 x x x x 1 0
A 0 1 x x A x x 1 0
JB = x KB = x
Fig. 3.3 : K-maps for combinational circuit of counter
• The Boolean equation obtained is :
JA = Bx KA = Bx
JB = x KB = x
• The logic diagram is shown in Fig. 3.4 and consists of two JK flip-flops
and a AND gate. The J and K input determine the next state of the
counter.
x
J Q A
C
K
J Q B
c
Clock
Fig. 3.4 : Logic diagram of a 2-bit binary counter
• The state table method is best suited for small control units only. If
the state table is very large, it is very difficult to design a control unit.
The state table does not give information about behaviour of the
circuit, for example, existence of repeated pattern or loops. It also
tends to have random structure due to which maintaining and
debugging of the circuit is difficult.
3.3.1.2 Delay Element Method
• In this method, the control unit is designed using delay elements and
sequence initiation signals. Let us consider an example of generating
the following sequence of control signals at time t1, t2, …, tn using
hardwired control unit.
t1 : Activate {C1, j}
!
tn : Activate {Cn, j}
• The control signals must be generated in sequence and hence a
proper delay element needs to be used. At time t1, control signal
(C1, j) must be activated to perform the corresponding micro-
operation. Let the initiation signal called START (t1) be available at
time t1. The START (t1) signal activates control signal {C1, j}.
• If START (t1) is also given to a delay element of delay t2 − t1, the
output of delay element can work as START (t2), the control signal
{C2, j} can be activated.
• Similarly, another delay element of t3 − t2 delay with START (t2) as

input and START (t3) as output can be used to activate control signal
{C3, j}. This continues till tn, activating (Cn, j) control signal.
• Thus, a sequence of delay elements can be used to generate control
signals in sequential manner. The delay element can be implemented
using D-flip-flop to ensure synchronous operation.
• The control unit using delay elements can be derived from flowchart
that specifies control signal sequence required. The circuit formed has
the same structure as that of a flow chart.
• The following rules must be used to transform flowchart into circuit
elements :
1. The sequence of successive micro-operations requires a delay
element. The signals that activate the control lines are taken
directly from the input and output lines of the delay are as shown
in Fig. 3.5 (a). The signals used to activate same control line Ci,
are fed to an OR gate whose output is Ci. Thus, control signals
C1, C2 and C3 can be generated by activating the inputs of OR
gate, from input or output of delay elements.
2. K-lines in the flowchart that merge to a common line are
transformed into a K input OR gate as shown in Fig. 3.5 (b).
3. A decision box may change sequence of control flow depending
on a condition. It can be implemented by two AND gates as
shown in Fig. 3.5 (c).
C1
{C1, j}
{C1, j}
Delay C2
element
{C2, j} {C2, j}
C3
(a)
k inputs k inputs x x
No
Is x = 1 ?
Yes
(b) (c)
Fig. 3.5 : Flow chart to control circuit transformation
• Let us consider the flowchart in Begin

Fig. 3.6 indicating the control
signal Cij to be activated in the {C1, j}
sequence shown. Fig. 3.7 shows
the control circuit obtained by
using transformation rules. {C2, j}
Is No
x=1?
Yes {C4, j}
{C3, j}
{C5, j}
Fig. 3.6 : Flowchart showing the

control signals to be activated
{C1, j}
Delay
element
{C2, j}
C1
Delay
element C2
x x
Ck
{C3, j} {C4, j}
Delay
element
{C5, j}
Fig. 3.7 : Control unit using delay element for the flowchart in
Fig. 3.6
• The delay element method is simple to design a control circuit, but

has the following disadvantages.
1. The number of delay elements needed is approximately equal to

the number of states n.
2. Each delay element is a sequential circuit of equal or greater

complexity than a flip-flop.
3. Delay element method is more expensive than state table

method due to greater complexity. Synchronization between
delay elements is also difficult.
3.3.1.3 Sequence Counter Method
• A sequence counter method uses a k-sequence counter for

producing the required sequence of control signals. Consider the
circuit shown in Fig. 3.8 (a).
• It consists of a modulo k-counter, whose output is connected to a

clocked 1/k decoder. If the count enable input is connected to a
clock, the modulo k-counter cycles continuously through its k states.
• The decoder generates k pulse signals on its output lines say (φi).
The consecutive pulses are separated by a clock period as shown in
Fig. 3.8 (a).
• The (φi) effectively divides the time required for one complete cycle
by the counter into k equal parts. The (φi) is called a phase signal.
• The Begin and End are the controls for the counter to start or stop
the count. If the Begin is activated, one of the input to AND gate
becomes 1 and when clock is high the counter is enabled. This
commence the counting which cycles until its reset input goes high.
The End or Reset if activated, resets the modulo-k counter and
disconnects the clock input. The symbol used to represent is shown in
Fig. 3.8 (b).
Begin S J Count
Enable
Modulo - k
End R O Reset counter
Clock
Reset
Enable
1 / k Decoder
Begin
Modulo - k
End
sequence
Clock Clock counter
period Reset
f1 f2 fk f1 f2 fk
(a) Symbol (b) Logic diagram

Fig. 3.8 : A modular k sequence counter
• There are many digital circuits that are designed to perform some
actions repeatedly. A control unit based on sequence counter is
shown in Fig. 3.9. The control lines are activated using the output (φi)
from the modulo-k sequence counter in step i for every instruction
cycle.
f1
Modulo - k f2
sequence Logic Count
counter circuit
fk
Cin
Fig. 3.9 : A control unit based on sequence counter
• The state table method is a more systematic approach, that minimises
the number of flip-flops used. The delay element method and
sequence counter method are less formal, but derive the circuit
directly from the behaviour of control unit. Therefore, it is much more
easier, although the number of flip-flops may not be minimised.
3.3.2 Micro-Program Control
• The principle of microprogramming is an elegant and systematic
method for controlling the sequence of micro-operations. The
control function that specifies a micro-operation is binary variable.
This variable is also known as control variable.
• If the control variable is 1, the corresponding micro-operation is

executed. In a bus organised system, the control signals that specify
micro-operations are groups of bits that select the paths in
multiplexers, decoders and ALU.
• The control variable at any given time can be represented by a string
of 1's and 0's called a control word. This control word can be
programmed to perform various operations. A control unit whose
binary control variables are in memory is called a micro-programmed
control unit. Each word is the control memory, which contains within
it, a micro-instruction.
• A micro-program is a sequence of microinstructions. The control
memory can be a ROM because once the control unit is operational,
the micro-program is not changed.
• A memory that is a part of control memory is referred to as control
memory. The next address generator of a micro-program is called a
micro-program sequencer because it determines the address
sequence that is read from the memory.
• The main advantage of micro-programmed control is that, once the
hardware configuration is established, there is no need to change the
hardware. If a different control sequence is needed, a different set of
micro-instructions are specified for the control memory.
• Wilkes first proposed the use of micro-programmed control unit in
1951. Wilkes observed that, there is a need for a flexible and
systematic approach to the design of control unit. We will look at the
Wilke's design in the following description.
• Each bit ki of the counter field corresponds to a distinct control line ci.
When ki = 1 in the current micro-instruction ci is activated otherwise
ci remains inactive. The Fig. 3.10 shows a control unit based in Wilke's
design. The figure shows a decoder, a diode matrix, control memory
address register and multiplexer.
• The ROM is shown in the form of a 8 × 8 diode matrix. Each ROM
location is addressed by the decoder. Each ROM holds an 8 bit
control word with low-order 3 bits specifying the next address and
high-order 5 bits indicate the control signals. The ROM contents are
activated using Control Memory Address Register (CMAR).
• The CMAR can be loaded, externally or from the lines of control
ROM. The decoder accepts the address from CMAR, decodes it and
activates specified diodes in ROM.
F.Y.B.Sc. Electronics (Comp. Sci.) (P-II)
Control Memory
Address Register (CMAR)
X2 0
0 D
1
E2 MUX
1 2
Fig. 3.10 : Wilke’s design
X1 3
0 D
4
MUX
External E1
address 1 5
Decoder
3.13
D X0
0
E0 MUX 6
1
7
Basics of Computer System

E
External load Clock
C0 C1 C2 C3 C4 Next address
Control field
Memory Control field
External
condition '
• The ROM contents are retrieved by the address in the CMAR. For
example, if X2 X1 X0 = 011, then the control lines C1 and C2 are
activated and the next ROM address 100 is feedback to CMAR at the
same time. The CMAR can be also loaded with an external address by
activating the external load input (i.e. E = 1).
• Many micro-programs can be loaded into the control memory and
any of these can be executed by specifying the starting address as an
external address.
• The length of micro-instruction is an important factor while designing
the control unit. This affects the memory-needed to store the micro-
programs in the control memory.
• The micro-instruction length is determined by :
1. The degree of parallelism required at micro-operation.
2. The way the control information is encoded or represented.
3. The method by which the address of next instruction is specified.
3.3.2.1 Micro-Instruction Sequencing and
Interpretation
• A micro-instruction consists of two fields : a control field used to
indicate the control lines to be activated and an address field for the
next micro-instruction in the control memory.
• The instruction in a micro-program follows a specific sequence. Each
instruction has a unique successor. The control sometimes might be
transferred depending on a condition or unconditionally, for example
in JUMP or JUMPZ.
• To control the proper sequencing of micro-instruction special
sequencer's are available.
• For example, AMD 2909 is a micro-program sequencer. AMD 2909 is
so called because it contains all the logic needed to generate next
address. It contains a micro-program program counter, a multiplexer
alongwith stack, so that subroutine calls are possible at micro-
program level.
3.4 Concept of Address Bus, Data Bus,
Control Bus
• A computer basically consists of a processor (CPU), different type of
memory devices and input-output devices. These devices are
connected to CPU by groups of lines. These lines, a communication
pathway, connecting two or more devices, are called buses.
• A bus is shared medium of communication and multiple devices can

be connected to it. A signal transmitted by one can be availed by
other devices attached to it.
• If two or more devices are transmitting data at a time, the signal will
overlap, thus only one device should transmit data at a time.
• A bus consists of a set of lines, each line capable of transmitting
signal representing 0 and 1. So a sequence of signals can be
transmitted through a line. But simultaneous transmission of data is
quicker which can be done by using several lines. For example, 8-bit
data can be transmitted by 8-lines.
• A bus which connects major computer components (CPU, Memory,
I/O) is called system bus. Depending upon function, the buses can be
classified as :
(i) Address bus
(ii) Data bus
(iii) Control bus.
• The address bus carries the address of a memory location or I/O
device that the CPU wants to access. When the address is placed on
address bus, all the devices will receive the address but the device
which receives enable signal from CPU, will only respond.
• The address bus is a unidirectional bus. The data bus provides a path
for moving the data between CPU and devices. The number of lines
in the bus is called as the width of data bus.
• Since each line can carry one bit at a time, the number of lines in the
bus will determine the number of bits which can be transferred at a
time. The width of data line determines the speed of computer
system. The data bus is bi-directional so the data can flow from both
the sides.
• The control bus is also bi-directional bus and used to control the
access to and the use of the data and address bus. The data and
address bus is shared by CPU and other devices, the control bus is
used to control their use. The control bus carries command and
timing information between the devices.
• The main control lines are :

(i) Memory Read : Indicates that, the processor wants to read from
the addressed memory location and the data is placed on the
data bus.
(ii) Memory Write : Indicates that, the processor wants to write into
the addressed memory location and the data from data bus is
written onto the memory.
(iii) I/O Select : Selects I/O or memory device.
(iv) I/O Write : Indicates that, the processor wants to sent data to an
output device and the data at data bus is sent to the addressed
output.
(v) I/O Read : Indicates that, the processor wants to read data from
an input device and the data from addressed I/O is placed on the
data bus.
(vi) Request :
(a) Bus Request : Indicates that, a particular device wants the
control of bus.
(b) Interrupt Request : Indicates that, an interrupt is pending.
(c) Hold Request : Indicates that, the DMA controller needs
control of the bus to perform memory read or write
operation. The signal is sent to the processor.
(vii) Acknowledge :
(a) Transfer Acknowledgement : Indicates that, data have been
transferred.
(b) Interrupt Acknowledgement : Indicates that, the pending
interrupt has been recognised.
(c) Hold Acknowledgement : Indicates that, the processor has
released the control of the bus temporarily.
(viii) Bus Grant : Indicates that, the control of bus has been given to
the device requesting it.
(ix) Clock : Synchronises the operation.
(x) Reset : Initialises all the devices and buses.
A schematic connection of bus is shown in Fig. 3.11.
Output
Memory
device
Control bus
Micro-
Address bus
processor
Data bus
DMA Input
controller device
Fig. 3.11 : Schematic connection of bus

3.5 CPU Block Diagram and Explanation of
Each Block
• A computer consists of an Input device, Output device, Central
Processing unit and Memory. Refer to Fig. 3.12 for the block diagram.
The input device is used for entering the data and output device is
used to display/print or present the output in readable form.
• The Central Processing Unit (or CPU) is the brain of computer
performing all the operations needed for a task/job. The memory is
used to store the data temporarily or permanently.
Central
Processing
Unit
Input Output
device device
Memory
Fig. 3.12 : Block diagram of a computer

• This article will be dealing with the CPU. As mentioned, the

processing of data is done in the CPU. A CPU consists of three major
parts: Register set, Arithmetic Logic Unit (or ALU) and Control Unit,
the diagram in Fig. 3.13 shows these parts of CPU.
• The register set is a fast memory that is used to store the
intermediate data of calculations performed by ALU. The ALU
performs all the required calculations or micro-operations for
executing the instructions. The control unit controls or supervises the
transfer of information between registers and instructs the ALU about
the operations to be performed.
Register
set
Control
Arithmetic
Logic Unit (ALU)
Fig. 3.13 : Major components of CPU

In succeeding articles, we would study the general register
organization, stack organization alongwith hardwired and micro-
programmed control unit.
3.6 Register Based CPU Organization
• In the Fig. 3.12, the memory is the Random Access Memory (RAM)
that is outside the processor. Therefore, accessing of this memory is
slow. This is very important as most of the computer time is
consumed in transferring data amongst memory and processor.
• Thus, using RAM for storing intermediate results of operations
performed in ALU is inefficient. Hence, it is more convenient and
efficient to store these intermediate values in the processor registers.
• A CPU with large number of registers works most efficiently if a
common bus connects these registers. The data transfer between
these registers becomes faster. Therefore, a common unit that can
perform all the arithmetic, logic and shift micro-operations must be
included in the microprocessors.
Register Register Register

A B C
Register Register
Enable/
A A
Disable
MULTIPLEXER
Register Enable/ Register Register

B Disable B D
signal
(a) (b) (c)
Fig. 3.14
• The registers can be connected to each other in different ways. The
output of one register can be connected to other register and vice
versa. This will enable the two registers to transfer the data faster.
This is shown in Fig. 3.14 (a).
• If all the registers are to be connected to each other and any of these
register can be treated as input register and other as output, then
there has to be a common input line and a common output line. This
will not be sufficient, as output of one register will get stored into all
the registers.
• Therefore, some arrangement is needed to select an appropriate
register. This is achieved by using an enable line for every register.
This is shown in Fig. 3.14 (b). The common line used is known as bus.
• The Fig. 3.15 shows a bus organisation for seven CPU registers. The
output of each register (R1 to R7) is connected to the two
multiplexers (MUX). The multiplexers output give the two buses A
and B. The register is selected using selection lines. These two lines A
and B provide the input to the ALU.
• The operations selected determine the micro-operations that are to
be performed. The output of the operations performed in the ALU is
available at the output lines. This output can also be stored in the
registers using the feedback lines shown in the diagram.
• The register to which the output is to be stored is selected using the
decoder. The decoder is used to activate enable line of one of the
register thus transferring the data from output bus of ALU to register
input.
Clock Input
R1
R2
R3
R4
R5
R6
R7
Load SELA SELB
(7 lines) MULTIPLEXER MULTIPLEXER
3´8 A bus B bus

decoder
Arithmetic and Logic Unit

SELD (ALU)
OPR
Output
Fig. 3.15 : Register set with common ALU
• The control unit controls the information flow through the registers
and ALU. The control unit enables or selects the appropriate units or
components in the system.
• For example, to perform the following operation
R1 ← R2 + R3
the control unit provides binary selection variables for the following
selector inputs:
1. MUX A selector (SELA) : This selection places the contents of
register R2 into bus A.
2. MUX B selector (SELB) : This selection places the contents of
register R3 into bus B.
3. ALU operation selector (OPR) : The operation to be performed
is selected i.e. in this case the operation selected is addition
A + B.
4. Decoder destination selector (SELD) : This selection is used to
transfer the content of output bus to register R1.
• The control unit generates the control variables at the beginning of
the clock cycle. The SELA and SELB variables select the registers R2
and R3. The contents of the register transfers through the
multiplexers to the ALU, where the operation is performed on the
data and the output is transferred to the inputs of the destination

register R1 using the control variable SELD.
• The entire operation takes place in one clock cycle. At the next clock
transition, the binary information from the output bus is transferred
into the destination register R1.
• The CPU in the above example contains four selection variables :
1. SELA: To place the contents of the source register on to the bus
A.
2. SELB : To place the contents of the register on to the bus B.
3. OPR : To select the operation to be performed.
4. SELD : To select the destination register to place the output of
ALU using the decoder and its seven load inputs.
• The number of bits needed for these selections form the control
word. In the above example, the control consists of 14 bits : 3 bits
each for SELA, SELB, SELD and 5 bits for OPR. The 14 bits applied to
the inputs specifies a particular micro-operation. The format of the
control word is shown in Fig. 3.16.
Bits 3 3 3 3
SELA SELB SELD OPR
Fig. 3.16 : Control word format

• The following table specifies the binary code for the selection
variables and the register selected by SELA, SELB and SELD
respectively. When SELA or SELB is 000, the corresponding
multiplexer selects the external input data. If SELD=000 the contents
of the output bus are available for the external output.
Table 3.2 : Encoding of Register Selection Fields
Binary Code SELA SELB SELD
000 Input Input Input
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
• The ALU performs all the arithmetic and logic operations. In addition,
the CPU also provides shift operations. The Table 3.3 shows the
various operations for the CPU.
Table 3.3 : Encoding of ALU Operations
OPR Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A + B ADD
00101 Subtract A − B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Examples of Micro-operations :
• The control word consists of 14 bits and specifies the micro-
operation needed for the CPU. The control word can be derived from
the selection variable.
• Consider the example,
R4 = R5 − R6
• It specifies R5 for A input and R6 for B input of the ALU, R4 is the
destination register and ALU operation is to subtract A − B. The
control word can be obtained from the corresponding binary value of
the each field from Table 3.2 and 3.3 respectively. The binary control
word for the subtract micro-operation is as follows 101 110 100
00101 and obtained as
Field SELA SELB SELD OPR
Symbol R5 R6 R4 SUB
Control Word 101 110 100 00101
• The control words for some of the other micro-operations are shown
in Table 3.4. The increment and transfer do not require B input and
hence it is indicated by a – (dash) in the table. Unused fields are 000
in the control word. Such many other micro-operations can be
generated.
• The efficient way to generate this control word is to store them in

memory unit. A memory unit that stores the control words is known
as control memory. The desired sequence of micro-operations can be
initiated by reading the control words from the memory. This type of
control is referred to as micro-programmed control.
Table 3.4 : Examples of Micro-operations for the CPU
Symbolic Destination
Micro-operation SELA SELB SELD OPR Control Word
R1 ← R2 − R3 R2 R3 R1 SUB 010 011 001 00101
R4 ← R4 V R5 R4 R5 R4 OR 100 101 100 01010
R6 ← R6 + 1 R6 − R6 INCA 110 000 110 00001
R7 ← R1 R1 − R7 TSFA 111 000 001 00000
Output ← R2 R2 − None TSFA 010 000 000 00000
Output ← Input Input − None TSFA 000 000 000 00000
R4 ← shl R4 R4 − R4 SHLA 100 000 100 11000
R5 ← 0 R5 R5 R5 XOR 101 101 101 01100
R2 ← R2 − 1 R2 − R2 DECA 010 000 010 00110
3.7 Concept of Stack and Its Organization

• The CPU of most of the computer contains a stack or a storage space
that stores data in the form of Last In First Out (LIFO) list. A stack is a
storage device in which the item stored last is retrieved first. The
stack in a computer is a contiguous memory that is addressable with
the help of a register.
• The register that holds the address of the stack is called stack pointer
(SP) because the value stored in the stack pointer always points to
the top of the stack.
• The stack pointer stores the address of the topmost element. The
reading and writing of stack is done with the help of stack pointer
and the read or written data is in the form of word.
• There are two operations that are performed on a stack. The insertion
of a word onto a stack is called push. The operation of deletion of an
item from the stack is called pop. Incrementing or decrementing the
stack pointer register simulates these operations.
3.7.1 Implementation of Stack
• A stack is normally implemented as a contiguous memory. A large
memory of finite memory words forms the stack. The stack pointer
register SP contains the address of the word that is currently on top
of the stack. The Fig. 3.17 shows a stack of 64 words.
• Consider that, the stack already contains three items: P, Q, and R as

shown in the Fig. 3.17. The item P has been inserted or pushed first,
and then Q and R have been pushed. Therefore, the item Q has been
pushed or inserted last and is on the top of stack. The stack pointer
register contains the value of 3 as the topmost word is at the address
3.
63
FULL EMTY
4
SP R 3
Q 2
P 1
0
DR
Fig. 3.17 : Block diagram of a 64-word stack

• The item is read from the stack by popping the topmost item i.e. R
and transferred to the destination. The stack pointer is then
decremented by 1 (SP = 2) and points to Q. The item is inserted by
incrementing the stack pointer by 1, item is pushed onto the stack by
writing the item at the address stored in the stack pointer register.
The item C is no longer accessible using the stack pointer register.
•
6
The stack pointer register consists of 6 bits because 2 = 64.
Therefore, 64 locations can be addressed with the help of 6 bits. The
address range from 000000 to 111111 i.e. from 0 to 63 in decimal.
• When the SP contains 63 and is incremented 111111 + 1 = 1000000,
then the SP will have 000000 as the stack pointer register consists of
6 bits only. Thus, incrementing SP when it contains an address of 63
changes the address to 0. Similarly, when SP = 0 and SP is
decremented it contains 111111.
• In addition to the stack pointer register two more registers are
needed to indicate if the stack is full or empty. The two registers are
shown as FULL and EMPTY in the above diagram.
• The 1-bit register FULL is set to 1 when the stack is full, and the 1-bit
register EMPTY is set to 1 when the stack is empty. The DR register is
used as data register to read from or write into data to the stack.
Push Operation :
• The initial condition is SP = 0, EMPTY = 1 and FULL = 0. The stack
pointer register points to the word at address 0, and the stack is
empty. A new item can be inserted if the stack is not full.
• The insertion of an item or data is implemented by the following set
of micro-operations :
SP ← SP + 1 Increment stack pointer to point to empty location
M[SP] ← DR Write the item on top of the stack
If (SP = 0) then (FULL ← 1) Check if the stack is full
EMPTY ← 0 Mark the stack not empty
• The stack pointer is incremented by 1 so that it points to the next
address location of the stack. Writing the data from the data register
DR onto the top of the stack indicates a push operation. The stack
pointer register SP holds the address of the top of the stack. M[SP] is
the data stored in the memory location pointed by the stack pointer
SP.
• The first item stored in the stack is at the address location 1 and the
last item is stored at the address 0. If SP = 0 means that the stack is
full and the FULL register is set to 1. If an item is written onto the
stack, then stack is not empty and hence EMTPY = 0.
Pop Operation :
• A new item is read from the stack using a pop operation. This item is
deleted from the stack if the stack is not empty (i.e. EMPTY = 0).
• The following sequence of micro-operations indicates the pop
operation:
DR ← M[SP] Read the item from the stack to the data register
SP ← SP − 1 Decrement the stack pointer
if (SP = 0) then EMPTY ← 1 Check if the stack is empty
FULL ← 0 Mark the stack not full
• The top item of the stack is copied into the data register DR. The
stack pointer is decremented by 1. If the value of SP becomes 0 then
the stack is empty and EMPTY register is set to 1. This condition is
reached when the item that is read or deleted is at the address 0, the
initial value of the stack pointer register.
• If pop operation is executed when SP = 0, then decrementing SP
results in the address 111111 to be stored in SP. In this condition, the
word at address 0 receives the last item from the stack. The
erroneous condition occurs when the data is popped from an empty
stack (EMPTY = 1) or pushed onto the stack that is full (FULL = 1).
3.7.2 Implementation of Memory Stack
• A stack is implemented in a Random Access Memory (RAM) that is
attached to the CPU. The stack can also exit as mentioned in the
previous paragraph. When the stack is implemented in RAM by
setting aside a part of memory for all the stack operations. A
processor register is used as a stack pointer.
• The Fig. 3.18 shows that part of memory that is divided into three
segments viz. text or programme, data and stack. The text segment
contains the actual programme that is under execution.
• The data segment contains the array data that is used by the
programme and the stack segment is the stack used for various
operations on stack. The programme counter (PC) is used to point
the next instruction to be executed in the program.
• The address register (AR) is used to traverse in the data segment. The
stack pointer points to the top of the stack. All the three registers use
a common bus to address the memory and can provide address that
points to the respective memory i.e. text, stack or data.
• The three registers are used during the different phases of an
execution cycle. The PC register is used during the fetch phase of the
read instruction. The AR register is used during the execution phase
of the read. The SP register is used while using the stack to push or
pop items from the stack.
Address
Memory unit
5000
PC
Program/Text
6000
AR
Data
(Operands)
7000
Stack
7996
SP 7997
7998
7999
8000
DR
Fig. 3.18 : Computer memory with program/text, data and stack
• The Fig. 3.18 has the initial value of the stack pointer as 8001. The
stack grows with the decreasing value of the stack pointer. The SP
points to the topmost element that is filled. Therefore, if an item is to
be pushed on to the stack, then decrement the stack and add the
item.
• In the figure, the first item is stored at the address 8000, the second
item is stored at the address 7999 and the last item is stored at the
address 7000. Thus, the stack can contain 1000 items. There is no
facility available to check the limits of the stack.
• The items are added and removed from the stack using the data
register (DR). A new item is added to the stack by pushing the item
on to the stack as follows :
SPA ← SP − 1
M[SP] ← DR
• As mentioned in the previous paragraph the stack pointer is
decremented to point to the empty location. A memory write
operation inserts the word onto the stack.
• An item id removed or deleted from the stack using pop operation is

as follows:
DR ← M[SP]
SP ← SP + 1
• The topmost item is first read and transferred to the data register.
The stack pointer is then incremented to point to the next item on
the stack.
• The computer implement the stack in the memory, but do not
provide any hardware to check stack limits i.e. a check for stack
overflow (stack full) or stack underflow (stack empty). The check can
be implemented by software by storing the stack limits in two
processor registers: one to store upper limit (7000 in the above case)
and other to store the lower limit (8001 in the above case).
• If an item is added i.e. pushed, the stack pointer is first compared
with the upper limit register and when the item is removed or
popped, the stack pointer is checked with the lower limit register.
• Sometimes the stack is implemented in a way that the stack pointer
points to the next empty location. In this case, the sequence of micro-
operations must be interchanged. Loading the bottom-most address
of an assigned stack of memory initializes a stack pointer.
• Thereafter, the stack is automatically incremented or decremented
with every stack operation (i.e. push or pop). The advantage of
memory stack is that, the CPU can refer to it without having to specify
an address, as the address is always available and automatically
updated in the stack pointer register.
3.7.3 Reverse Polish Notation
• A stack is used to evaluate any mathematical expression most easily.
The most common method of writing a mathematical equation is
called Infix Notation. In this notation, the operator is between the
operands.
• For example,
A+B∗C+D
• The ∗ represents multiplication operator. In the above expression,
operators are placed between the operands. A, B, C and D are the
operands and +, ∗ are the operators. The addition (or +) operator is
placed between the operands A and B, C and D. In this example, first
A is added to B (evaluation of A + B), add C to D (evaluation of
C + D) and multiply the two sums. This indicates that storing of two
values is necessary and the evaluation needs to move backward for

finding the value of previous addition. In the above example, there is
also a necessity of parenthesis as someone may evaluate the above
expression as A + (B ∗ C) + D.
• The Polish mathematician Lukasiewicz developed a method to
evaluate this arithmetic expression by representing it in prefix
notation. This notation is also called as Polish notation.
• In this notation, the operators are placed before the operands. If the
operators are placed after the operands it is called Postfix Notation or
Reverse Polish Notation (RPN).
• The example below shows all the three representations of an
expression :
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or Reverse Polish notation
• The Postfix Notation or Reverse Polish Notation (RPN) is best suited
for evaluation of an arithmetic expression using a stack. Consider an
expression
A+B*C+D
The reverse Polish form of the above expression is
AB + CD +*
• The evaluation of reverse polish notation scans the expression from
left to right. The reading stops when an operator is read. On
occurrence of operator, the previous two operands found on the left
side are used as operands and removed from the expression.
• They are replaced by the value obtained by using the operands and
operator just read. The scanning and evaluation continues in this
manner till all the operators are used.
• In the above expression, the scan starts from left reading in the two
operands A and B. As soon as the operator + is read, the expression
A + B is evaluated. The result stored temporarily is say X. Now,
instead of A + B the X acts as one of the operands further.
• The scan continues and finds another operator which is +. The
variable C and D are added and are stored temporarily in say Y. The
next operator we read is *. This operator now has the result of two
additions as operand i.e. evaluates X * Y.
• Thus, the evaluation of arithmetic expression is also possible by using

reverse polish notation. It is important to note that, no parenthesis
are needed in reverse polish notation to indicate the priorities as it is
needed in infix notation.
3.7.4 Conversion from Infix to Postfix Notation
• It is important to note that, conversion from infix to postfix notation
must consider the operator precedence rules of the infix notation.
Using parenthesis we can change the operator precedence.
• The multiplication and division operator is at the same precedence
level and followed by addition and subtraction. When two or more
operators of the same precedence level appear in an expression then
the evaluation is from left to right.
• Consider the following infix expression
(A + B) ∗ [C ∗ (D + E) + F]
• In the above expression, the precedence is changed using the
parenthesis. The evaluation of parenthesis is from inside to outside.
To evaluate the expression, (A + B) and (D + E) are evaluated. The
multiplication is done next i.e. C * (D + E) before adding F to the
product as multiplication has higher precedence. The reverse polish
does not require any parenthesis.
• The above expression can be written as follows in RPN
AB + DE + C * F +*
• The RPN expression is evaluated from left to right.
3.7.5 Evaluation of Arithmetic Expression
• An expression can be evaluated using stack and reverse polish
notation. The expression to be evaluated is first converted to reverse
polish notation. The RPN expression is read from left to right and the
operands are pushed onto the stack.
• On occurrence of an operator two operands from the stack are
popped and the expression is evaluated using the operator read and
the operands popped. The result is again pushed onto the stack. This
procedure continues till the expression is completed and the value
stored in the stack is finally popped.
• Consider the following infix expression,
(1 + 2) * (4 + 5)
• The reverse polish representation of the above expression is,
1 2 + 4 5 +*
• The Fig. 3.19 shows the stack operation. Each box represents stack
storage and the pointer points to the topmost element of the stack.
The RPN expression is scanned from left to right.
• The first two operands 1 and 2 read and pushed onto the stack. The
next symbol is an operator +. Therefore, the stack is popped twice to
get the operands for the operator and evaluated (1 + 2). The result is
again pushed onto the stack replacing the original two operands.
• Next we encounter two operands 4 and 5, so they are pushed onto
the stack. The stack operation that results (4 + 5) from the next +
replaces these operands. The last operation multiplies the topmost
numbers in the stack and produces the result 27. The computers that
use stack organized CPU provides a system program to perform the
conversion for the user.
5
2 4 4 9
1 1 3 3 3 3 27
Fig. 3.19 : Stack operation for evaluation of (1 + 2) * (4 + 5)

3.8 I/O Organization: Need of Interface,
Block Diagram of General I/O Interface
• The Input-Output subsystem or I/O provides the efficient mode of
communication between the central system and the outside
environment. Thus, the I/O subsystem forms the interface between
the computer/central system and the outside world.
• A computer will be useless if it cannot accept any input or display any
output in a human readable form or meaningful form.
• The program and data must be entered into the computer memory
and the results obtained from computation/processing of this
program must be displayed for the user.
• The most popular way to enter the information into the computer
memory is by using typewriter like keyboard. The keyboard allows a
person to enter the alphanumeric information directly into the
computer memory. The speed at which the information can be
entered is dependent on the operator's or person's speed of typing.
• The CPU speed is very high in comparison with the typing speed of
even a fastest typist. Therefore, the CPU remains idle for most of the
time when a person is entering the information directly into the
computer memory using a keyboard.
• To make the efficient utilization of the computer, a large amount of
program and data is prepared in advance and stored on a storage
media like floppy disk or tapes.
• The information on the disk is then transferred into the computer
memory at a much faster rate. Similarly, the results of a program are
also transferred onto the high-speed storage like disks. Later, this can
be transferred to the printer to provide the printout of the results.
• The devices that are under the direct control of the computer are
called connected online. These devices are part of the computer
system and read information into or out of the memory unit on the
command of the CPU.
3.9 REVIEW OF PERIPHERALS
• In the following two sections we review the two most common
peripheral devices Keyboard/Monitor and Disk drive.
3.9.1 Keyboard/Monitor
• The most common means of computer/user interaction is a
Keyboard/Monitor arrangement. The user provides input through the
keyboard. This input is sent to the computer in binary code form and
may also be displayed on the monitor.
• Some additional information may be displayed on the monitor
provided to it by the computer.
• The unit of exchange is character. Each character is represented in
binary by using a 7-bit or 8-bit code. Some of the most commonly
used code is a 7-bit code known as ASCII (American Standard Code
for Information Interchange) and CCITT Alphabet Number 5
internationally.
• Each character is represented by 7-bit binary code. Therefore, 128
characters can be represented.
• There are two types of character sets : Printable and Control. The
printable characters are alphabetic, numeric and special characters,
that can be printed on paper or displayed on a screen.
• For example, character 'A' is represented by bit pattern '1000001'. The

control characters are used to control display/print a character. For
example, CR or carriage return character.
• The key depression on a keyboard generates an electrical signal
interpreted by a transducer and translates to the bit pattern of the
corresponding ASCII code.
3.9.2 Disk Drive
• A disk drive contains electronics for exchanging data, control and
status signals with an I/O module and electronics for controlling the
disk read-write mechanism. A moving head disk must be capable to
cause the disk arm to move radially in and out across the disks
surface.
3.10 Input/Output Interface

• The I/O interface provides a method to transfer information between
internal storage and external I/O device. The peripherals are
connected to the CPU through special communication link.
• The peripheral devices usually differ from the CPU in a way they store
and transfer information. Therefore, the communication link needs to
resolve the difference between the CPU and each of the peripheral.
• Some of the major differences are as follows :
1. The peripherals are usually electromechanical and
electromagnetic devices. The operating signals of these devices
are different from the operations of CPU and memory. For
example, in a hard disk or floppy disk, a motor (a mechanical
devices) moves the read write head to the appropriate sector.
Therefore, proper conversion of signal value is necessary.
2. The data transfer rate of peripherals is much slower than that of
CPU, and hence proper synchronization is needed to manage the
speed mismatch, so that there is no loss of information during
the transfer.
3. The data codes and formats in peripherals are different from the
word format of CPU and memory. The control signals and codes
might be different for peripherals. For example, rotate a motor to
read a reading from CPU registers.
4. The operating modes of peripherals are different from each other

and each must be controlled so that the signals of one does not
interfere with that of other or CPU.
• A special hardware component is used to resolve the differences
between the CPU and peripherals. This component also supervises
and synchronizes all the input and output data transfers. These
components are called as interface units or I/O interface because they
interface between the processor bus and the peripheral device.
• Each device may have a specific controller to supervise operations of
the particular mechanism in the peripheral. For example, hard disk
controller.
3.10.1 I/O Bus and Interface Modules
• In any general purpose computer the processor or CPU is connected
to many peripherals such as printer, keyboard, terminals and
magnetic disk. The CPU communicates with these peripherals using
an Input-Output (I/O) bus.
• The I/O bus consists of data lines, address lines and control lines.
Sometimes a magnetic tape is also connected and used as backup
store. Each peripheral device has an associated interface unit.
• Fig. 3.20 shows a communication link between a processor and
peripheral devices alongwith the interface unit. Each interface
decodes the address and control signals received from the I/O bus,
interpret them for the peripheral, provide appropriate signals for the
peripheral controller.
• The interface synchronizes the data flow and supervises the transfer
between the processor and peripheral. For every peripheral there is a
controller that operates the electromechanical device.
• For example, the hard disk controller, controls the movement of the
motor to bring the sector below the read-write head. In case of
printer, the printer controller controls the paper motion, print timing
and the selection of character to be printed. The controller can be
mounted separately or can be built in for the peripheral.
I/O bus
Data
Address
Processor
Control
Interface Interface Interface Interface
Keyboard
and Magnetic Magnetic
Printer tape
display disk
terminal
Fig. 3.20 : Connection of I/O bus, processor and input-output devices

• The processor communicates with the peripheral by placing the
address of the peripheral on the address lines. Each interface
attached (as shown in Fig. 3.20) contains an address decoder that
constantly reads the address lines.
• As soon as the interface finds the address on address lines itself
(i.e. of attached peripheral), it activates the link between I/O lines and
the peripheral device. The interface of remaining peripherals ignore
the data and control lines.
• This also indicates that, each peripheral must have a unique address.
• The processor provides a function code on the control line
simultaneously when the address is on address line. The interface
with that particular address responds to the function code and
proceeds to execute it.
• The function code is called I/O command. The meaning or
interpretation of the command depends on the peripheral that is
addressed by the processor.
• An interface can receive four types of commands. The commands are
classified as control, status, data output and data input.
o A control command activates the peripheral device and inform
about the action to be performed by the peripheral. The control
command depends on the peripheral used because each
peripheral device has different sequence of commands. The
control command defines the type and the mode of operation.
For example, magnetic tape may be instructed to rewind the tape

or start the tape moving in forward direction.
o A status command is used to test various status conditions in the
interface and the peripherals. During transfer of data one or more
error can occur. These errors are detected by the interface. It is
indicated by setting corresponding bits in the status register. The
processor can read the status register later and know about the
status of the peripheral device. The status register in printer can
indicate paper jam, out of paper, printer not ready etc.
o A data output causes the interface to respond by transferring
the data from data bus to one of its registers. For example, when
a floppy is inserted into the floppy drive a some sector is under
the read-write head. The control command by the processor
request a sector for writing the data onto the floppy. As soon as
the correct sector is at the read-write head, the processor issues a
data output command after reading the status register. The
interface responds to the address and command and transfers
data from data bus to its buffer register. The interface then
communicate with disk controller and sends data to be stored
onto the floppy disk.
o The data input command is opposite of data output command.
The interface receives the data from the peripheral and places in
its buffer register. The status register is set to indicate that the
data requested is available. The processor after reading that
status register issues an data input command. The interface
places the data on the data lines and accepted by the processor.
• Similar to the I/O, the processor also communicates with the memory.
Therefore, a memory bus must also contains data, address and
control lines.
• These are 3 ways in which the memory bus and I/O bus can co-exist
as follows :
1. Use two separate buses, one for memory and other for I/O.
2. Use common bus (data and address) for memory and I/O but
have separate control lines for each.
3. Use common bus (data, control and address) for memory and
I/O.
• The first method is used in computers that provide separate I/O

Processor (IOP) alongwith CPU. The I/O processor is connected to the
memory and CPU. Similarly memory also communicates with IOP and
CPU using memory bus.
• The IOP communicates with the input and output device through a
separate I/O bus. The IOP is used to provide an independent pathway
between memory and external devices. The I/O processor is also
called a data channel. Fig. 3.21 shows the IOP alongwith the CPU and
memory.
Central
Processing
Unit (CPU)
Peripheral devices
Memory Bus
Memory PD PD PD PD
Input/
Output
Processor I/O Bus
Fig. 3.21 : Computer with I/O processor

• The second method is called a memory-mapped I/O. In this method,
the memory and I/O devices share the same address space. The
advantage is that, all memory related instructions are available for I/O
devices.
• All the read and write signals do not distinguish between memory
and I/O addresses. Fig. 3.22 (a) shows memory mapped I/O.
• The third method is called I/O mapped I/O or Isolated I/O. In this, the
memory and I/O addresses are isolated. Therefore, any interface
address assignment does not affect the memory address value.
Fig. 3.22 (b) shows isolated I/O.
Data
Processor Address
Control
I/O Memory
(a)
Data
Address
Processor
Memory control
I/O control
I/O Memory
(b)
Fig. 3.22 : Block diagram of I/O interface unit
3.10.2 ‘I/O Mapped I/O’ Versus ‘Memory Mapped I/O’
• As mentioned above, a common bus can be used to transfer
information between I/O or memory and CPU: The read and write
control a line specifies whether the address on address line is of
memory or I/O. The I/O read or I/O write control lines are enabled
during an I/O transfer.
• Similarly, memory read or memory write control lines are enabled
during memory transfer. In this configuration, the address space of
I/O and memory are distinct or isolated and hence referred to as
isolated I/O method for assigning addresses on common bus.
• In isolated I/O, the CPU has distinct input and output instruction, and
each of these instructions is associated with the address of an
interface register. The CPU fetches and decodes every instruction in
the program. If the operation code is I/O instruction, it places address
associated from the instruction on to the common address lines.
• Simultaneously, CPU enables I/O read or I/O write control lines. This
informs the external components that are attached to common bus
that the address on the address lines is for interface register and not
for memory word.
• If the CPU is fetching an instruction or operand from memory, CPU
places the memory address on the address lines. Simultaneously, it
enables the read memory or writes memory control lines. The
external component recognises that the address is of memory and
ignores it.
• The isolated I/O has separate memory and I/O addresses. Therefore,
any interface address assignment does not affect memory address
values. Each one has its own address space. In the other method, the
memory and I/O share or use the same address space. The computer
has only one set of read and write signals and does not distinguish
between I/O and memory address. This configuration is called as

memory-mapped I/O.
• The interface register is a part of memory system. This reduces the
address space available for memory. No specific input-output
instruction. The memory related instructions are applicable to
interface register also.
• In this configuration, certain addresses are reserved for interface
register. This is not mandatory, as the interface register can be
located at any address, provided no memory address clashes or has
same address.
• The memory-type instructions can also be used for accessing I/O
data. There are no separate instructions of accessing data from
interface register. The major advantage is that, more memory
reference instructions are available than from I/O instruction.
3.10.3 I/O Interface : An Example
• Consider an example of an I/O interface as shown in Fig. 3.23. The
figure shows two data registers called ports (Port A and Port B), a
control register, a status register, bus buffer and timing and control
circuits.
• The chip select alongwith register select form the address of I/O
interface. The CPU and I/O interface communicate using data
registers.
• There are two control lines I/O read for input and I/O write for output
respectively. The ports or data register directly communicate with the
I/O interface.
• The I/O interface may be an input device or output device or both.
The ports : Port A and Port B can be used for transferring information
in or from the computer. If the interface is an output device like the
printer, then data will only be written or output to printer.
• If interface services a character it will only read data. The interface
may give a bidirectional service in the devices like disks.
• In the above case, function code in I/O bus is not needed, because
control is sent to control register, status information is received from
status register and data transferred to and from ports A and B
registers. The common data bus is used to transfer data, control and
status information.
• The distinction of data, control and status information is determined
from the particular interface register that communicates with the
CPU.
Bidirectional Bus Port I/O data

data bus Buffer A
Port I/O data

Chip select B
CS
Internal bus
RS1
Register select Control Control
RS0 Timing register
and
I/O read Control
RD
Status Status
I/O write
WR register
CPU I/O
Fig. 3.23 : I/O Interface example
CS RS1 RS0 Register Selected
0 X X None (Chip not selected)
1 0 0 Port A
1 0 1 Port B
1 1 0 Control
1 1 1 Status
• The control information is given by the CPU using control register.
The bits of control register are set to place the CPU and I/O in
different operating modes.
• For example, port A can be defined as ‘input port’ and port B as
‘output port’. The status register bits are used for indicating the
status, possibly an error occurring during data transfer. The status
may indicate that, port A has received data.
• The interface registers and CPU communicate using bi-directional
data bus. As shown in Fig. 3.23 the address bus line selects the
interface unit using chip select and the two register select inputs. A
decoder is used to enable the Chip Select (CS) when interface is
selected.
• The inputs RS1 and RS0 are two significant lines of the address bus.
These are used to select one of the four registers in the interface. The
information from register is read into the CPU when I/O read is
enabled. The CPU writes the data to the interface when I/O write is
enabled.
Think Over It
• Consider human being life as a computer and identify CPU,

memory, instruction sets, interface, actions and reactions etc.
• Think over when we say that computer operation is hanged?
What may be situation of computer as a system at this stage.
• Visualize concept of stack and stack pointer in day to day life.
Summary
1. A computer basically consists of a processor (CPU), different type of
memory devices and input-output devices.
2. In computer organization architectural attributes include the
instruction set, the number of bits used to represent various data
types (e.g., numbers, characters), I/O mechanisms, and techniques for
addressing memory.
3. In computer organization, organizational attributes include those
hardware details transparent to the programmer, such as control
signals; interfaces between the computer and peripherals and the
memory technology used.
4. CPU consists of register set, ALU and control unit.
5. There are two types of control organization : Hardwired control and
Micro-programmed control.
6. In the micro-programmed organization, control information is stored
in the control memory.
7. There are three methods of designing the control units : The State
table method, Sequence counter method and Delay element method.
8. A state table relates outputs and next states as a function of inputs
and present state.
9. A state diagram represents graphically the behaviour of a sequential
circuit.
10. The state table method is best suited for small control units only.
11. The control unit using delay elements can be derived from flowchart
that specifies control signal sequence required.
12. Delay element method is more expensive than state table method
due to greater complexity.
13. The principle of microprogramming is an elegant and systematic
method for controlling the sequence of micro-operations.
14. A micro-program is a sequence of microinstructions.
15. A memory that is a part of control memory is referred to as control
memory.
16. The main advantage of micro-programmed control is that, once the
hardware configuration is established, there is no need to change the
hardware.
17. The length of micro-instruction is an important factor while designing
the control unit.
18. A bus is shared medium of communication and multiple devices can
be connected to it.
19. A bus consists of a set of lines, each line capable of transmitting
signal representing 0 and 1.
20. A CPU with large number of registers works most efficiently if a
common bus connects these registers.
21. A stack is normally implemented as a contiguous memory.
22. The stack pointer stores the address of the topmost element.
23. The insertion of a word onto a stack is called push.
24. The operation of deletion of an item from the stack is called pop.
25. A stack is used to evaluate any mathematical expression most easily.
26. The RPN expression is evaluated from left to right.
27. The devices that are under the direct control of the computer are
called connected online.
28. Disk drive contains electronics for exchanging data, control and
status signals with an I/O module and electronics for controlling the
disk read-write mechanism.
29. The most common means of computer/user interaction is a
Keyboard/Monitor arrangement.
30. The processor communicates with the peripheral by placing the
address of the peripheral on the address lines.
31. The key depression on a keyboard generates an electrical signal
interpreted by a transducer and translates to the bit pattern of the
corresponding ASCII code.
32. The I/O bus consists of data lines, address lines and control lines.
33. A control command activates the peripheral device and inform about
the action to be performed by the peripheral.
34. A status command is used to test various status conditions in the
interface and the peripherals.
35. A data output causes the interface to respond by transferring the
data from data bus to one of its registers.
36. The interface register is a part of memory system.
Exercise
[A] True or False :
1. Architectural attributes include the instruction set.
2. The RPN expression is evaluated from right to left .
3. The stack pointer stores the address of the topmost element .
4. A micro-program is a sequence of microinstructions.
5. A CPU with minimum number of registers works most efficiently
if a common bus connects these registers.
6. The state table method is best suited for large control units.
7. A stack is normally implemented as a contiguous memory.
8. The interface registers and CPU communicate using uni-
directional data bus.
9. All the read and write signals do not distinguish between
memory and I/O addresses.
10. Computer organization refers to the operational units and their
interconnections that realize the architectural specifications.
11. The control bus carries the address of a memory location or I/O
device that the CPU wants to access.
12. Delay element method is more expensive than state table
method.
1. Which memory device is generally made of semiconductors?
(a) RAM (b) Hard-disk
(c) Floppy disk (d) CD
2. The control unit controls other units by generating ……
(a) Control signals (b) Timing signals
(c) Transfer signals (d) Command Signals
3. …… bus structure is usually used to connect I/O devices.
(a) Single bus (b) Multiple bus
(c) Star bus (d) Rambus
4. The I/O interface required to connect the I/O device to the bus
consists of ……
(a) Address decoder and registers
(b) Control circuits
(c) Address decoder, registers and control circuits
(d) Only control circuits
5. During the execution of a program which gets initialized first?
(a) MDR (b) IR
(c) PC (d) MAR
6. The main advantage of multiple bus organization over a single bus is
……
(a) Reduction in the number of cycles for execution
(b) Increase in size of the registers
(c) Better connectivity
(d) None of the above
7. The clock rate of the processor can be improved by ……
(a) Improving the IC technology of the logic circuits
(b) Reducing the amount of processing done in one step
(c) By using the overclocking method
(d) All of the mentioned
8. When performing a looping operation, the instruction gets stored in
the ……
(a) Registers (b) Cache
(c) System heap (d) System stack
9. …… is an extension of the processor BUS.
(a) SCSI BUS (b) USB
(c) PCI BUS (d) None of the these
10. …… are the different type/s of generating control signals.
(a) Micro-programmed
(b) Hardwired
(c) Micro-instruction
(d) Both micro-programmed and hardwired
11. What does the end instruction do?
(a) It ends the generation of a signal
(b) It ends the complete generation process
(c) It starts a new instruction fetch cycle and resets the counter
(d) It is used to shift the control to the processor
12. In micro-programmed approach, the signals are generated by ……

(a) Machine instructions (b) System programs
(c) Utility tools (d) None of the above
13. A sequence of control words corresponding to a control sequence is
called ……
(a) Micro routine (b) Micro function
(c) Micro procedure (d) None of the above
14. The digital information is stored on the hard disk by ……
(a) Applying a suitable electric pulse
(b) Applying a suitable magnetic field
(c) Applying a suitable nuclear field
(d) By using optic waves
1. What are the advantages of general register organization?
2. Explain with an appropriate diagram a bus organization for CPU
register.
3. How are micro operations interpreted/implemented in CPU bus
organization.
4. What is a stack? What are the different operations performed on a
stack?
5. How stack is implemented? Explain with an example of
implementation of PUSH and POP.
6. Explain Infix and Prefix representation of an expression. Give suitable
example.
7. Convert the following expression from infix and PRN.
(a) (A * B * C) + (D * E) (b) (A * B + C) * (D/E)
(c) A + (B * C) + D
8. Convert the following expression from PRN to infix.
(a) A B C D E + * − / (b) A B C * / D – E F / +
(c) A B C D E F G +*+*+*
9. Explain with an example the stack operations for evaluation of an
expression using RPN.
10. Explain the steps involved in hardwired control design.
11. Explain Wilke’s design.
12. Explain the following design methods of control unit.
(a) State table method (b) Delay element method
(c) Sequence counter method
13. What are rules for transforming a flowchart into a circuit?

14. Write a short note on micro program sequencer.
15. Explain with example I/O interface with computer system.
1. State composition of computer system.
2. State applications of processor.
3. What is computer organization?
4. List types of control organization.
5. Define CPU in processor.
6. What is micro-programmed organization?
7. State main advantage of micro-programmed control.
8. What is hardwired control?
9. Define state table, state diagram.
10. State disadvantages of delay element method.
11. State principle of microprogramming.
12. Give names of micro-instruction fields.
13. Describe in brief disk drive.
14. What is stack? State its application.
15. Define PUSH and POP operation in stack.
16. What is Infix notation? Give example.
17. Enlist important Input and Output peripherals to computer.
18. State role of I/O interface.
19. What is ‘I/O Mapped I/O’ and ‘Memory Mapped I/O’?
20. How PRN is evaluated?
21. What is role of status command for interface of peripheral?
Answers
[A] True or False :
(4) True (5) False (6) False
1. (a) 2. (b) 3. (a) 4. (c) 5. (c) 6. (a) 7. (d)
8. (b) 9. (c) 10. (d) 11. (c) 12. (a) 13. (a) 14. (a)
✍✍✍
Unit 4…
Memory Organization
Tom Kilburn CBE FRS (11 August 1921 – 17
January 2001) was an English mathematician and
computer scientist. Over the course of a
productive 30-year career, he was involved in the
development of five computers of great historical
significance. The Williams tube, or the Williams–
Kilburn tube after inventors Freddie Williams and
Tom Kilburn, is an early form of computer
memory. It was the first random-access digital
Tom Kilburn storage device and used in the world's first
(CBE FRS) electronic stored-program computer.
In computing, memory refers to a device that is used to store
information for immediate use in a computer or related computer
hardware device. A memory unit is the collection of storage units or
devices together. The memory unit stores the binary information in the
form of bits. Generally, memory/storage is classified into two categories,
one as Volatile Memory and other Non-volatile memory. Volatile memory
loses its data, when power is switched off, whereas in non-volatile
memory there is a permanent storage and it does not lose any data when
power is switched off.
4.1 Introduction
• The memory unit that communicates directly within the CPU, Auxiliary
memory and Cache memory, is called main memory. It is the central
storage unit of the computer system. It is a large and fast memory
used to store data during computer operations.
• Devices that provide backup storage like magnetic disc, CD are called
auxiliary memory. It is not directly accessible to the CPU, and is
accessed using the Input/Output channels. The data or contents of
the main memory that are used again and again by CPU, are stored in
the cache memory so that we can easily access that data in shorter
time.
4.1
F.Y.B.Sc. Electronics (Comp. Sci.) (P-II) 4.2 Memory Organization
• Virtual memory is a system where all physical memory is controlled

by the operating system. When a program needs memory, it requests
it from the operating system. The operating system then decides in
what physical location to place the program's code and data.
• In this unit we will discuss Memory architecture, Memory hierarchy,
Types of memory, Data Read/Write process, Vertical and Horizontal
memory expansion, Role of Cache memory and Virtual memory.
4.2 Memory Architecture
• Memory is an essential part of computer which stores data and
instructions required for its operation. The computer also stores
intermediate results and final results in the memory. So a computer
needs an immediate and uninterrupted assess to memory. As data
interchange takes place between processor and memory devices, so
the time required should be such that the processor can operate with
its maximum speed.
• If the speed of memory is less than the speed of processor, the
processor has to wait for data and instructions which are stored in
memory. A processor is a semiconductor device and operates at very
high speed. So a semiconductor memory, with comparable speed,
should be used for immediate data transfer.
• Semiconductor memories are faster, smaller in size and light in
weight, but relatively costly, whereas magnetic or optical memories
are cheaper but are slow in comparison with semiconductor
memories. So, one has to use combination of semiconductor,
magnetic and optical memories.
• The memory can be divided into following main groups
1. Internal Processor Memory : This consist of a set of registers
built in processor chip itself. The speed of it is same as that of
CPU. This part of memory is mainly used for storing intermediate
results, temporarily. As the size of memory is very small, cannot
be used for data storage.
2. Cache Memory : This is, also, used for storing currently needed
instructions and data of a programme being executed. It is
placed, logically, between internal processor memory and main
memory and can operate with high speed.
3. Main Memory : This is also a fast semiconductor memory having

relatively large size and can be accessed by the processor.
It stores programs and data processed by the processor.
4. Secondary or Auxiliary Memory : This type of memory have
large storage capacity but is slower than main memory. It is used
for storing data permanently, data having large size, data not
used frequently by processor and also serves as an overflow
memory. The data cannot be accessed directly by the processor.
4.3 Memory Device Characteristics
• A memory organization uses different types of memories, having
different parameters. Selection of a memory device depends on its
speed, cost, size and type. So, while designing a memory technology,
one must have good knowledge of these general properties.
(i) Cost : The cost of a memory unit decides the price of complete
memory device. The price of the memory device includes the cost of the
data storage unit, and the cost of peripheral equipment or access circuitry
which are essential for the operation of the memory.
If C is the price of complete memory system (memory device and
peripherals) having S bits of storage capacity, then the cost c of the
memory will be
C
c = Rupees/bit
S
(ii) Access Time : This will decide the time taken for the interchange
of the data between memory and processor. Basically, it will be decided
by the speed of the memory and the processor. The speed of the memory
will depend on the rate at which information can be read from or written
into the memory.
The read access time tA, is the average time required to read a fixed
amount of information from the memory.
Similarly, write access time is the average time required to write a
fixed amount of information from the memory. Usually, read and write
access time is equal.
The access time depends on physical characteristics of storage device
and access mechanism used. It is measured from the time, a read request
is received to the time requested data is made available at the output
terminal of memory device. The words accessed per second is defined as
1
‘access rate, bA’ and mathematically, it is .
tA
Low cost and high access rates are desired memory characteristics
but in reality it is not possible. Generally, low cost memories are slower
and high access rate is achieved at higher cost. The relation can be
approximated by a straight line.
y x
If we write tA = 10 and C = 10 , then y = mx + k. The Fig. 4.1 shows
graph of access time versus cost for a memory technology.
0
10
Optical memory
Access time (tA)
-5 Magnetic
10 disks MOS RAMs
-11
Bipolar RAMs
10
-9 -6 -3
10 10 10
Cost (C)
Fig. 4.1
(iii) Access Modes : A desired location on memory device can be
accessed in many ways. Firstly, a memory location can be accessed in any
order. This type of memory is called Random Access Memory (RAM). In
RAMs, any memory location can be accessed directly, the access time is
independent of memory location. Best example is semiconductor
memory.
Secondly, a memory location can be accessed by only a
predetermined order. This type of memory is called serial-access memory.
In this, the access time depends on the location of the information, hence
increasing overall access time. Magnetic-tape, magnetic disk and optical
memories use serial access methods.
In random-access memory, a separate access mechanism or a read
write head is used for every location. The Fig. 4.2 shows schematic
diagram for R random access memories.
Read-write head selector
Read-write
heads
memory
location
Fig. 4.2 : Random access memory

The Fig. 4.3 shows schematic diagram for serial access memory. In
serial access memory, a single access mechanism or read-write head is
used which is shared by different locations.
Read - write
head
Memory
location
Fig. 4.3 : Serial access memory

The read-write head or the stored information or both are moved
and a particular location is accessed when it pass the read-write head.
Thus, the access time depends on the location of the information.
A magnetic disk contains a large number of independent rotating
tracks and each track has its own read-write head. So, in this case tracks
can be accessed randomly and each track is accessed serially. Such mode
of access is called semirandom.
(iv) Reliability : There are always chances of memory failure. The
mean time of failure, done over large time, gives reliability of a memory
device. The memories having no moving part, semiconductor memories,
are more reliable than memories having moving parts like hard disk,
floppy disk etc. These memories have moving mechanism which increases
the failure rate. But in semiconductor memories also, the failure may
increase due to high storage density and high data-transfer rate. The
reliability can be increased by using error detecting and error correcting
codes.
(v) Power Consumption : The power consumption of a memory is
an important character while designing a memory system. The power
consumption decides the running cost of the computer system. A
memory having large capacity and high power consumption generates
heat. This requires proper cooling for avoiding memory failure.
(vi) Package Density : The package density is the bits of data stored
per unit area or volume. The package density determines the physical size
of the memory. A portable computer system needs smaller physical size
with high package density.
(vii) Alterability : Sometimes the method used to write information
into a memory may be irreversible i.e. once the data has written, cannot
be altered or atleast difficult to alter. The memories whose contents
cannot be altered are called Read Only Memories (ROMs). ROMs are
most widely used for storing control programme. The memories whose
contents can be (with difficulty and off-line) changed are called
Programmable Read-Only Memories (PROMS).
(viii) Permanence of Storage : There are three important
characteristics that can destroy the information :
(a) Destructive read-out
(b) Dynamic storage
(c) Volatility
(a) Destructive read out : Some memories have property that the
data is destroyed while reading the memory, this is called
Destructive Readout (DRO). But sometimes reading does not
affect the stored data, is called Non-destructive Read-Out
(NDRO). In DRO memories, each read operation must be
followed by write operation that restores the original data. This
restoration is done automatically by buffer register.
(b) Dynamic storage : In some memories, the data is lost due to
leakage of stored charge. In this, the data is restored by
refreshing it. Such type of memory is called dynamic memory. On
the other hand static memories do not decay with time.
(c) Volatility : In some memories data is lost by power failure. Such
memories are called volatile memories. Semiconductor memories
are volatile memories. The magnetic or optical memories do not
loose data even after power failure and are termed as non-
volatile.
(ix) Cycle time and data transfer rate : In dynamic of DRO
memories, it is not possible to have second memory access until a restore
or refresh operation has been carried out. Thus, the time taken between
two accesses is greater than access time. This delayed time is called the
cycle time (tm).
So, time needed to complete read or write operation is tm, hence the
1
maximum amount of data transferred every second is . This is called
tm
the data transfer rate or bandwidth bm. The bandwidth is limited by
memory bus width w.
w
bm =
tm
(x) Physical characteristics : The physical properties used for
memories are electronic, magnetic, mechanical and optical. A storage
medium must have two well defined physical states, that can be used to
represent the logic 0 and 1. The access rate also depends on the rate of
reading physical 0 and 1 state.
Characteristics of Memory Technologies:
Technology Access Access Alterability Permanence Physical
time tA ‘S’ mode storage
medium
CD-ROM 1 Semi- ROM Non-volatile Optical
random
Magnetic 10−1 Serial R/W Non-volatile Magnetic
tape
Magnetic disk 10−2 Semi- R/W Non-volatile Magnetic
random
MOS 10−8 Random R/W Volatile Electronic
Bipolar Semi- 10−9 Random R/W Volatile Electronic
conductor
4.4 Memory Hierarchy
• The main constraints while designing a memory are size, speed and
cost. But memory with smaller access time is costly, with greater
capacity have low cost per bit and with greater capacity have greater
access time.
• A designer always prefer large capacity memory, because of its

capacity and because the cost per bit is low. But for greater
performance the designer needs memories with fast access time, but
these are expensive with low capacity.
• The dilemma can be solved by using memory hierarchy. The Fig. 4.4
(a) and (b) shows a typical hierarchy.
Cache
Main Secondary
CPU Memory Memory
(a)
Registers
Cache
Main memory
Magnetic disk
Magnetic tape Optical disk
(b)
Fig. 4.4
• As one goes down the hierarchy, the following occur
(i) Decreasing cost/bit [Ci > Ci + 1]
(ii) Increasing capacity [Si < Si + 1]
(iii) Increasing access time [tAi < tAi + 1]
(iv) Decreasing frequency of access by processor.
• Thus, smaller, expensive, faster memories are supplemented by larger,
cheaper, slower memories.
• Suppose (M1, M2 … M3) are memory system forming a memory
hierarchy in which each member Mi is subordinate to next higher
member Mi − 1 of the hierarchy. In general, all the information stored
in Mi − 1 can be stored in Mi, but not vice versa. The processor

communicate directly with first member M1, M1 can communicate
directly with M2 and so on.
• During execution of a program, the processor generates a continuous
stream of memory addresses. If the address is assigned only to
Mi (i ≠ 1), the address must be reassigned to M1 so that the processor
can access it directly. This involves transfer of data from Mi to M1
which decreases the speed of process. So for a hierarchy to work
efficiently the address generated by processor should be found in M1
all the time.
Locality of Reference :
• For efficient working of hierarchy it requires prediction of future
address so that the information can be transferred to M1, before it is
requested by the processor. The prediction of logical memory
address is called locality of reference.
• Suppose that, a request is made for a one-word data D stored at
address A, assigned to memory Mi (i ≠ 1). The data required next, by
the processor is the one immediate following D, stored at address
A + 1. Thus, instead of transferring just D to M1 a string of
consecutive data is transferred.
• Generally, data stored in memory is divided into pages. So if a
request is made for data D from memory Mi, one complete page with
Spi words is transferred to Mi from Mi + 1. Then the page of Spi − 1
transferred to Mi − 1 and so on. Finally, page having length Sp1
containing data D is transferred to M1, where it can be directly
accessed by processor.
Design Objectives :
• The purpose of designing a memory hierarchy is to achieve speed of
fastest memory M1 and cost per bit of cheapest device Mn.
• The performance of the hierarchy depends on factors :
1. The address reference statistics.
2. The access time tA of each unit.
3. The storage capacity of each unit.
4. The size of the data page transferred between successive
memory units.
• But these parameters are related in very complex manner. The overall
analysis can be done by using analytic models and simulations.
Cost and Performance :

• Consider two level hierarchy with units M1 and M2. The average cost
per bit of memory is given by :
c1S1 + c2S2
c = … (i)
S1 + S2
where, c = Cost per bit
S = Storage capacity
• The performance of memory hierarchy is measured in 'Hit ratio' (H).
The hit ratio H is defined as, “the probability that a logical address
generated by processor refers to information stored in M1”. Let N1
and N2 be the references satisfied by M1 and M2 respectively then,
N1
H = … (ii)
N1 + N2
The hit ratio H depends on address generating program.
The quantity 1 − H is called the 'miss ratio'.
• The average access time for the processor to access a word in the
memory system M1 and M2 are,
tA = H tA1 + (1 − H) tA2 … (iii)
where tA1 and tA2 are access times of M1 and M2.
• When request for data not available in the main memory is made, a
block of data is transferred to the main memory. Till then the
processor has to wait for the data. The time tB required to transfer a
block of data is called the 'block replacement'.
Therefore, tA2 = tB + tA1 … (iv)
Substituting in equation (iii),
tA = HtA1 + (1 − H) (tB + tA1)
tA = tB + tA1 − HtB
∴ tA = tA1 + (1 − H) tB … (v)
As block transfer is a slow process, tB >> tA1.
∴ tA2 = tB … (vi)
tA2
• The access time ratio of two levels of memory is given by r = . The
tA1
tA1
factor e = is called ‘access-efficiency’.
tA
Consider equation (iii),

tA = HtA1 + (1 − H) tA2
tA = H(tA1 − tA2) + tA2
1 tA tA1 tA2 tA2

Dividing by tA1 = =H − +
e tA1 tA1 tA1 tA1
1
∴ e = … (vii)
r + (1 − r) H
• Memory is costly and it is desired not to waste even small part of
memory. So at anytime, the memory space Su occupied by active
parts of user programmes to the total amount of memory space
available is S. This is called as the space utilization u,
Su
u = … (viii)
S
The space S − Su which is not used by programmer is called wasted
space.
4.5 Types of Memories
4.5.1 Main Memory
• In earlier computers, the most common form of random access
storage for main memory employed an array of doughnut shaped
ferromagnetic loops called as cores. Therefore, main memory is also
called as core. But now magnetic memories have been totally
replaced by semiconductor memory chips.
• The main memory of computer consists of Random Access Memory
(RAM). The major types of semiconductor memories are Read-Write
Memory (RAM), Read Only Memory (ROM), Programmable ROM
(PROM), Erasable PROM (EPROM) and Electrically Erasable PROM
(EEPROM).
• The main characteristics of RAM is that, we can read or write data
directly at any given memory location. The other feature of RAM is
that they are volatile, so they need constant power supply.
• The almost opposite of RAM is Read Only Memory (ROM). As the
name indicates, it is not possible to write down new data into it.
Basically, ROMs are used for storing library subroutine, system
programs and function tables.
• Sometimes, one needs special type of data to be stored in ROM but
such specific ROM may not be available in the market. The said
problem can be solved by using programmable ROM's (PROM’s). Like

ROM, PROM is also non-volatile and data can be written just once.
In PROM, data is written electrically by manufacturer, once, as per the
requirement of user.
• Slight variation of read-only memory is read-mostly memory. In this,
data is read more frequently than it is written. One of these is
erasable PROM (EPROM). Here read and write operation is done
electrically. The more attractive form of EPROM is electrically erasable
PROM (EPROM). Here writing procedure is easier than EPROM.
4.5.2 Associative Memory
• In an associative memory any stored item can be accessed directly by
using the contents of the item in the question, generally some
specified subfield as an address. The subfield to address the memory
is called key. So the data stored in associative memory is key + data.
• Any subfield of stored data can be chosen as key. The desired key is
specified by the mask register. The key is compared simultaneously
with all stored words. When the key matches, it gives a match signal
which goes to select circuit.
• The select circuit enables the data to be accessed. If many
information have same key then the select circuit decides the data to
be read. The Fig. 4.5 shows structure of associative memory.
• Every keyword is compared to the input key word and must have
individual match circuit. This requires a complex electronic circuit
which makes it expensive.
Input
Mask Register
Key
Match
Storage Cell Select
Circuit
Select
Output
Fig. 4.5
• The advances in semiconductor technology has made it economically
feasible. But, still high prices limit to applications where relatively
small amount of data is to be accessed very rapidly.
• The following table has three columns

Name ID No. Roll No.
Ankit 136 22
Mayank 141 24
Amit 001 26
Shiv 170 27
Rafique 169 28
• The table has three subfields : Name, ID No. and Roll No. If second
row is to be accessed by associative memory, one of the entity, like
ID No., can be used as key.
4.5.3 Auxiliary Memory
• The auxiliary memory is also called secondary memory or backing
memory. Secondary memory is generally used for supporting the
main memory. This is a slow and low cost and larger in capacity.
• Due to these properties it is used for storing bulk data which, are not
referred frequently by the processor. It is, also used, as an overflow
memory when the capacity of main memory is full. The data in
secondary memory can not be accessed directly by the processor but
I/O instructions are used for transferring the data to main memory
from the secondary memory. From main memory data can be
accessed by the processor.
•
rd
This is permanent memory used at 3 level in memory hierarchy.
Generally, magnetic tapes, magnetic disks and optical disks are used
as secondary memory. These are cheaper than semiconductor
memories having mass storage capacity. It stores operating system,
compilers, assemblers, application programmes etc.
(i) Magnetic Disk :
• The data and programs are stored in computer system by using
ROMs, RAMS, EPROMs etc. But these devices cannot store large
amount of data. So for storing large amount of data, magnetic disks
are used. The type of disks are, floppy disks or diskettes and hard
disks.
• A disk is a circular plate of metal or plastic coated with a magnetic
material. The data is read or written by conducting coil, called head.
The magnetic field induces current flow in the coil or vice-versa.
(a) Floppy Disk :

•
1 1
Floppy disks normally come in 3 /2 inch, 5 /4 inch and 8 inch.
They are thin and circular, enclosed permanently in a plastic
jacket. The jacket protects the circular disk and the disks rotates
within the jacket. The Fig. 4.6 shows floppy disk.
• The disk is made of very thin plastic material coated with
magnetic material on one or both the sides. A hole is provided at
the centre of the disk for drive spindle. Another hole in the jacket
near the centre is provided to detect the index hole in the disk.
This provides index mark.
• There is another slot called the heat slot, which exposes the
recording surface to the head. When the disk is rotating, the
head moves across the surface of the disk through the head
window. To prevent the data recorded, from unwanted erasure,
there is write enable notch, which when covered with tab,
protects the erasure.
• There are two locating notches which helps in positioning of the
disk correctly in the drive.
Floppy disk
Jacket
Write enable
notch
Hole in disk
for drive
Index hole in jacket
Index hole in disk
Head
window Locating notches
Fig. 4.6
Disk Formats :
• In order to locate a data for reading or data location for writing,
it is necessary to organize the disk into tracks and tracks into
sectors. The tracks are concentric set of rings separated by gaps
for proper data storage.
• The width of tracks is same as that of head. The data is recorded,
in the disk, in form of blocks. Typically, the block is smaller than
the capacity of a track. The region storing a block of data is
known as sector. The Fig. 4.7 show disk data layout.
Inter - record gap

Sector
Inter - track gap
Tracks
Fig. 4.7 : Disk data layout

• Generally, a floppy disk has 40 or 80 tracks and typically 10 to
100 sectors per track. If the disk is double sided, both the sides
can be formatted and can be used for storing the data.
(b) Hard Disk :
• Hard disks use a rigid aluminium plate on which recording
material is deposited for storing the data. The hard disk
continuously rotates with speed of 2400 to 3000 rpm. The
read/write heads are aerodynamically designed and fly over the
disk surface and never touch it.
• Some disk drives accommodate multiple platter stacked vertically
about an inch apart. Separate heads are used for reaching each
disk and each side of disk. The platters come as a unit known as a
disk pack. The Fig. 4.8 shows hard disk mechanism.
Read / write head
(one per surface)
Direction of
arm motion
Recording
surface
Fig. 4.8 : Multiple platter disk
Characteristics of Disk System :

Head motion : Fixed (one per track)
Movable (one per surface)
Platters : Single-platter
Multiple-platter
Sides : Single-sided
Double-sided
Head mechanism : Contact (floppy)
Aerodynamic gap (Hard- disk)
(ii) Magnetic Tape :
• Just like cassette tape recorder, magnetic tape can be used for
recording the data in coded form. The magnetic tapes can record
large amount of data which can be erased and recorded easily.
• The tape reels can be changed and hence same drive mechanism can
be used. But the main disadvantage is that, the data is accessed
serially and access time is large. This makes it a slow memory.
• The information is generally stored in nine parallel longitudinal tracks,
(8 bit data and 1 bit parity check). A single head reads or writes the
data simultaneously on 9 tracks.
• The Fig. 4.9 shows the main component of a tape drive system. Two
reels are used to store the tape. The tape does not move
continuously but on receiving an access request, the tape moves
forward or backward to the desired location and is stopped at the
end of data transfer.
Tape reels
Head
Capstans
Fig. 4.9 : Magnetic tape drive
• The data transfer takes place only when the tape is moving at
constant velocity, hence the data transfer rate is determined by the
storage density and the tape speed. The information stored in tape, is
in the form of block. This permits the tape to start and stop between
blocks.
4.6 Data Read/Write Process
• The basic element of memory is memory cell. A memory of large
capacity is realized interconnecting small memory cells. Most
commonly, the cell has three functional terminals capable of carrying
an electrical signal. The select terminal, selects a memory cell for
read-write operation. The control terminal indicates read or write. For
reading the signal, third terminal is provided.
Control
Data in / out
Select
Fig. 4.10 : Memory cell operation

• The Fig. 4.11 shows how RAM and ROM units in a computer system
are connected to the processor and I/O devices by buses.
Address bus
Input /
Output ROM RAM Processor
I/O
Control bus
Data bus
Fig. 4.11 : Main memory organization
• Whenever a program is executed, the instruction sets and data

should be present in the main memory unit so that the processor can
directly fetch the instructions or data. And the processed
information/final result is stored in the main memory.
• If the instruction/data is not present in main memory, the processor
first loads it from auxiliary memory into main memory. If the memory
is slow, the processor has to wait, so the main memory should be fast
enough to improve the overall performance of the system. The main
memory constitutes semiconductor memory like ROM, RAM.
(i) Read-Only-Memory (ROM) :
• The ROMs are used to store binary information, permanently ROMs
are implemented with electronic devices like diodes and transistors.
The data is written into the memory at the time of manufacture as
per the requirement of user.
• The data, once written, cannot be changed or atleast difficult to
change. The ROM uses memory cell which is fabricated by using
diodes or transistors.
• The memory cells are organised in rows and columns as shown in
Fig. 4.12.
Cell Cell Cell Cell
y1 11 12 13 14 Word 1
y2 Word 2
y3 Word 3
Address Decoder
A
Word 4
Address
y4
B
y5 Word 5
C
y6 Word 6
Word 7
y7
81 82 83 84 Word 8
y8
Output Buffer
D C B A
Fig. 4.12 : ROM organization
• In reading process the data appears at the output. The output is

buffered so that the memory contents are not lost during reading
process. The diagram shows 32 memory cells placed in 4 columns
(word) and 8 rows. Each word can be addressed any time by an
address decoder.
• The ROMs are available from small to large capacities but they are
manufactured according to users requirement. The Fig. 4.13 shows
IC 7488 A, which is 256 bit (32 words of 8 bit each) TTL device. The
5
32 rows (8 bits each) are accessed by 5 (2 = 32) address inputs.
y1 1 16 + VCC A 10 16 + VCC
y2 2 15 G (Enable) B 11 1
y3 C 2
3 14 E Input 12
3
y4 4 13 D D 13
7488 A 4
y5 5 12 C E 14 5
y6 6 11 B G 15 6
(Enable)
y7 A 7
7 10
Gnd 8 9 y8 Gnd 8 9
(a) Pin connection (b) Logic symbol

Fig. 4.13 : IC 7488 A
• A larger memory organization is difficult to implement.
(ii) Random-Access-Memory (RAM):
• The ROMs provide facility of just reading the data stored in the
memory. In ROMs data can be stored once and cannot be erased or
rewritten. In a RAM, data can be written into it as often as desired
and can be read without destroying the contents of the memory.
• There are two types of RAMS, static and dynamic. In static RAM and
flip-flop, bipolar or MOS is used for storing the data. The Dynamic
RAM stores data in form of charge which is stored by using MOS
devices. As the charge decays with time, it needs continuous
refreshing.
• The Fig. 4.14 shows RAM IC 7489. In IC 7489, 64 memory cells are
arranged in 16 rows and 4 columns. The words can be accessed by 4
address lines.
11 12 13 14 Word 1
Word 2
Address decoder
A0 1
Address
A1 15
14
A2
13
A3
CE
2
161 162 163 164 Word 16
Memory
enable
Write 3
Raed / Write Raed / Write Raed / Write Raed / Write
enable WE Bit 1 Bit 2 Bit 3 Bit 4
4 5 6 7 10 9 12 11
Output O1 O2 O3 O4
Input D1 D2 D3 D4
(a) Block diagram
1 VCC 16 + 5 V
A0 1 16 + VCC A0
15
Address
A1 A1
CE 2 15 14
A2 O4 11
13
Data output
WE 3 14 A2
A3 9
O3
D1 4 13 A3
7489 2 7489 O2 7
O1 5 12 D4 Memory enable CE
Write enable 3 5
WE O1
D2 6 11 12
O4 D4
10
Data Input
O2 7 10 D3 D3
6
D2 8
Gnd 8 9 O3 4
D1
(b) Pin connection (c) Logic symbol

Fig. 4.14
4.7 Vertical and Horizontal Memory Expansion
• In computer applications operating large size programs needs large
memory capacity, means the number of words and word size be
greater. This requirement is not satisfied by a single available memory
IC chip, hence by incorporating several similar chips suitably large size
of word length and word capacity is obtained.
• Increasing word capacity of memory by combining similar memory
chips is vertical memory expansion whereas increasing word length of
memory by combining similar memory chip is called horizontal
memory expansion.
Vertical Memory Expansion:

• Memory capacity expansion connects memory devices together so
that the data width is unchanged but the address range increases.
The size of the data units is the same, but using number of data units
in cascade memory capacity increases. This is achieved by applying
external logic to have only one memory device is active at a time and
the system must provide some means of distinguishing the two units.
• An inverter is used on the chip select line on one of the memory
devices, so that selecting one will automatically de-select the other.
• Typical block diagram for vertical memory expansion is shown in
Fig. 4.15.
ROM 2M ´ 8
Address RAM Address RAM 1
bus 20 bits bus 20 bits
1M ´ 8 1M ´ 8
21 bits EN
Data 8 bits
8 bits
bus
Control Control
bus bus
8 bits
Address RAM RAM 2
bus 20 bits 20 bits
1M ´ 8 1M ´ 8
8 bits Data EN 8 bits

bus
Control
bus
Fig. 4.15
• To obtain a memory of capacity m words, using memory chips with
M words each, the number of chips required is an integer next higher
to the value of m divided by M.
• Procedure to connect these memory chips to obtain vertical
expansion of memory is as described in following steps.
Step 1: Connect the corresponding address lines of each chip
individually.
Step 2: Connect read input (RD) of each chip together. Connect write
(WR) input together.
Step 3: Using decoder we can select chip select (CS) terminal of each
memory one by one for storing data.
Horizontal Memory Expansion:
• Word length expansion connects memory devices in parallel, so that
the address range is unchanged but the data storage wider. Word
length expansion usually requires external logic to implement, as the

memory devices operate in unison and therefore share all address,
data, and control lines.
• Typical block diagram for vertical memory expansion is shown in
Fig. 4.16.
65,536 ´ 8
Address ROM Address ROM 1
bus 16 bits 65,536 bus 16 bits
´4 Data
4 bits 4 bits
bus
Control Control
bus bus
Data
8 bits bus
Address ROM ROM 2
bus 16 bits 16 bits
65,536
´4 Data
4 bits bus 4 bits
Control
bus
Fig. 4.16
• With available word size of memory chip N and required word length
n (n > N), we have to combine similar memory chips together for
getting the desired word size n.
• The number of memory chips required is an integer next higher to
the value n divided by N.
• Procedure to connect these memory chips to obtain horizontal
expansion of memory is as described in following steps.
Step 1: Connect the corresponding address lines of each chip
individually i.e. A0, A1, A2, A3, … address lines to be connected together.
Step 2: Connect the read input (RD) of each memory chip together
which will act as the read input for overall combined memory.
Step3: Connect Write (WR) and Chip Select (CS) inputs of all chips
together.
• Using bidirection input and output lines common to all memory chips
horizontal memory expansion is achieved.
4.8 Role of Cache Memory
• The performance of a microcomputer can be improved significantly
by introducing a small inexpensive, but fast memory between the
microprocessor and main memory. This memory is called cache
memory.
• Cache memory is intended to give memory speed approaching that

of the fastest memories available and at the same time provide a
large memory size at the price of less expensive type of memories.
The Fig. 4.17 shows concept of cache memory.
Word Transfer Block Transfer
Cache
Main
CPU Memory
Fig. 4.17 : Memory organization with cache

• The cache contains a copy of portions of main memory. When the
processor attempts to read a word of memory, first check is made in
cache. If data is found in cache, it is called a cache hit and the data is
transferred to processor from the cache. If the data is not found in
cache, it is called cache miss.
• When there is cache miss, the main memory is accessed and data is
transferred to processor from the main memory. At the same time,
block of data containing the desired data is transferred from main
memory to cache.
• The block normally contains 4 to 16 words and the block is placed in
cache using First-In-First-Out (FIFO) technique. The block transfer is
done in hope that in future the references made by processor will be
confined to the cache. Sometimes cache is used for storing
instructions because unlike data instructions do not change.
Data Tag Block
Memory 0 Slot 0
Address number
1 Block 1
(K-words)
2 2
3 3
Block Block
n n
2 -1 2 -1
Word Block length
length (K-words)
Fig. 4.18 : Cache main memory structure
• The Fig. 4.18 shows the structure of a cache and main memory
n
system. For n-bit address the main memory will have 2 addressable
word. For mapping, the main memory is divided into fixed length
blocks M of K-word each. The cache consists of C block of K word
each called cache pages or lines. Each of the cache page is a subblock
of main memory (C << M).
• In general, a subset of the blocks of main memory is stored in the
cache. For reading memory, a block of memory is transferred to slot
of cache. But a cache has less slots, so same slots should be used for
storing a block. Thus, the slot has a tag to indicate the block currently
stored in the cache.
• If a physical address is generated by the processor, it is compared
with the tag (Address tag) of the cache. If it matches, there is cache
hit. On the other hand if it does not matches, there is cache miss,
then the blocks are copied into the cache from main memory. In this
process, Last Recently Used (LRU) method is employed for replacing
the data.
• The relationship between the cache and main memory block is
established using mapping technique : (i) Direct mapping (ii) Fully
associative mapping (iii) Set-associative mapping.
(i) Direct Mapping:
• One of the simplest memory mapping is direct mapping. In this, the
main memory address is divided into two fields an index field and a
tag field. The number of bits in the index field is equal to the number
of bits required to access the cache.
• If the main memory address is m-bit wide and the cache memory
address is n-bit wide, then index field is n-bit wide and tag field is
(m − n) bit wide. The each word in the cache includes data and its
associated tag.
• When address is generated by processor, first index address is used
for addressing cache. The tag field in the word read from cache is
compared with the tag field of main memory, If this matches, a cache
hit occurs. If a miss occurs, the data with new tag is written in the
cache from main memory.
• The main disadvantage of direct mapping is that, the cache hit ratio
drops sharply if two or more frequently used blocks happen to have
same index but different tags. This possibility is minimised by placing
such blocks far apart in the logical address space.
• The general mechanism for direct mapping is shown in Fig. 4.19.
Data Tag Data

Memory 0
Address
1 BO LO
Bn LM
n
2 -1
Word
length
(a) Main memory (b) Cache
Fig. 4.19 : Direct mapping
• For cache access, the main memory can be viewed as consisting of
three fields. The lowest bits identify the word or byte in the block of
main memory. The last part specifies the block of the main memory.
The middle part identifies the line of the cache.
Memory address
Tag Line Word
MSB LSB
Fig. 4.20 : Direct mapping address

(ii) Fully Associative Mapping :
• The fastest cache memory utilises an associative memory. The
method is known as fully associative mapping. Here main memory
addresses are stored in the cache alongwith the data. When a
memory address is generated by the processor, it is sent to the

associative memory where it is compared with all the addresses in the
cache.
• If there is a match, the data is read from associative cache memory
and sent to the processor. If a miss occurs, the address is forwarded
to the main memory which responds to the original processor
request. Same time, a block of words is send to cache. In associative
mapping, the address of data is stored in the cache. Thus, associative
cache is expensive although very fast.
• The Fig. 4.21 shows mechanism. Here address field is divided into tag
field and data field.
Memory address
Tag Word
MSB LSB
Fig. 4.21 : Fully associative mapping

(iii) Set-Associative Mapping:
• A set-associative mapping uses both fully associative and direct
mapping. It generally uses fully associative mapping and direct
mapping as a special case. Each word in cache stores two or more
main memory words using the same index address. Each memory
word consists of a tag and its data word.
• When the processor generates memory address, the index is used as
cache address. The tag field is compared with tags stored. If a match
occurs, the desired data word is read. If a miss occurs, the data is read
from the main memory and also written into the cache with its tag.
The hit ratio improves as the set size increases.
4.9 Virtual Memory
• The main memory available to processor is called real or physical
memory. On other hand, the 'virtual memory' mean which appear to
be present but actually it is not. The virtual memory technique allows
users to use more memory for a programme than the real memory of
computer.
• In this case, secondary memory is used and currently needed data is

transferred from secondary memory to the main memory for
execution. After execution of program, the program alongwith the
results are sent back to the secondary memory. After this, the
processor takes another part of the program for execution.
• Thus, main memory always keeps only the currently needed part of
the program. Such transfer of data from main memory to secondary
memory is called swapping. Thus, by swapping a program requiring
more memory space than the main memory can be executed.
• In virtual memory technique, a process is broken up into pages and
each page is brought in only when it is needed, on demand of
processor.
• Virtual memory allows for very effective multiprogramming and
breaks the barrier due to size of main memory.
• In virtual-memory system, there is Logical address space L and actual
address used in main memory called Physical address space P. The L
may be larger than P, hence called virtual memory.
• While actual execution, the logical address is to be translated into a
physical address. Thus, a mapping technology f : L → P is to be
implemented. If it is found that required information is not in main
memory, it is transferred from secondary to main memory.
(a) Paging : It is convenient to divide main memory into fixed size
contiguous areas, called page frames and to divide programs into pieces
of the same size, called pages. Here principle of demand paging is used
i.e. a page is brought to processor when it is needed (demanded). For
avoiding unnecessary load, only few pages are loaded in the main
memory. But, if a required data (page) is not found in main memory, a
page fault is triggered. This indicates the processor to bring in the desired
page. The execution of the program is suspended until the desired page
is brought into the main memory. In between, the processor can continue
with other programs, while page swapping is taking place. As a page
swapping is an I/O operation, it can be controlled by I/O processors.
When a page is brought in the main memory the Least Recently Used
page or unused page is thrown out. This is called thrashing. Thus,
swapping of unwanted pages should be avoided.
The Fig. 4.22 shows typical demand paging algorithm.
Start
Process
Compute physical
address A of next
word required
Fetch
the data
Is
A in memory
Yes
Program execution
No suspended
Is
there a page No Select page
frame in to be thrashed
memory
Yes
No Is
it altered
Yes
Transfer to
secondary memory
Transfer page
containing A from
secondary memory
Fig. 4.22 : Demand paging system

(b) Segmentation : The other way of dividing the addressable
memory is called the segmentation. The paging is invisible to the
programmer, whereas segmentation is visible to the user. Segmentation
provides a convenient method for organizing programs and data. The
segments are dynamic i.e. variable in size. Generally, a programmer or
operating system will break program and data into segments. So one has
number of program segments and data segments. The memory address
consists of segment number alongwith the offset.
The segmentation has following advantages over paging :

(a) Simplifies the handling of growing data structures as the
operating system will expand or shrink the segments as needed.
(b) A program can be altered and recompiled independently.
(c) A segment can be shared among processes.
(d) A segment can be constructed to contain well-defined set of
programs or data, the programmer can give privileges in
convenient fashion.
Memory Management Concept :
• As the massive amount of information is to be stored in a computer,
one needs a disk (optical or magnetic). If every time the reference is
made to disk the process will slow down to an unacceptable level.
• The solution is to use a large and fast semiconductor memory, but
the cost is very high. So a combination of main memory and
secondary memory should be used in a system. There should be a
separate mechanism for transfer of data between main memory and
secondary memory.
• The mechanism must transfer data efficiently, must keep track of data
usage. This needs a separate device located between processor and
memory. As the device manages memory configuration, it is called
Memory Management Unit (MMU).
• The MMU reduces burden on the operating system. The MMU
translates logical program addresses to physical memory addresses.
This is done by the substitution technique or by adding an offset to
each logical address to obtain the corresponding physical address.
• Memory is usually divided into small manageable "pages" and
"segments". The paging divides the memory into equal sized pages,
while segmentation divides the memory into variable sized segments.
This makes the address translation easier to implement.
• There are three ways to map logical addresses to physical addresses.
1. Paging
2. Segmentation
3. Combination of paging and segmentation.
• In pages system, a user has to access a larger address space than
main memory provides. The virtual memory technique is managed by
both software and hardware. The MMU, the hardware, handles the
address translation while memory management software of operating
system replaces the page as per the requirement.
• The software removes a desired page from main memory to make

space for new page from secondary memory at right time and placing
at right place. The replacement policies are First-In-First-Out (FIFO)
and Least Recently Used (LRU).
• In segmentation, the MMU uses the segment selector to obtain a
descriptor which contains the physical address for a segment. After
getting logical address from the process, the MMU checks the
segment in physical memory.
• If it is, the MMU adds an offset component to the segment base
component of the address obtained from the segment descriptor to
provide the physical address. The MMU generates physical address
for selecting the memory.
• If the MMU does not find the logical address in physical memory, it
interrupts the processor and the processor brings the desired
program from a secondary memory to the physical memory.
Think Over It
• Assume human mind as processor and brain as memory device

and try to define types of memories used in our life.
• Think over role of cache memory as serving food at huge dinner
party.
• Prepare chart for memory devices starting from latch to pen
drive, cloud storage etc.
Summary
1. The memory unit that communicates directly within the CPU, Auxiliary
memory and Cache memory, is called main memory. Main memory is
also called as core memory.
2. The main memory of computer consists of RAM, ROM, EPROM,
EEPROM.
3. The performance of a microcomputer can be improved significantly
by introducing a small inexpensive, but fast memory between the
microprocessor and main memory. This memory is called cache
memory.
4. Devices that provide backup storage like magnetic disc, CD are called
auxiliary memory.
5. The basic element of memory is memory cell.
6. The data or contents of the main memory that are used again and
again by CPU, are stored in the cache memory.
7. Virtual memory is a system where all physical memory is controlled
by the operating system.
8. Memory is an essential part of computer which stores data and
instructions required for its operation.
9. A processor is a semiconductor device and operates at very high
speed.
10. Semiconductor memories are faster, smaller in size and light in
weight, but relatively costly, whereas magnetic or optical memories
are cheaper but are slow in comparison with semiconductor
memories.
11. The memory can be divided into following main groups, Internal
Processor Memory, Cache Memory, Main Memory, Secondary or
Auxiliary Memory.
12. Memory Device Characteristics are cost, access time, access mode,
reliability, power consumption, package density, alterability,
permanence of storage, cycle time and data transfer rate and physical
characteristics.
13. The main constraints while designing a memory are size, speed and
cost.
14. In an associative memory any stored item can be accessed directly by
using the contents of the item in the question, generally some
specified subfield as an address.
15. The auxiliary memory is also called secondary memory or backing
memory.
16. Secondary memory is generally used for supporting the main
memory.
17. Secondary memory is a slow, low cost and larger in capacity.
18. The main memory available to processor is called real or physical
memory.
19. The 'virtual memory' means which appear to be present but actually it
is not.
20. The virtual memory technique allows users to use more memory for a
programme than the real memory of computer.
21. It is convenient to divide main memory into fixed size contiguous
areas, called page frames and to divide programs into pieces of the
same size, called pages.
22. The way of dividing the addressable memory is called the
segmentation.
23. The paging is invisible to the programmer, whereas segmentation is
visible to the user.
24. Segmentation provides a convenient method for organizing
programs and data.
25. The segments are dynamic i.e. variable in size.
26. There are three ways to map logical addresses to physical addresses,
paging,
27. Segmentation and Combination of paging and segmentation.
Exercise
[A] True or False :
1. Cache memory is the onboard storage.
2. Main memory is used for storing currently needed instructions and
data of program.
3. Cost of a memory unit decides the price of complete memory device.
4. In RAM we can read or write data at any given memory location.
5. ROM is used to store library subroutine, system programs and
function tables.
6. Logical address space can be larger than physical address space.
7. The auxiliary memory is also called as temporary memory.
8. The paging is invisible to the programmer, whereas segmentation is
visible to the user.
9. Secondary memory is fast and cheaper than main memory.
10. The way of dividing the addressable memory is called the paging.
11. Virtual memory is a system where all physical memory is controlled
by the processor used in a system.
12. A processor is a semiconductor device and operates at very high
speed.

1. Any electronic holding place where data can be stored and retrieved
later whenever required is ……
(a) memory (b) drive
(c) disk (d) circuit
2. The fastest means of memory access for CPU is through ……
(a) registers (b) cache
(c) main memory (d) virtual memory
3. Devices that provide backup storage like magnetic disc, CD are called
……
(a) output device (b) auxiliary memory
(c) cache memory (d) virtual memory
4. Speed of operation of microcomputer depends on ……
(a) cache memory (b) auxiliary memory
(c) virtual memory (d) processor
5. The basic element of memory is ……
(a) size (b) speed
(c) memory cell (d) processor
6. Cache memory is intended to give ……
(a) more storage (b) accuracy
(c) memory speed (d) backup
7. Dividing main memory into fixed size continuous areas is called ……
(a) page frame (b) memory frames
(c) pages (d) local page
8. Any program, no matter how small, occupies an entire partition. This
is called ……
(a) fragmentation (b) prior fragmentation
(c) internal fragmentation (d) external fragmentation
9. A set of hard disk drives with a controller mounted in a single box,

forming a single large storage unit is ……
(a) disk array (b) drives
(c) compact drives (d) multi-cores
10. Storage which stores or retains data after power off is called ……
(a) volatile storage (b) non-volatile storage
(c) sequential storage (d) direct storage
1. Explain: The role of memory in a computer system.
2. What are different types of memories used in a computer system?

Explain any one in detail.
3. Write a short note on memory device characteristics.
4. “The memory device characteristics helps in designing a memory

system”, elaborate.
5. Why memory hierarchy is required?
6. How memory hierarchy affects the performance? Explain.
7. What is main memory in computer? State its importance.
8. What are different types of memories used as main memory?
9. Write short notes on RAM organization, ROM organization.
10. What is need for cache memory? How a cache is organized?
11. What are different mapping techniques used in cache?
12. Write a short note on associative memory.
13. What is auxiliary memory? Explain magnetic tape in brief.
14. Write short note on Floppy disk, Hard Disk.
15. How virtual memory is implemented? Explain in detail.
16. Give concepts used in memory management.

1. Define memory device.
2. What is main memory in microcomputer system?
3. List names of auxiliary memory devices.
4. What is advantage of Cache memory?
5. Define: Concept of virtual memory.
6. State groups of memory used in microcomputer system.
7. List memory device characteristics.
8. Differentiate between volatile and non-volatile memory.
9. Define memory hierarchy in computer system. Why it is essential.
10. Differentiate between RAM and ROM.
11. Describe Data Read/Write concept in memory cell.
12. Discuss main role of cache memory in microcomputer.
13. What is memory mapping? List its types.
14. What is virtual memory? State its advantage.
15. Differentiate between paging and segmentation in memory mapping.
Answers
[A] True or False :
(4) True (5) True (6) True
(7) False (8) True (9) False
(10) False (11) False (12) True

1. (a) 2. (a) 3. (b) 4. (d) 5. (c) 6. (c) 7. (a)
8. (c) 9. (a) 10. (b)
April 2015
1. Discuss Memory Hierarchy with diagrams.

2. Define volatile and non-volatile memory.
April 2017
1. Define ‘Storage Capacity’ of memory.

2. Name any two cache memory mapping techniques.
3. Explain paging technique of virtual memory mapping.
4. What is need of cache memory?
5. Write tasks performed by operating system under memory
management.
October 2017
1. Draw and explain two level, three level memory hierarchy.
April 2018
1. What is virtual memory?

2. Draw two level memory hierarchy.
3. List various dynamic allocation memory management methods.
✍✍✍
SAMPLE QUESTION PAPER - I
Total Marks : 35 Time : 2 Hours
Note:
(a) Q. 1 is compulsory.
(b) Solve any three questions from Q. 2 to Q. 5.
(c) Questions 2 to 5 carry equal marks.
Q.1. Solve any Five of the following: [5]

(a) What is flip flop?
(b) What is synchronous counter ?
(c) State TRUE or FALSE : Architectural attributes include the
instruction set.
(d) List types of control organization.
(e) Draw two level memory hierarchy.
(f) What is micro-programmed organization?
Q.2. [A] Draw the circuit symbol of J-K flip-flop with positive edge
triggering and with negative edge triggering. [6]
[B] State the different applications of shift register. [4]
Q.3. [A] What do you mean by modulus of a counter? Construct
mod-7 counter. Show logic diagram, timing diagram and count
sequence. [6]
[B] Explain with example I/O interface with computer system. [4]
Q.4. [A] How stack is implemented? Explain with an example of
implementation of PUSH and POP. [6]
[B] What are different types of memories used in a computer
system? Explain any one in detail. [4]
Q.5. Write short notes on any FOUR of the following: [10]
(a) Memory device characteristics.
(b) Associative memory.
(c) General register organization.
(d) Ring counter.
(e) Limitations of RS flip-flop.
(f) Hardwired control design.
✍✍✍
P.1
SAMPLE QUESTION PAPER - II
Total Marks : 35 Time : 2 Hours
Note:
(a) Q. 1 is compulsory.
(b) Solve any three questions from Q. 2 to Q. 5.
(c) Questions 2 to 5 carry equal marks.
Q.1. Solve any Five of the following: [5]

(a) What is asynchronous counter ?
(b) Define R and S inputs in RS flip-flop.
(c) What are four modes of shift register?
(d) State TRUE or FALSE : The RPN expression is evaluated from
right to left .
(e) What is hardwired control?
(f) Why memory hierarchy is required?
Q.2. [A] What is race around condition? Which Flip-Flop exhibits this
condition? How can race around condition be eliminated? [6]
[B] Draw logic diagram of shift register as ring counter. Explain its
action. [4]
Q.3. [A] Draw the circuit diagram of 3-bit up-down counter. Explain its
action with state table and timing diagram. [6]
[B] Explain Wilke’s design. [4]
Q.4. [A] Explain Infix and Prefix representation of an expression. Give
suitable example. [6]
[B] What is need for cache memory? How a cache is organized? [4]
Q.5. Write short notes on any FOUR of the following: [10]
(a) Master slave JK flip-flop.
(b) Concept of modulus counters.
(c) Stack implementation in memory organization.
(d) Hardwired control design.
(e) Floppy disk, Hard disk.
✍✍✍
P.2

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ELC - 122

S. R. Chaudhari Dr. J. A. Bangali

Prof. (Dr.) M. L. Dongare Prof. (Dr.) P. B. Buchade

Published By: Polyplate Printed By:

1. Flip-Flops 1.1 − 1.18

2. Shift Registers and Counters 2.1 − 2.32

3. Basics of Computer System 3.1 − 3.46

4. Memory Organization 4.1 − 4.36

Model Question Papers P.1 - P.2

(a) S-R flip-flop using NAND gates (b) Truth table

• Case (ii) S = 1, R = 0 : Then output of N3 is 0 and output of N4 is 1.

(a) S-R flip-flop using NAND gates (b) Truth table

(a) J-K flip-flop (b) Truth table

1.4.2 Preset and Clear

• Table 1.2 summarises the operation of preset and clear input.

Fig. 1.7 : J-K flip-flop with edge triggering

1.4.5 Master Slave J-K Flip-Flop

Fig. 1.12 : T flip-flop output

• Can we use two or more master J-K flip-flop cascaded as a shift

3. A flip-flop is a bistable device and have two stable states.

4. A flip-flop is in the toggle condition when ……

12. What is meaning of TOGGLE when J=1, K=1 in JK flip-flop.

• Flip-flops are connected in such a way that binary number can be

Parallel data output

Fig. 2.2 : Serial in serial out shift register

• Thus, before the application of the clock pulse,

QA QB QC QD = 1000 after one clock pulse

= 0100 after two clock pulses

= 0010 after three clock pulses

= 0001 after four clock pulses, i.e. serially out

= 0000 after fifth clock pulses, new data to be entered

Fig. 2.4 : Serial in parallel out shift register

2.2.3 Parallel In Serial Out Register

Fig. 2.11 : 4-bit ring counter waveforms

2.4 Counters - Synchronous and Asynchronous

• Synchronous counter : A type of counter in which each stage is

2.4.1 Asynchronous Counter

• Fig. 2.12 shows the circuit of 4-bit binary counter.

• As seen, it is obtained by cascading the flip-flops such that output of

Fig. 2.12 : 4-bit binary counter

• Note that, the output of A flip-flop drives the B flip-flop. B flip-flop

• When clock pulse is applied and it goes negative, flip-flop A changes

• A flip-flop has to change the state to trigger B flip-flop. B has to

• In working of asynchronous counter before application of any

(c) Timing diagram

• If we have to build mod 16 parallel counter, we require 4 flip-flops

(a) Logic diagram of mod 7 synchronous counter

Synchronous (parallel) counter Asynchronous (ripple) counter

2.5 3-bit Up, Down and Up-Down Counter

• The output of the flip-flops is a binary number equivalent to the

• Fig. 2.18 shows the circuit of 3-bit down counter.

Fig. 2.19 : Waveforms of 3-bit down counter

(a) 3-bit up-down counter

(b) Waveforms of up counter

(c) Waveforms of down counter

• The 4-bit binary counter contains 4 flip-flop counts through 16 states.

(a) Logic diagram

• List practical applications of shift registers and counters.