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SN65HVD1050-Q1

www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

EMC-OPTIMIZED CAN TRANSCEIVER


Check for Samples: SN65HVD1050-Q1

1FEATURES APPLICATIONS

2 Qualified for Automotive Applications • GMW3122 Dual-Wire CAN Physical Layer
• Customer-Specific Configuration Control Can • SAE J2284 High-Speed CAN for Automotive
Be Supported Along With Major-Change Applications
Approval • SAE J1939 Standard Data Bus Interface
• Improved Drop-In Replacement for TJA1050 • ISO 11783 Standard Data Bus Interface
• Meets or Exceeds the Requirements of • NMEA 2000 Standard Data Bus Interface
ISO 11898-2 • Industrial Automation
• GIFT/ICT Compliant – DeviceNet™ Data Buses (Vendor ID #806)
• ESD Protection up to ±8 kV (Human-Body
Model) on Bus Pins
DESCRIPTION
• High Electromagnetic Immunity (EMI) The SN65HVD1050 meets or exceeds the
specifications of the ISO 11898 standard for use in
• Low Electromagnetic Emissions (EME) applications employing a Controller Area Network
• Bus-Fault Protection of –27 V to 40 V (CAN). The device is qualified for use in automotive
• Dominant Time-Out Function applications.
• Thermal Shutdown Protection As a CAN transceiver, this device provides differential
• Power-Up/Down Glitch-Free Bus Inputs and transmit capability to the bus and differential receive
Outputs capability to a CAN controller at signaling rates up to
1 megabit per second (Mbps) (1).
– High Input Impedance With Low VCC
(1) The signaling rate of a line is the number of voltage
– Monotonic Outputs During Power Cycling transitions that are made per second expressed in the units
bps (bits per second).

FUNCTION BLOCK DIAGRAM


8
Silent Mode S
VCC VCC
5
3 30 µA VCC/2 Vref
Dominant Over-Temperature
Time Out Sensor

30 µA
7
1 CANH
TXD Driver 6
CANL

4
RXD

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 DeviceNet is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD1050-Q1
SLLS696C – MAY 2006 – REVISED DECEMBER 2010 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)
Designed for operation is especially harsh environments, the SN65HVD1050 features cross-wire, over-voltage,
and loss of ground protection from –27 V to 40 V, over-temperature protection, a –12-V to 12-V common-mode
range, and withstands voltage transients from –200 V to 200 V according to ISO 7637.
Pin 8 provides for two different modes of operation: high-speed or silent mode. The high-speed mode of
operation is selected by connecting S (pin 8) to ground.
If a high logic level is applied to the S pin of the SN65HVD1050, the device enters a listen-only silent mode
during which the driver is switched off while the receiver remains fully functional.
In silent mode, all bus activity is passed by the receiver output to the local protocol controller. When data
transmission is required, the local protocol controller reverses this low-current silent mode by placing a logic low
on the S pin to resume full operation.
A dominant time-out circuit in the SN65HVD1050 prevents the driver from blocking network communication with
a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge
is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the
next rising edge on TXD.
Vref (pin 5) is available as a VCC/2 voltage reference.
The SN65HVD1050 is characterized for operation from –40°C to 125°C.

SN65HVD1050

TXD 1 8 S
GND 2 7 CANH
VCC 3 6 CANL
RXD 4 5 Vref

ORDERING INFORMATION (1)


MARKED
PART NUMBER PACKAGE (2) ORDERING NUMBER
AS
SN65HVD1050-Q1 SOIC-8 H1050Q SN65HVD1050QDRQ1 (reel)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Application Hint: CAN Nodes Using Common-Mode Chokes


The SN65HVD1050 has been EMC optimized to allow use in CAN systems without a common-mode choke.
However, sometimes the CAN network and termination architecture may require their use. If a common-mode
choke is used in a CAN node where bus-line shorts to dc voltages may be possible, care should be taken in the
choice of common-mode choke (winding type, core type, and value) along with the termination and protection
scheme of the node and bus. During CAN bus shorts to dc voltages the inductance of the common-mode choke
may cause inductive flyback transients. Some combinations of common-mode chokes, bus termination, and
shorting voltages take the bus voltages outside the absolute maximum ratings of the device, possibly leading to
damage.

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SN65HVD1050-Q1
www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

ABSOLUTE MAXIMUM RATINGS (1)


over operating free-air temperature range (unless otherwise noted)
UNIT
VCC Supply voltage range (2) –0.3 V to 6 V
Voltage range at any bus terminal (CANH, CANL, Vref) –27 V to 40 V
IO Receiver output current 20 mA
VI Voltage input range, ac transient pulse (3) (CANH, CANL) –200 V to 200 V
VI Voltage input range (TXD, S) –0.3 V to 6 V
TJ Junction temperature range –40°C to 170°C
TA Operating free-air temperature range –40°C to 125°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637-1, test pulses 1, 2, 3a, 3b, 5, 6, and 7. ISO 7637-1 transient tests are ac only; if dc may be coupled
in with ac transients, externally protect the bus pins within the absolute maximum voltage range at any bus terminal (–27 V to 40 V). If
common-mode chokes are used in the system and the bus lines may be shorted to dc, ensure that the choke type and value in
combination with the node termination and shorting voltage either will not create inductive flyback outside of voltage maximum
specification or use an external transient-suppression circuit to protect the transceiver from the inductive transients

ELECTROSTATIC DISCHARGE PROTECTION


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS UNIT
Bus terminals and GND ±8 kV
Human-Body Model (2)
(1)
All pins ±4 kV
Electrostatic discharge
Charged-Device Model (3) All pins ±1.5 kV
Machine Model ±200 V

(1) All typical values at 25°C.


(2) Tested in accordance JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance JEDEC Standard 22, Test Method C101.

RECOMMENDED OPERATING CONDITIONS


MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
VIH High-level input voltage TXD, S 2 5.25 V
VIL Low-level input voltage TXD, S 0 0.8 V
VID Differential input voltage –6 6 V
Driver –70
IOH High-level output current mA
Receiver –2
Driver 70
IOL Low-level output current mA
Receiver 2
TJ Junction temperature See Thermal Characteristics table 150 °C

SUPPLY CURRENT
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Silent mode S at VCC, VI = VCC 6 10
ICC 5-V supply current Dominant VI = 0 V, 60-Ω load, S at 0 V 50 70 mA
Recessive VI = VCC, No load, S at 0 V 6 10

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3


SN65HVD1050-Q1
SLLS696C – MAY 2006 – REVISED DECEMBER 2010 www.ti.com

DEVICE SWITCHING CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Total loop delay, driver input to receiver output,
td(LOOP1) S at 0 V, See Figure 9 90 230 ns
recessive to dominant
Total loop delay, driver input to receiver output,
td(LOOP2) S at 0 V, See Figure 9 90 230 ns
dominant to recessive

DRIVER ELECTRICAL CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
CANH VI = 0 V, S at 0 V, RL = 60 Ω, See Figure 1 2.9 3.4 4.5
VO(D) Bus output voltage (dominant) V
CANL and Figure 2 0.8 1.5
VI = 3 V, S at 0 V, RL = 60 Ω, See Figure 1
VO(R) Bus output voltage (recessive) 2 2.3 3 V
and Figure 2
VI = 0 V, RL = 60 Ω, S at 0 V, See Figure 1,
1.5 3 V
Figure 2, and Figure 3
VOD(D) Differential output voltage (dominant)
VI = 0 V, RL = 45 Ω, S at 0 V, See Figure 1,
1.4 3 V
Figure 2, and Figure 3
VI = 3 V, S at 0 V, See Figure 1 and Figure 2 –0.012 0.012
VOD(R) Differential output voltage (recessive) V
VI = 3 V, S at 0 V, No Load –0.5 0.05
Steady state common-mode output
VOC(ss) 2 2.3 3 V
voltage
S at 0 V, Figure 8
Change in steady-state common-mode
ΔVOC(ss) 30 mV
output voltage
IIH High-level input current, TXD input VI at VCC –2 2
IIL Low-level input current, TXD input VI at 0 V –50 –10 mA
IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1
VCANH = –12 V, CANL open, See Figure 11 –105 –72
VCANH = 12 V, CANL open, See Figure 11 0.36 1
IOS(ss) Short-circuit steady-state output current mA
VCANL = –12 V, CANH open, See Figure 11 –1 –0.5
VCANL = 12 V, CANH open, See Figure 11 71 105
CO Output capacitance See receiver input capacitance

(1) All typical values are at 25°C with a 5-V supply.

DRIVER SWITCHING CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output S at 0 V, See Figure 4 25 65 120 ns
tPHL Propagation delay time, high-to-low level output S at 0 V, See Figure 4 25 45 120 ns
tr Differential output signal rise time S at 0 V, See Figure 4 25 ns
tf Differential output signal fall time S at 0 V, See Figure 4 50 ns
ten Enable time from silent mode to dominant See Figure 7 1 ms
t(dom) Dominant time out ↓VI, See Figure 10 300 450 700 ms

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SN65HVD1050-Q1
www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

RECEIVER ELECTRICAL CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
VIT+ Positive-going input threshold voltage S at 0 V, See Table 3 800 900 mV
VIT– Negative-going input threshold voltage S at 0 V, See Table 3 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
VOH High-level output voltage IO = –2 mA, See Figure 6 4 4.6 V
VOL Low-level output voltage IO = 2 mA, See Figure 6 0.2 0.4 V
CANH or CANL = 5 V,
II(off) Power-off bus input current Other pin at 0 V, 165 250 mA
VCC at 0 V, TXD at 0 V
IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 mA
TXD at 3 V,
CI Input capacitance to ground (CANH or CANL) 13 pF
VI = 0.4 sin (4E6pt) + 2.5 V
CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6pt) 5 pF
RID Differential input resistance TXD at 3 V, S at 0 V 30 80 kΩ
RIN Input resistance (CANH or CANL) TXD at 3 V, S at 0 V 15 30 40 kΩ
Input resistance matching
RI(m) V(CANH) = V(CANL) –3 0 3 %
[1 – (RIN (CANH) / RIN (CANL))] × 100%

(1) All typical values are at 25°C with a 5-V supply.

RECEIVER SWITCHING CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 60 100 130 ns
tPHL Propagation delay time, high-to-low-level output 45 70 130 ns
S at 0 V or VCC, See Figure 6
tr Output signal rise time 8 ns
tf Output signal fall time 8 ns

S PIN CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High level input current S at 2 V 20 40 70 mA
IIL Low level input current S at 0.8 V 5 20 30 mA

VREF PIN CHARACTERISTICS


over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Reference output voltage –50 mA < IO < 50 mA 0.4 VCC 0.5 VCC 0.6 VCC V

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5


SN65HVD1050-Q1
SLLS696C – MAY 2006 – REVISED DECEMBER 2010 www.ti.com

THERMAL CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-K thermal resistance (1) 211
qJA Junction-to-air thermal resistance °C/W
High-K thermal resistance 131
qJB Junction-to-board thermal resistance 53 °C/W
qJC Junction-to-case thermal resistance 79 °C/W
VCC = 5 V, TJ = 27°C, RL = 60 Ω, S at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave, 112
CL at RXD = 15 pF
PD Average power dissipation mW
VCC = 5.5 V, TJ = 130°C, RL = 45 Ω, S at 0 V,
Input to TXD at 500 kHz, 50% duty cycle square wave, 170
CL at RXD = 15 pF
Thermal shutdown temperature 190 °C

(1) Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.

FUNCTION TABLES

Table 1. DRIVER (1)


INPUTS OUTPUTS
BUS STATE
TXD S CANH CANL
L L or Open H L Dominant
H X Z Z Recessive
Open X Z Z Recessive
X H Z Z Recessive

(1) H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impedance

Table 2. RECEIVER (1)


DIFFERENTIAL INPUTS OUTPUT
BUS STATE
VID = V(CANH) – V(CANL) RXD
VID ≥ 0.9 V L Dominant
0.5 V < VID < 0.9 V ? ?
VID ≤ 0.5 V H Recessive
Open H Recessive

(1) H = high level, L = low level, X = irrelevant, ? = indeterminate, Z = high impedance

6 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated


SN65HVD1050-Q1
www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

PARAMETER MEASUREMENT INFORMATION


IO(CANH) Dominant
 3.5 V VO(CANH)

TXD VO (CANH)
II RL
VOD
VO(CANH) + VO(CANL) Recessive  2.5 V
2
S I I(S)
VI VOC
+ I O(CANL)
VI(S) V O(CANL)
_  1.5 V VO(CANL)

Figure 1. Driver Voltage, Current, and Test Figure 2. Bus Logic State Voltage Definitions
Definition
330 W +1%
CANH

TXD
0V VOD RL
+
_ −2 V 3 VTEST 3 7 V
S
CANL
330 W +1%

Figure 3. Driver VOD Test Circuit


CANH
VCC
VI
VCC/2 VCC/2

TXD 0V
RL = 60 W VO
±1% tPLH tPHL
CL = 100 pF VO(D)
VI (see Note B) 90%
0.9 V
VO 0.5 V
S 10%
VO(R)
(See Note A) CANL tr tf

Figure 4. Driver Test Circuit and Voltage Waveforms

CANH
VI (CANH) RXD
IO
VID
V + VI (CANL)
VIC = I (CANH)
2
VO
VI (CANL) CANL

Figure 5. Receiver Voltage and Current Definitions

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 7


SN65HVD1050-Q1
SLLS696C – MAY 2006 – REVISED DECEMBER 2010 www.ti.com

PARAMETER MEASUREMENT INFORMATION (continued)

CANH 3.5 V
VI 2V 2.4 V
RXD IO
VI 1.5 V
tPLH tPHL
CANL VOH
(See Note A) 1.5 V CL = 15 pF ±20% 90% 0.75 VCC
VO
STB (See Note B) VO 0.25 VCC
10% VOL
tr tf

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 6. Receiver Test Circuit and Voltage Waveforms

Table 3. Differential Input Voltage Threshold Test


INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L
12 V 11.1 V 900 mV L
VOL
–6 V –12 V 6V L
12 V 6V 6V L
–11.5 V –12 V 500 mV H
12 V 11.5 V 500 mV H
–12 V –6 V 6V H VOH
6V 12 V 6V H
Open Open X H

DUT

CANH VCC
(B)
TXD (A) 60 W VI 0.5 VCC
0V CL
±1% 0V

STB CANL
VI VOH

VO 0.5 VCC
RXD VOL
ten
+
VO
_ 15 pF ± 20%

A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.


B. All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 7. ten Test Circuit and Waveforms

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SN65HVD1050-Q1
www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

CANH

TXD
VI RL VO(CANH) + VO(CANL) VOC(SS)
VOC =
2
VOC
STB CANL VO(CANH)
VO(CANL)

NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 8. Common-Mode Output Voltage Test and Waveforms

DUT

CANH VCC
TXD Input 0.5 VCC
(B) TXD (A)
60 W
VI CL 0V
± 1%
tloop2 tloop1
S CANL VOH
0.5 VCC 0.5 VCC
RXD Output
RXD VOL

VO
_ 15 pF ± 20%

A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.


B. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 9. t(LOOP) Test Circuit and Waveforms

CANH
VCC
VI
TXD
RL = 60 W CL
(B)
VOD 0V
±1%
VI
(A) VOD(D)
VOD
900 mV
STB 500 mV
CANL 0V
tdom

A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.

Figure 10. Dominant Time-Out Test Circuit and Waveforms

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 9


SN65HVD1050-Q1
SLLS696C – MAY 2006 – REVISED DECEMBER 2010 www.ti.com

| IOS(SS) |
IOS | IOS(P) |

CANH 200 ms
TXD
0V
0 V or VCC
12 V
S CANL −12 V or 12 V
VIN Vin
0V

or 10 ms

0V
Vin

−12 V

Figure 11. Driver Short-Circuit Current Test and Waveforms

10 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated


SN65HVD1050-Q1
www.ti.com SLLS696C – MAY 2006 – REVISED DECEMBER 2010

Equivalent Input and Output Schematic Diagrams

TXD Input RXD Output


VCC
VCC

4.3 kW 25 W
Input Output

6V 6V

CANH Input CANL Input


VCC VCC

10 kW 10 kW
20 kW 20 kW
Input Input

10 kW 10 kW
40 V
40 V

S Input CANH and CANL Outputs


VCC VCC

4.3 kW CANH
Input CANL

6V 40 kW 40 V 40 V

Vref Output
VCC

2 kW
Output

2 kW
40 V

Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 11


PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)

SN65HVD1050QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 H1050Q
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD1050-Q1 :

• Catalog: SN65HVD1050

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

• Enhanced Product: SN65HVD1050-EP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product


• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD1050QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD1050QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 18-Aug-2014

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD1050QDRQ1 SOIC D 8 2500 367.0 367.0 35.0
SN65HVD1050QDRQ1 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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