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TPS54540
SLVSBX7B – MAY 2013 – REVISED MARCH 2017

TPS54540 4.5-V to 42-V Input, 5 A, Step Down DC-DC Converter

with Eco-mode™
1 Features 3 Description
1• High Efficiency at Light Loads with Pulse Skipping The TPS54540 is a 42 V, 5 A, step down regulator
Eco-mode™ with an integrated high side MOSFET. The device
survives load dump pulses up to 45V per ISO 7637.
• 92-mΩ High-Side MOSFET Current mode control provides simple external
• 146 μA Operating Quiescent Current and compensation and flexible component selection. A
2 μA Shutdown Current low ripple pulse skip mode reduces the no load
• 100 kHz to 2.5 MHz Fixed Switching Frequency supply current to 146 μA. Shutdown supply current is
reduced to 2 μA when the enable pin is pulled low.
• Synchronizes to External Clock
• Low Dropout at Light Loads with Integrated BOOT Undervoltage lockout is internally set at 4.3 V but can
be increased using the enable pin. The output voltage
Recharge FET
start up ramp is internally controlled to provide a
• Adjustable UVLO Voltage and Hysteresis controlled start up and eliminate overshoot.
• 0.8 V 1% Internal Voltage Reference
A wide switching frequency range allows either
• 8-Terminal HSOP with PowerPAD™ Package efficiency or external component size to be optimized.
• –40°C to 150°C TJ Operating Range Output current is limited cycle-by-cycle. Frequency
• Create a Custom Design using the TPS54540 with foldback and thermal shutdown protects internal and
external components during an overload condition.
the WEBENCH® Power Designer
The TPS54540 is available in an 8-terminal thermally
2 Applications enhanced HSOP PowerPAD™ package.
• Industrial Automation and Motor Control Device Information
• Vehicle Accessories: GPS, Entertainment PART NUMBER PACKAGE BODY SIZE
• USB Dedicated Charging Ports and Battery TPS54540 HSOP (8) 4,89mm x 3,9mm
Chargers
• 12 V and 24 V Industrial, Automotive and
Communications Power Systems
spacer
Simplified Schematic
Efficiency vs Load Current
VIN
VIN BOOT 100
36 V to 12 V
TPS54540 95

VOUT 90
EN SW
Efficiency (%)

85
COMP 12 V to 3.3 V
80
12 V to 5 V
RT/CLK 75
FB

70
GND
65 VOUT = 12 V, fsw = 800 kHz
VOUT = 5 V and 3.3 V, fsw = 400 kHz
Copyright © 2017, Texas Instruments Incorporated 60
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO - Output Current (A) C024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 23
2 Applications ........................................................... 1 8 Application and Implementation ........................ 25
3 Description ............................................................. 1 8.1 Application Information............................................ 25
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 25
5 Pin Configuration and Functions ......................... 4 9 Power Supply Recommendations...................... 36
6 Specifications......................................................... 5 10 Layout................................................................... 37
6.1 Absolute Maximum Ratings ...................................... 5 10.1 Safe Operating Area ............................................. 37
6.2 ESD Ratings.............................................................. 5 10.2 Layout Guidelines ................................................. 38
6.3 Recommended Operating Conditions....................... 5 10.3 Layout Example .................................................... 38
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 39
6.5 Electrical Characteristics........................................... 6 11.1 Custom Design with WEBENCH® Tools .............. 39
6.6 Timing Requirements ................................................ 7 11.2 Receiving Notification of Documentation Updates 39
6.7 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 39
7 Detailed Description ............................................ 11 11.4 Trademarks ........................................................... 39
7.1 Overview ................................................................. 11 11.5 Electrostatic Discharge Caution ............................ 39
7.2 Functional Block Diagram ....................................... 12 11.6 Glossary ................................................................ 39
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 39

4 Revision History
Changes from Revision A (March 2014) to Revision B Page

• Added the WEBENCH information in the Features, Detailed Design Procedure, and Device Support sections .................. 1
• Changed the Handling Ratings table To ESD Ratings table.................................................................................................. 5
• Changed VIN MIN Value From: 4.5 V To: VO + VDO, and added Note 1 in the Recommended Operating Conditions .......... 5
• Deleted last graph: "5 V Start and Stop Voltage" from the Typical Characteristics ............................................................. 10
• Updated text and added Equation 1 in the Low Dropout Operation and Bootstrap Voltage (BOOT) ................................. 13
• Deleted text: "The start and stop voltage for a typical 5 V..." from the Low Dropout Operation and Bootstrap Voltage
(BOOT) section..................................................................................................................................................................... 13
• Changed Equation 7 and Equation 8. ................................................................................................................................. 15
• Changed Equation 27 .......................................................................................................................................................... 26
• Added new section: Minimum VIN ......................................................................................................................................... 31
• Deleted 2 graphs named "Low Dropout Operation" from the Application Curves section .................................................. 33

Changes from Original (May 2013) to Revision A Page

• Added Device Information table, Recommended Operating Conditions table, Pin Configuration and Functions
section, Handling Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
• Changed the Electrical Characteristics Conditions From: VIN = 4.5 to 60 V To: VIN = 4.5 to 42 V...................................... 6
• Changed the Operating: nonswitching supply current TEST CONDITIONS From: FB = 0.83 V To: FB = 0.9 V .................. 6
• Changed RT/CLK high threshold MAX value From: 1.7 V To: 2 V ....................................................................................... 6
• Changed the title of graph "5 V Start and Stop Voltage" to include a link to the Low Dropout Operation section. ............ 10
• Changed the FBD, removed the Logic block and Shutdown signal from the OV comparator ............................................. 12
• Changed VF = Forward Drop of the Catch Diode To: VD = Forward Drop of the Catch Diode .......................................... 14
• Deleted value TSW = 1 / Fsw from the list following Equation 2 ......................................................................................... 14
• Changed VB2SW = VBOOT + VF To: VB2SW = VBOOT + VD ........................................................................................... 14
• Changed VBOOT = (1.41 x VIN - 0.554 - VF / TSW - 1.847 x 103 x IB2SW) / (1.41 + 1 / Tsw) To: VBOOT = (1.41 x

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VIN - 0.554 - VD x ƒSW - 1.847 x 103 x IB2SW) / (1.41 + ƒSW)............................................................................................... 14

• Deleted figure: "5V Start/Stop Voltage" ................................................................................................................................ 14
• Added a title to Figure 23 ..................................................................................................................................................... 14
• Changed the section title From: Selecting the Switching Frequency To: Accurate Current Limit Operation and
Maximum Switching Frequency............................................................................................................................................ 16
• Changed text in the Synchronization to RT/CLK terminal section From: "0.5 V and higher than 1.7 V" To: "0.5 V and
higher than 2 V" ................................................................................................................................................................... 17
• Changed Equation 33 From: (5.13V2 - 5 V2) To: 3.43 V2 - 3.3 V2) ...................................................................................... 28
• Changed Figure 36, VOUT From: 200 mV/div To 100 mV/div ............................................................................................ 33
• Changed Figure 38 , EN From: 1 V/div To: 2 V/div, VOUT From: 4 V/div To: 2 V/div, and Time = 2 ms/div To: Time
= 20 ms/div ........................................................................................................................................................................... 33
• Changed Figure 39 , VOUT From: 4 V/div To: 2 V/div......................................................................................................... 33

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5 Pin Configuration and Functions

HSOIC Package
(Top View)

BOOT 1 8 SW

VIN 2 7 GND
PowerPAD
9
EN 3 6 COMP

RT/CLK 4 5 FB

Pin Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the minimum
BOOT 1 O
required to operate the high side MOSFET, the output is switched off until the capacitor is refreshed.
VIN 2 I Input supply voltage with 4.5 V to 42 V operating range.
Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the
EN 3 I
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper
RT/CLK 4 I threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is
disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB 5 I Inverting input of the transconductance (gm) error amplifier.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
COMP 6 O
compensation components to this terminal.
GND 7 – Ground
SW 8 I The source of the internal high-side power MOSFET and switching node of the converter.
Thermal GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper
9 –
Pad operation.

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN –0.3 45
EN –0.3 8.4
BOOT 53
Input voltage V
FB –0.3 3
COMP –0.3 3
RT/CLK –0.3 3.6
BOOT-SW 8
Output voltage SW –0.6 45 V
SW, 10-ns Transient –2 45
Operating junction temperature, TJ –40 150 °C
Storage temperature, TSTG –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
(2)
(1)
Human Body Model (HBM) ESD Stress Voltage ±2000 V
VESD (3)
Charged Device Model (HBM) ESD Stress Voltage ±500 V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
(1)
VIN Supply input voltage VO + VDO 42 V
VO Output voltage 0.8 41.1 V
IO Output current 0 5 A
TJ Junction Temperature –40 150 °C

(1) See Equation 1

6.4 Thermal Information

TPS54540
THERMAL METRIC (1) (2) UNIT
DDA (8 PINS)
θJA Junction-to-ambient thermal resistance (standard board) 42.0 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 23.4 °C/W
θJCtop Junction-to-case(top) thermal resistance 45.8 °C/W
θJCbot Junction-to-case(bottom) thermal resistance 3.6 °C/W
θJB Junction-to-board thermal resistance 23.4 v

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

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6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN TERMINAL)
Operating input voltage 4.5 42 V
Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V
Internal undervoltage lockout threshold
325 mV
hysteresis
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V 2.25 4.5
μA
Operating: nonswitching supply current FB = 0.9 V, TA = 25°C 146 175
ENABLE AND UVLO (EN TERMINAL)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Enable threshold +50 mV –4.6
Input current μA
Enable threshold –50 mV –0.58 –1.2 –1.8
Hysteresis current –2.2 –3.4 –4.5 μA
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μMhos
Error amplifier transconductance (gM) during
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μMhos
soft-start
Error amplifier dc gain VFB = 0.8 V 10,000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±30 μA
COMP to SW current transconductance 17 A/V
CURRENT LIMIT
All VIN and temperatures, Open Loop (1) 6.3 7.5 8.8
Current limit threshold All temperatures, VIN = 12 V, Open Loop (1) 6.3 7.5 8.3 A
VIN = 12 V, TA = 25°C, Open Loop (1) 7.1 7.5 7.9
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Switching frequency range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency range using CLK mode 160 2300 kHz
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V

(1) Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.

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6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE AND UVLO (EN TERMINAL)
Enable to COMP active VIN = 12 V, TA = 25°C 540 µs
INTERNAL SOFT-START TIME
Soft-Start Time fSW = 500 kHz, 10% to 90% 2.1 ms
Soft-Start Time fSW = 2.5 MHz, 10% to 90% 0.42 ms
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 92 190 mΩ
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Minimum CLK input pulse width 15 ns
RT/CLK falling edge to SW rising edge
Measured at 500 kHz with RT resistor in series 55 ns
delay
PLL lock in time Measured at 500 kHz 78 μs

6.7 Typical Characteristics

0.25 0.814
RDSON - On-State Resistance ( )

0.809

VFB - Voltage Referance ( V)

0.2

0.804
0.15
0.799
0.1
0.794

0.05 BOOT-SW = 3 V 0.789

BOOT-SW = 6 V
0 0.784
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ - Junction Temperature (ƒC) C025 TJ - Junction Temperature (ƒC) C026

Figure 1. On Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

9 9
±40 ƒC
Series1
25 ƒC
Series2
8.5
High Side Switch Current (A)

8.5 150 ƒC
Series4
High Side Switch Current (A)

8 8

7.5
7.5

7
7

6.5
6.5
6
6 0 7 14 21 28 35 42
-50 -25 0 25 50 75 100 125 150 VI - Input Voltage (V) C028
TJ - Junction Temperature (qC)

Figure 4. Switch Current Limit vs Input Voltage

Figure 3. Switch Current Limit vs Junction Temperature

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Typical Characteristics (continued)

550 500
540 450

FSW - Switching Frequency (kHz)

FS - Switching Frequency (kHz)

530 400
520 350
510 300
500 250
490 200
480 150
470 100
460 50
450 0
±50 ±25 0 25 50 75 100 125 150 200 300 400 500 600 700 800 900 1000
TJ - Junction Temperature (ƒC) C029 RT/CLK - Resistance (k ) C030

Figure 5. Switching Frequency vs Junction Temperature Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range

2500 500
2300
FSW - Switching Frequency (kHz)

450
2100
1900
400
gm (µA/V)

1700
1500 350
1300
300
1100
900
250
700
500 200
0 50 100 150 200 ±50 ±25 0 25 50 75 100 125 150
RT/CLK - Resistance (k ) C031 TJ - Junction Temperature (ƒC) C032

Figure 7. Switching Frequency vs RT/CLK Resistance Figure 8. EA Transconductance vs Junction Temperature

High Frequency Range

120 1.3
1.29
110
1.28
100 1.27
1.26
EN - Threshold (V)

90
1.25
gm (µA/V)

80 1.24
1.23
70
1.22
60 1.21
1.2
50
1.19
40 1.18
1.17
30
1.16
20 1.15
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ - Junction Temperature (ƒC) C033 TJ - Junction Temperature (ƒC) C034

Figure 9. EA Transconductance During Soft-Start vs Figure 10. EN Terminal Voltage vs Junction Temperature
Junction Temperature

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Typical Characteristics (continued)

±3.5 ±0.5
±3.7 ±0.7
±3.9 ±0.9
±4.1 ±1.1
±4.3 ±1.3

IEN (µA)
IEN (uA)

±4.5 ±1.5
±4.7 ±1.7
±4.9 ±1.9
±5.1 ±2.1
±5.3 ±2.3
±5.5 ±2.5
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ - Junction Temperature (ƒC) C035 TJ - Junction Temperature (ƒC) C036

Figure 11. EN Terminal Current vs Junction Temperature Figure 12. EN Terminal Current vs Junction Temperature

±2.5 100
Series2
VSENSE Falling

% of Nominal Switching Frequency

±2.7
VSENSE Rising
Series4
±2.9
75
IEN - Hysteresis (µA)

±3.1
±3.3
±3.5 50
±3.7
±3.9
25
±4.1
±4.3
±4.5 0
±50 ±25 0 25 50 75 100 125 150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TJ - Junction Temperature (ƒC) C037 VSENSE (V) C038

Figure 13. EN Terminal Current Hysteresis vs Junction Figure 14. Switching Frequency vs VSENSE
Temperature

3 3
TJ =Series2
25ƒC
2.5 2.5

2 2
IVIN (µA)

IVIN (µA)

1.5 1.5

1 1

0.5 0.5

0 0
±50 ±25 0 25 50 75 100 125 150 0 7 14 21 28 35 42
TJ - Junction Temperature (ƒC) C039 VIN - Input Voltage (V) C040

Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
Temperature

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Typical Characteristics (continued)

210 210
TJSeries2
= 25ƒC
190 190

170 170
IVIN (µA)

IVIN (µA)
150 150

130 130

110 110

90 90

70 70
±50 ±25 0 25 50 75 100 125 150 0 7 14 21 28 35 42
TJ - Junction Temperature (ƒC) C041 VIN - Input Voltage (V) C042

Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage

2.6 4.5
BOOT-PH UVLO Falling UVLO Start Switching
2.5 BOOT-PH UVLO Rising 4.4 UVLO Stop Switching

2.4 4.3
VI - BOOT-PH (V)

2.3 VIN (V) 4.2

2.2 4.1

2.1 4.0

2.0 3.9

1.9 3.8

1.8 3.7
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ - Junction Temperature (ƒC) C043 TJ - Junction Temperature (ƒC) C044

Figure 19. BOOT-SW UVLO vs Junction Temperature Figure 20. Input Voltage UVLO vs Junction Temperature

10
12
12V,V,25ƒC
25 C
9
8
Soft-Start Time (ms)

7
6
5
4
3
2
1
0
100
100 300
300 500
500700
700900
9001100
11001300
13001500
15001700 1900
1700 2100
1900 2300
2100 2500
2300 2500
Switching Frequency (kHz) C045

Figure 21. Soft-Start Time vs Switching Frequency

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7 Detailed Description

7.1 Overview
The TPS54540 is a 42 V, 5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET. The
device implements constant frequency, current mode control which reduces output capacitance and simplifies
external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either
efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted
using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked loop (PLL)
connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of an external
clock signal.
The TPS54540 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to
adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up
current source enables operation when the EN terminal is floating. The operating current is 146 μA under no load
condition (not switching). When the device is disabled, the supply current is 2 μA.
The integrated 92 mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54540 reduces the
external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is
monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54540 to operate at high duty
cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of
the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54540 includes an internal soft-start circuit that slows the output rise time during start-up to reduce in-
rush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.

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7.2 Functional Block Diagram

EN VIN

Thermal
Shutdown UVLO
Enable
OV Comparator
Shutdown
Shutdown
Logic

Enable
Threshold
Boot
Charge
Voltage
Minimum Boot
Reference Current
Clamp UVLO
Sense
Pulse
Error Skip
Amplifier PWM
FB Comparator BOOT

Logic

Shutdown

Slope
6 Compensation

COMP SW

Frequency
Foldback
Reference
DAC for
Soft- Start

Maximum
Clamp
Oscillator
with PLL

8/8/ 2012 A 0192789

GND POWERPAD RT/ CLK

Copyright © 2016, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Fixed Frequency PWM Control
The TPS54540 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier
output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch
current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal
voltage will increase and decrease as the output current increases and decreases. The device implements
current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is
implemented with a minimum voltage clamp on the COMP terminal.

7.3.2 Slope Compensation Output Current

The TPS54540 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.

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Feature Description (continued)

7.3.3 Pulse Skip Eco-mode
The TPS54540 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited.
Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54540 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 35 enters Eco-mode at about 18 mA output current. As the load current approaches
zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54540 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the
high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54540 will
operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1V. When the voltage
from BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET
pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high
output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.

Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal
operation of the device. This calculation must include tolerance of the component specifications and the variation
of these specifications at their maximum operating temperature in the application
VOUT VF Rdc u IOUT
VIN min RDS on u IOUT VF
0.99

where
• VF = Schottky diode forward voltage
• Rdc = DC resistance of inductor and PCB
• RDS(on) = High-side MOSFET RDS(on) (1)

During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor is
being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to insure a monotonic startup. Equation 2 can be
used to calculate the minimum input voltage for this condition.

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Feature Description (continued)

VOUT(max) = D(max) x (VIN(min) - IOUT(max) x RDS(on) + VD) - VD + IOUT(max) x Rdc
where
• D(max) ≥ 0.9
• IB2SW = 100 µA
• VD = Forward Drop of the Catch Diode
• VB2SW = VBOOT + VD
• VBOOT = (1.41 x VIN - 0.554 - VD x fSW - 1.847 x 103 x IB2SW) / (1.41 + fSW)
• RDS(on) = 1 / (-0.3 x VB2SW2 + 3.577 x VB2SW - 4.246) (2)

7.3.5 Error Amplifier

The TPS54540 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage
reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-
start operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP terminal and GND terminal.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider
resistors. Select the low side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To
improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the
regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç ÷
è 0.8 V ø (3)

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54540 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds
the enable threshold of 1.2 V. The TPS54540 is disabled when the VIN terminal voltage falls below 4 V or when
the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 μA that
enables operation of the TPS54540 when the EN terminal floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to
adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an
additional 3.4 μA of hysteresis current, IHYS, is sourced out of the EN terminal. When the EN terminal is pulled
below 1.2 V, the 3.4 μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO
hysteresis. Use Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to
calculate RUVLO2 for the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, up to 42 V), the EN terminal may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN terminal is clamped internally with a 5.8 V zener diode that will sink up to 150 μA.

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Feature Description (continued)

VIN
TPS54540
VIN

i1 ihys
RUVLO1 RUVLO1

10 kW
EN EN
Node
V EN
RUVLO2 RUVLO2 5.8 V

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Figure 22. Adjustable Undervoltage Lockout Figure 23. Internal EN Terminal Clamp
(UVLO)
V - VSTOP
RUVLO1 = START
IHYS (4)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1 (5)

7.3.8 Internal Soft-Start

The TPS54540 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value
in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6.
1024
tSS (ms) =
fSW (kHz) (6)
If the EN terminal is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets.
The soft-start also resets in thermal shutdown.

7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)

The switching frequency of the TPS54540 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK terminal and GND terminal. The RT/CLK terminal voltage is typically 0.5 V and
must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given
switching frequency, use Equation 7 or Equation 8 or the curves in Figure 5 and Figure 6. To reduce the solution
size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion
efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum
controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high
input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback
circuit. A more detailed discussion of the maximum switching frequency is provided in the next section.
101756
RT (kW) =
f sw (kHz)1.008 (7)
92417
f sw (kHz) =
RT (kW)0.991 (8)

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Feature Description (continued)

7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
The TPS54540 implements peak current mode control in which the COMP terminal voltage controls the peak
current of the high side MOSFET. A signal proportional to the high side switch current and the COMP terminal
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high
side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier
increases switch current by driving the COMP terminal high. The error amplifier output is clamped internally at a
level which sets the peak switch current limit. The TPS54540 provides an accurate current limit threshold with a
typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor
current. The relationship between the inductor value and the peak inductor current is shown in Figure 24.

Peak Inductor Current

ΔCLPeak Open Loop Current Limit

Inductor Current (A)

ΔCLPeak = VIN/L x tCLdelay

tCLdelay

tON

Figure 24. Current Limit Delay

To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54540
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB terminal voltage
falls from 0.8 V to 0 V. The TPS54540 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 10 calculates the maximum switching frequency at
which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating
frequency should not exceed the calculated value.
Equation 9 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
æ I ´R + V ö
1 OUT + Vd
fSW (max skip ) = ´ç O dc ÷
tON ç VIN - IO ´ RDS(on ) + Vd ÷
è ø (9)

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Feature Description (continued)

fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd ö

÷
fSW(shift) = ´
tON ç VIN - ICL ´ RDS(on ) + Vd ÷
è ø (10)
IO Output current
ICL Current limit
Rdc inductor resistance
VIN maximum input voltage
VOUT output voltage
VOUTSC output voltage during short
Vd diode voltage drop
RDS(on) switch on resistance
tON controllable on time
ƒDIV frequency divide equals (1, 2, 4, or 8)

7.3.11 Synchronization to RT/CLK Terminal

The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To
implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit
network shown in Figure 25. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and
higher than 2 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to
2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The
external synchronization circuit should be designed such that the default frequency set resistor is connected from
the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal
source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor
(that is, 50 Ω) as shown in Figure 25. The two resistors in series provide the default frequency setting resistance
when the signal source is turned off. The sum of the resistance should set the switching frequency close to the
external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic
capacitor to RT/CLK terminal.
The first time the RT/CLK is pulled above the PLL threshold the TPS54540 switches from the RT resistor free-
running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The
device implements a digital frequency foldback to enable synchronizing to an external clock during normal start-
up and fault conditions. Figure 26, Figure 27 and Figure 28 show the device synchronized to an external system
clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).

TPS54540 TPS54540
RT /CLK
RT /CLK
PLL PLL
RT Hi -Z
Clock Clock
Source Source RT

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Figure 25. Synchronizing to a System Clock

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Feature Description (continued)

SW

SW

EXT EXT

IL

IL

Figure 26. Plot of Synchronizing in CCM Figure 27. Plot of Synchronizing in DCM

SW

EXT

IL

Figure 28. Plot of Synchronizing in Eco-mode

7.3.12 Overvoltage Protection

The TPS54540 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB terminal voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak
current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power supply output voltage can
increase faster than the response of the error amplifier output resulting in an output overshoot.

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Feature Description (continued)

The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB
terminal voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB
terminal voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to
minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106%
of the internal voltage reference, the high side MOSFET resumes normal operation.

7.3.13 Thermal Shutdown

The TPS54540 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by the internal soft-start circuitry.

7.3.14 Small Signal Model for Loop Response

Figure 29 shows an equivalent model for the TPS54540 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor RO
and capacitor CO model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source
between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.

SW
VO
Power Stage
gmps 17 A/V
a

R1 RESR

COMP RL
c
FB COUT
0.8 V
R3 CO RO
gmea
C2
350 mA/V R2
C1

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Figure 29. Small Signal Model for Loop Response

7.3.15 Simple Small Signal Model for Peak Current Mode Control
Figure 30 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54540 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 11 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP terminal voltage (node c in Figure 29) is the power stage
transconductance, gmPS. The gmPS for the TPS54540 is 17 A/V. The low-frequency gain of the power stage is
the product of the transconductance and the load resistance as shown in Equation 12.

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Feature Description (continued)

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of
Figure 30. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14).
VO

VC Adc

RESR
fp
RL
gmps
COUT

fz

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Figure 30. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

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Feature Description (continued)

æ s ö
ç1 + ÷
VOUT 2p ´ fZ
= Adc ´ è ø
VC æ s ö
ç1 + ÷
è 2p ´ fP ø (11)
Adc = gmps ´ RL
(12)
1
fP =
COUT ´ RL ´ 2p (13)
1
fZ =
COUT ´ RESR ´ 2p (14)

7.3.16 Small Signal Model for Frequency Compensation

The TPS54540 uses a transconductance amplifier for the error amplifier and supports three of the commonly-
used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 31. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to the small
signal model in Figure 31. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 31. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
VO

R1
FB
gmea Type 2A Type 2B Type 1
COMP

Vref
R3 C2 R3
R2 RO CO C2

C1 C1

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Figure 31. Types of Frequency Compensation

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Feature Description (continued)

Aol

A0 P1

Z1 P2
A1

BW

Figure 32. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
Ro =
gmea (15)
gmea
CO =
2p ´ BW (Hz) (16)
æ s ö
ç1 + ÷
è 2p ´ fZ1 ø
EA = A0 ´
æ s ö æ s ö
ç1 + ÷ ´ ç1 + ÷
è 2p ´ fP1 ø è 2p ´ fP2 ø
(17)
R2
A0 = gmea ´ Ro ´
R1 + R2 (18)
R2
A1 = gmea ´ Ro| | R3 ´
R1 + R2 (19)
1
P1 =
2p ´ Ro ´ C1 (20)
1
Z1 =
2p ´ R3 ´ C1 (21)
1
P2 = type 2a
2p ´ R3 | | RO ´ (C2 + CO ) (22)
1
P2 = type 2b
2p ´ R3 | | RO ´ CO (23)
1
P2 = type 1
2p ´ R O ´ (C2 + C O ) (24)

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7.4 Device Functional Modes

7.4.1 Operation with VIN = < 4.5 V (Minimum VIN)
The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. If EN is externally pulled up to VIN or left floating, when VIN passes the
UVLO threshold the device will become active. Switching is enabled, and the soft start sequence is initiated. The
TPS54540 will start at the soft start time determined by the internal soft start time.

7.4.2 Operation with EN Control

The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft start sequence is initiated. The TPS54540 will start at the soft start time
determined by the internal soft start time.

7.4.3 Alternate Power Supply Topologies

7.4.3.1 Inverting Power

The TPS54540 can be used to convert a positive input voltage to a negative output voltage. Idea applications are
amplifiers requiring a negative power supply. For a more detailed example see SLVA317.
VIN +
Cin
Cboot
Lo
BOOT SW
VIN GND
Cd R1
+
GND
R2 Co
TPS54540
FB
VOUT

EN
COMP

RT /CLK Rcomp

Czero Cpole
RT

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Figure 33. TPS54540 Inverting Power Supply

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Device Functional Modes (continued)

7.4.3.2 Split Rail Power Supply
The TPS54540 can be used to convert a positive input voltage to a split rail positive and negative output voltage
by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and negative voltage
power supply. For a more detailed example see SLVA369.

VOPOS
+
VIN + Copos
Cin
Cboot

BOOT GND
VIN SW
Lo
Cd R1
+
GND Coneg
TPS54540 R2

FB VONEG

EN
COMP
Rcomp
RT /CLK

Czero Cpole
RT

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Figure 34. TPS54540 Split Rail Power Supply

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54540 is a 42 V, 5 A, step down regulator with an integrated high side MOSFET. Idea applications are:
12 V and 24 V Industrial, Automotive and Communications Power Systems.

8.2 Typical Application

L1
5.5uH
C4 0.1uF 3.3V, 5A VOUT

U1 D1 C6 C7
TPS54540DDA 100uF 100uF
1 8 PDS760
BOOT SW R5
VIN 6 V to 42 V 2 7 31.6k
VIN GND
3 6
EN COMP
PWRPD

C10 C3 C1 C2 R1 FB FB
4 5
365k RT/CLK FB
4.7uF 4.7uF 4.7uF 4.7uF

9 R4
16 .9k C8 R6
R2 R3 47 pF 10 .2k
88.7k 243 k C5

4700 pF

Copyright © 2017, Texas Instruments Incorporated

Figure 35. 3.3 V Output TPS54540 Design Example

8.2.1 Design Requirements

This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet (SLVC452)
located on the product page. For this example, start with the following known parameters:

Table 1. Design Parameters

PARAMETER VALUE
Output Voltage 3.3 V
Transient Response 1.25 A to 3.75 A load step ΔVOUT = 4 %
Maximum Output Current 5A
Input Voltage 12 V nom. 6 V to 42 V
Output Voltage Ripple 0.5% of VOUT
Start Input Voltage (rising VIN) 5.75 V
Stop Input Voltage (falling VIN) 4.5 V

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54540 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Selecting the Switching Frequency

The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 9 and Equation 10 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54540. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 mΩ,
typical switch resistance of 92 mΩ and 5 A load, from Equation 25 the maximum switch frequency to avoid pulse
skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits use Equation 26 to
determine the maximum switching frequency for frequency foldback protection. With a current limit value of 6.3 A
and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 27 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 35. For 400 kHz operation, the closest
standard value resistor is 243 kΩ.
1 æ 5 A x 10.3 mW + 3.3 V + 0.52 V ö
fSW(max skip) = ´ ç ÷ = 680 kHz
135ns è 42 V - 5 A x 92 mW + 0.52 V ø (25)
8 æ 6.3 A x 10.3 mW + 0.1 V + 0.52 V ö
fSW(shift) = ´ ç ÷ = 960 kHz
135 ns è 42 V - 6.3 A x 92 mW + 0.52 V ø (26)
101756
RT (kW) = = 242 kW
400 (kHz)1.008 (27)

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8.2.2.3 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 28.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS
current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can
be found from Equation 30 and Equation 31. For this design, the RMS inductor current is 5 A and the peak
inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A
and an RMS current rating of 10 A. This also has a typical inductance of 5.5 µH at no load and 4.8 µH at 5 A
load. Lastly it has a DCR of 10.3 mΩ.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54540 which is nominally 7.5 A.
VIN(max ) - VOUT VOUT 42 V - 3.3 V 3.3 V
LO(min ) = ´ = ´ = 5.1 mH
IOUT ´ KIND VIN(max ) ´ fSW 5 A x 0.3 42 V ´ 400 kHz
(28)
spacer
VOUT ´ (VIN(max ) - VOUT ) 3.3 V x (42 V - 3.3 V)
IRIPPLE = = = 1.58 A
VIN(max ) ´ LO ´ fSW 42 V x 4.8 mH x 400 kHz
(29)
spacer

( )÷ö
2
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
1 æ 3.3 V ´ (42 V - 3.3 V ) ö
IL(rms ) = (IOUT ) 2
+ ´
12 çç VIN(max ) ´ LO ´ fSW ÷ = (5 A )
2
+ ´ ç
ç
÷ =5A
÷
÷ 12 è 42 V ´ 4.8 mH ´ 400 kHz ø
è ø
(30)
spacer
IRIPPLE 1.58 A
IL(peak ) = IOUT + = 5A + = 5.79 A
2 2 (31)

8.2.2.4 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.

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The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. A regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 32 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A. Therefore,
ΔIOUT is 3.75 A - 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. Using these numbers gives a minimum
capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage
change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and
tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure 36. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 33 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step
will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in
our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 V = 3.43 V. Vi is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum
capacitance of 68 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 34 yields 30 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the equivalent ESR should be less than 10 mΩ.
The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 2 x
100 μF, 6.3 V type X5R ceramic capacitors with 2 mΩ of ESR will be used. The derated capacitance is 130 µF,
well above the minimum required capacitance of 95 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability, especially non ceramic capacitors. Some capacitor data sheets specify the Root Mean Square (RMS)
value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current that the output
capacitor must support. For this example, Equation 36 yields 460 mA.
2 ´ DIOUT 2 ´ 2.5 A
COUT > = = 95 mF
fSW ´ DVOUT 400 kHz x 0.13 V (32)

COUT > LO x
((I ) - (I ) ) = 4.8 mH x (3.75 A - 1.25 A ) = 68 mF
OH
2
OL
2 2 2

((V ) - (V ) )
f
2
I
2
(3.43 V - 3.3 V )
2 2
(33)
1 1 1 1
COUT > ´ = x = 30 mF
8 ´ fSW æ VORIPPLE ö 8 x 400 kHz æ 16 mV ö
ç ÷ ç 1.58 A ÷
è IRIPPLE ø è ø (34)
V 16 mV
RESR < ORIPPLE = = 10 mW
IRIPPLE 1.58 A (35)

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ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT )= 3.3 V ´ (42 V - 3.3 V )
= 460 mA
12 ´ VIN(max ) ´ LO ´ fSW 12 ´ 42 V ´ 4.8 mH ´ 400 kHz
(36)

8.2.2.5 Catch Diode

The TPS54540 requires an external catch diode between the SW terminal and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54540.
For the example design, the PDS760-13 Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760-13 is 0.52 volts
at 5 A and 25°C.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The PDS760-13 diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode at the
nominal input voltage is 1.9 W.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.

PD =
(V IN(max ) - VOUT )´ I OUT ´ Vf d
+
C j ´ fSW ´ (VIN + Vf d)
2
=
VIN 2
(12 V - 3.3 V ) ´ 5 A x 0.52 V 300 pF x 400 kHz x (12 V + 0.52 V)2
+ = 1.9 W
12 V 2 (37)

8.2.2.6 Input Capacitor

The TPS54540 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54540. The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support transients
up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V,
16 V, 25 V, 50 V or 100 V. For this example, four 4.7 μF, 50 V capacitors in parallel are used. Table 2 shows
several choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage
ripple occurs at 50% duty cycle and can be calculated using Equation 39. Using the design example values, IOUT
= 5 A, CIN = 18.8 μF, ƒsw = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of
2.5 A.

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ICI(rms ) = IOUT x
VOUT
x
(V IN(min ) - VOUT ) = 5A 3.3 V
´
(6 V - 3.3 V )
= 2.5 A
VIN(min ) VIN(min ) 6V 6V
(38)
I ´ 0.25 5 A ´ 0.25
DVIN = OUT = = 170 mV
CIN ´ fSW 18.8 mF ´ 400 kHz (39)

Table 2. Capacitor Types

VALUE (μF) EIA Size VOLTAGE DIALECTRIC COMMENTS
1 to 2.2 100 V
1210 GRM32 series
1 to 4.7 50 V
1 100 V
1206 GRM31 series
1 to 2.2 50 V
1 to 1.8 50 V
2220
1 to 1.2 100 V
VJ X7R series
1 to 3.9 50 V
2225
1 to 1.8 100 V
X7R
1 to 2.2 100 V
1812 C series C4532
1.5 to 6.8 50 V
1 to 2.2 100 V
1210 C series C3225
1 to 3.3 50 V
1 to 4.7 50 V
1210
1 100 V
X7R dielectric series
1 to 4.7 50 V
1812
1 to 2.2 100 V

8.2.2.7 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW terminals for proper operation. A
ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or
higher voltage rating.

8.2.2.8 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the
TPS54540. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and
ground connected to the EN terminal. Equation 4 and Equation 5 calculate the resistance values necessary. For
the example application, a 365 kΩ between VIN and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2)
are required to produce the 5.75 V and 4.5 V start and stop voltages.
V - VSTOP 5.75 V - 4.5 V
RUVLO1 = START = = 368 kW
IHYS 3.4 mA (40)
VENA 1.2 V
RUVLO2 = = = 88.7 kW
VSTART - VENA 5.75 V - 1.2 V
+ I1 + 1.2 mA
RUVLO1 365 kW (41)

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8.2.2.9 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 3, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB terminal, the current flowing through the feedback network should be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
V - 0.8 V æ 3.3 V - 0.8 V ö
RHS = RLS x OUT = 10.2 kW x ç ÷ = 31.9 kW
0.8 V è 0.8 V ø (42)

8.2.2.10 Minimum VIN

To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the
device must be above the value calculated with Equation 43. Using the typical values for the RHS, RDC and VF in
this application example, the minimum input voltage is 5.56 V. The BOOT-SW = 3 V curve in Figure 1 was used
for RDS(on) = 0.12 Ω because the device operates with low drop out. When operating with low dropout, the BOOT-
SW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed every switching
cycle. In the final application, the values of RDS(on), Rdc and VF used in this equation must include tolerance of the
component specifications and the variation of these specifications at their maximum operating temperature in the
application. In this application example, the calculated minimum input voltage is near the input voltage UVLO for
the TPS54540 so the device may turn off before going into drop out.
VOUT VF Rdc u IOUT
VIN min RDS on u I OUT VF
0.99
3.3 V 0.5 V 0.0103 : u 5 A
VIN min 0.12 : u 5 A 0.5 V 3.99 V
0.99 (43)

8.2.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 44 and
Equation 45. For COUT, use a derated value of 130 μF. Use equations Equation 46 and Equation 47 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz.
Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of
modulator pole and half of the switching frequency. Equation 46 yields 34 kHz and Equation 47 gives 19 kHz.
Use the geometric mean value of Equation 46 and Equation 47 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max ) 5A
fP(mod) = = = 1850 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 130 mF (44)
1 1
f Z(mod) = = = 610 kHz
2 ´ p ´ RESR ´ COUT 2 ´ p ´ 1 mW ´ 130 mF (45)
fco1 = fp(mod) x f z(mod) = 1850 Hz x 610 kHz = 34 kHz
(46)
fSW 400 kHz
fco2 = fp(mod) x = 1850 Hz x = 19 kHz
2 2 (47)

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To determine the compensation resistor, R4, use Equation 48. The typical power stage transconductance, gmps,
is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8
V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use
Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5100 pF for
compensating capacitor C5. 4700 pF is used for this design.
æ 2 ´ p ´ fco ´ COUT ö æ VOUT ö æ 2 ´ p ´ 30 kHz ´ 130 mF ö æ 3.3V ö
R4 = ç ÷ x ç ÷ = ç ÷ xç ÷ = 17 kW
è gmps ø è VREF x gmea ø è 17 A / V ø è 0.8 V x 350 mA / V ø
(48)
1 1
C5 = = = 5100 pF
2 ´ p ´ R4 x fp(mod) 2 ´ p ´ 16.9 kW x 1850 Hz (49)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C x RESR 130 mF x 1 mW
C8 = OUT = = 15 pF
R4 16.9 kW (50)
1 1
C8 = = = 47 pF
R4 x f sw x p 16.9 kW x 400 kHz x p (51)

8.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input
current draw is 241 μA with no load.

8.2.2.13 Power Dissipation Estimate

The following formulas show how to estimate the TPS54540 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æV ö 3.3 V
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 92 mW ´
2
= 0.633 W
è VIN ø 12 V (52)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W (53)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W (54)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W (55)
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET

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IQ is the operating nonswitching supply current

Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.633 W + 0.118 W + 0.014 W + 0.0018 W = 0.77 W (56)
For given TA,
TJ = TA + RTH ´ PTOT (57)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(58)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance of the package (°C/W)
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.

8.2.3 Application Curves

Measurements are taken with standard EVM using a 12 V input, 3.3 V output, and 5 A load unless otherwise
noted.
10 V/div

IOUT
1 A/div

VIN

VOUT ±3.3V offset

10 mV/div
100 mV/div

VOUT ±3.3V offset

Time = 4 ms/div
Time = 100 Ps/div

Figure 37. Line Transient (8 V to 40 V)

Figure 36. Load Transient

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VIN

5 V/div
VIN
5 V/div

EN

2 V/div
2 V/div

EN

2 V/div
VOUT VOUT
2 V/div

Time = 20 ms/div Time = 2 ms/div

Figure 38. Start-up With VIN Figure 39. Start-up With EN

SW
10 V/div

10 V/div
SW

500 mA/div
1 A/div

IL

IL
10 mV/div
10 mV/div

VOUT ± AC Coupled
VOUT ± AC Coupled
IOUT = 100 mA

Time = 4 Ps/div Time = 4 Ps/div

Figure 40. Output Ripple CCM Figure 41. Output Ripple DCM

SW
10 V/div
10 V/div

SW
1 A/div
200 mA/div

IL
IL
200 mV/div
10 mV/div

VOUT ± AC Coupled

No Load
VIN ± AC Coupled

Time = 1 ms/div Time = 4 Ps/div

Figure 42. Output Ripple PSM Figure 43. Input Ripple CCM

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SW

2 V/div
10 V/div

IL
SW
500 mA/div

200 mA/div
IL
10 mV/div

VOUT = 5 V

20 mV/div
VIN ± AC Coupled
IOUT = 100 mA No Load
VIN = 5.5 V EN Floating

Time = 4 Ps/div Time = 40 Ps/div

Figure 44. Input Ripple DCM Figure 45. Low Dropout Operation

100 100
90
95
80
90
70
Efficiency (%)
Efficiency (%)

85 60
80 50
VIN=6V
V IN = 7 V
40
75
V IN = 12 V
VIN=12V
30
70 VOUT = 5 V, fsw = 400 kHz
20 VIN=24V
V IN = 24 V
65 Series4
VIN = 7 V 12V
VIN = 12 V
10
VIN = 24 V
24V VIN = 36 V
36V VOUT = 5 V, fsw = 400 kHz VIN=24V
V IN = 36 V
60 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.001 0.01 0.1 1
IO - Output Current (A) C024 IO - Output Current (A) C024

Figure 46. Efficiency vs Load Current Figure 47. Light Load Efficiency

100 100

95 90
80
90
70
Efficiency (%)

Efficiency (%)

85 60
80 50

75 40

VIN
V IN ==66VV
30 VIN
V IN ==66VV
70
V IN ==12
VIN 12VV 20 V IN ==12
VIN 12VV
65 V IN ==24
VIN 24VV V IN ==24
VIN 24VV
10
V VOUT = 3.3 V, fsw = 400 kHz
VOUT = 3.3 V, fsw = 400 kHz IN ==36
VIN 36VV V IN ==36
VIN 36VV
60 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.001 0.01 0.1 1
Load Current (A) C050 Load Current (A) C051

Figure 48. Efficiency vs Load Current Figure 49. Light Load Efficiency

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100 60 180
50 150
95
40 120
90 30 90
20 60
Efficiency (%)

85

Gain (dB)

Phase (£)
10 30
80 0 0
±10 ±30
75 ±20 ±60
V IN = 18 V
18in
70 ±30 ±90
Series1
V IN = 24 V ±40 Gain ±120
65 ±50 ±150
VOUT = 12 V, fsw = 800 kHz Series3 VIN = 12 V, VOUT = 3.3 V, IOUT = 5 A Phase
V IN = 36 V
±60 ±180
60
10 100 1k 10k 100k 1M
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Frequency (Hz) C053
IO - Output Current (A) C024

Figure 50. Efficiency vs Output Current Figure 51. Overall Loop Frequency Response

0.5 0.20
VIN = 12 V, IOUT = 5 A, fsw = 400 kHz
0.4 0.15
Output Voltage Normalized (%)

Output Voltage Normalized (%)

0.3
0.10
0.2
0.05
0.1
0.00
0
±0.05
-0.1
±0.10
-0.2

-0.3 ±0.15
VIN = 12 V, VOUT = 3.3 V, fsw = 400 kHz
-0.4 ±0.20
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 30 35 40 45
Output Current (A) C054 Input Voltage (V) C055

Figure 52. Regulation vs Load Current Figure 53. Regulation vs Input Voltage

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4.5 V and42 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS54540 converter
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.

36 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

Product Folder Links: TPS54540

 TPS54540
www.ti.com SLVSBX7B – MAY 2013 – REVISED MARCH 2017

10 Layout

10.1 Safe Operating Area

The safe operating area (SOA) of the device is shown in Figure 54, through Figure 57 for 3.3 V, 5 V and 12 V
outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions at
which the internal and external components are at or below the manufacturer’s maximum operating
temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz. copper, similar
to the EVM. Careful attention must be paid to the other components chosen for the design, especially the catch
diode. In most of these test conditions, the thermal performance is limited by the catch diode. When operating at
high duty cycles or at higher switching frequency the TPS54540’s thermal performance can become the limiting
factor.

90 90

80 80

70 70

60 60
TA (ƒC)

TA (ƒC)
50 50
6V 8V
40 40
12 V 12 V
30 24 V 30 24 V
36 V 36 V
20 20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT (Amps) C056 IOUT (Amps) C057

Figure 54. 3.3V Outputs Figure 55. 5V Outputs

90 90

80 80

70 70

60 60
TA (ƒC)

TA (ƒC)

fsw = 800 kHz

50 50
400 LFM
18 V
40 40 200 LFM
24 V 100 LFM
30 30
36 V Nat Conv
20 20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT (Amps) C058 IOUT (Amps) C048

Figure 56. 12V Outputs Figure 57. Air Flow Conditions

VIN = 36 V, VO = 12 V

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TPS54540
SLVSBX7B – MAY 2013 – REVISED MARCH 2017 www.ti.com

10.2 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance.
• To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN
terminal, and the anode of the catch diode.
• The GND terminal should be tied directly to the power pad under the IC and the PowerPAD™.
• The power pad should be connected to internal PCB ground planes using multiple vias directly under the IC.
• The SW terminal should be routed to the cathode of the catch diode and to the output inductor.
• Since the SW connection is the switching node, the catch diode and output inductor should be located close
to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
• The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.

10.3 Layout Example

Vout

Output
Capacitor Output
Topside Inductor
Ground Route Boot Capacitor
Area Catch
Trace on another layer to
provide wide path for Diode
topside ground

Input
Bypass
Capacitor BOOT SW
Vin
VIN GND

EN COMP
UVLO
RT/CLK FB
Adjust Compensation
Resistor
Resistors Network
Divider

Frequency Thermal VIA

Set Resistor
Signal VIA

Figure 58. PCB Layout Example

10.3.1 Estimated Circuit Area

Boxing in the components in the design of Figure 35 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.

38 Submit Documentation Feedback Copyright © 2013–2017, Texas Instruments Incorporated

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 TPS54540
www.ti.com SLVSBX7B – MAY 2013 – REVISED MARCH 2017

11 Device and Documentation Support

11.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54540 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance
– Run thermal simulations to understand the thermal performance of your board
– Export your customized schematic and layout into popular CAD formats
– Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
Eco-mode, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2013–2017, Texas Instruments Incorporated Submit Documentation Feedback 39

Product Folder Links: TPS54540
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Sep-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54540DDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR 0 to 0 54540 Samples

TPS54540DDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54540 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Sep-2023

OTHER QUALIFIED VERSIONS OF TPS54540 :

• Automotive : TPS54540-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Sep-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54540DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
PowerPAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Sep-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54540DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Sep-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS54540DDA DDA HSOIC 8 75 517 7.87 635 4.25
TPS54540DDA DDA HSOIC 8 75 507 8 3940 4.32

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
DDA 8 PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4202561/G
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/A 08/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/A 08/2016

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
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