DDR3 HynixX
DDR3 HynixX
DDR3 HynixX
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Features
Ordering Information
# of
Part Number Density Organization Component Composition FDHS
ranks
CAS
tCK tRCD tRP tRAS tRC
MT/s Grade Latency CL-tRCD-tRP
(ns) (ns) (ns) (ns) (ns)
(tCK)
Speed Grade
Frequency [MHz]
Grade Remark
CL6 CL7 CL8 CL9 CL10 CL10
Address Table
Refresh
8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms
Method
Column
A0-A9 A0-A9 A0-A9,A11 A0-A9 A0-A9,A11 A0-A9,A11
Address
Positive Positive line of the differential pair of system clock inputs that drives input to the on-
CK0 IN
Line DIMM Clock Driver.
Negative Negative line of the differential pair of system clock inputs that drives the input to the
CK0 IN
Line on-DIMM Clock Driver.
Positive
CK1 IN Terminated but not used on RDIMMs.
Line
Negative
CK1 IN Terminated but not used on RDIMMs.
Line
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
Active buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
CKE[1:0] IN
High POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
Active and previous operations continue. Other combinations of these input signals perform
S[3:0] IN
Low unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
Active
ODT[1:0] IN On-Die Termination control signals
High
Active When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
RAS, CAS, WE IN
Low operation to be executed by the SDRAM.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
VREFCA Supply
ODT0 and ODT1.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the mem-
A[15:13, ory array in the respective bank. A10 is sampled during a Precharge command to deter-
12/BC,11, IN — mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
10/AP,[9:0] only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
DQ[63:0],
I/O — Data and Check Bit Input/Output pins
CB[7:0]
Active
DM[8:0] IN Masks write data when high, issued concurrently with input data.
High
VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
Positive
DQS[17:0] I/O Positive line of the differential data strobe for input and output data.
Edge
Negative
DQS[17:0] I/O Negative line of the differential data strobe for input and output data.
Edge
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
TDQS[17:9] MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
TDQS[17:9] OUT applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4/X16 DRAMs must disable the
TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
SA[2:0] IN —
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
SDA I/O — must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
SCL IN —
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing
OUT
device.The system should guarantee the electrical level requirement is met for the
EVENT (open Active Low
EVENT pin on TS/SPD part.
drain)
No pull-up resister is provided on DIMM.
VDDSPD Serial EEPROM positive power supply wired to a separate power pin at the connector
Supply
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
RESET IN
the DRAM.
Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
OUT Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out (open Err_Out bus line to VDD on the system planar to act as a pull up.
drain)
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Capacitance Values
DDR3-800
1066/1333/1600
Symbol Parameter Conditions Unit
Min Max
EVENT
SCL
SDA SA0
EVENT
SPD with SA1
SCL Integrated SA2
SA0 SDA TS
SA1
SA2
Active Range,
- ± 0.5 ± 1.0 °C
75°C < TA < 95°C
Resolution 0.25 °C
/BA[N:O]A
/BA[N:O]B
A[N:O]A
A[N:O]B
RODT0A
RODT0B
RCKE0A
RCKE0B
RCASA
RCASB
RRASA
RRASB
PCK0A
PCK0B
PCK0A
PCK0B
RWEA
RWEB
RS0A
RS0B
DQS8 DQS ZQ DQS4 DQS ZQ
DQS8 DQS DQS4 DQS
A[N:O]/BA[N:O]
A[O:N]/BA[O:N]
DM8/DQS17 TDQS DM4/DQS13 TDQS
DQS17 TDQS D8 DQS13 TDQS D4
CB[7:0] DQ [7:0] DQ[39:32] DQ [7:0]
ODT
ODT
RAS
RAS
CAS
CAS
CKE
CKE
WE
WE
CK
CK
CK
CK
CS
CS
DQS3 DQS ZQ DQS5 DQS ZQ
DQS3 DQS DQS5 DQS
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
ODT
ODT
RAS
CAS
CKE
RAS
CAS
CKE
WE
WE
CK
CK
CS
CK
CK
CS
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
RAS
CAS
CKE
RAS
CAS
CKE
WE
WE
CK
CK
CK
CK
CS
CS
A[N:O]/BA[N:O]
ODT
RAS
CAS
RAS
CKE
CAS
CKE
VREFCA
WE
WE
D0–D8
CK
CK
CK
CK
CS
CS
VREFDQ D0–D8
DQS0 DQS ZQ Vtt
VSS D0–D8
DQS0 DQS
A[N:O]/BA[N:O]
DM0/DQS9 TDQS
DQS9 TDQS D0
DQ[7:0] DQ [7:0] Note:
1.DQ-to-I/O wiring may be changed within byte.
ODT
RAS
CAS
CKE
WE
2.ZQ resistors are 240 Ω ±1%.For all other resistor values refer to the
CK
CK
CS
/BA[N:O]A
/BA[N:O]B
A[N:O]A
A[N:O]B
RODT0A
RODT0B
RCKE0A
RODT1A
RCKE0B
RODT1B
RCKE1A
RCKE1B
RCASA
RCASB
RRASA
RRASB
PCK0A
PCK0B
PCK0A
PCK0B
RWEA
PCK1A
RWEB
PCK1B
PCK1A
PCK1B
RS0A
RS0B
RS1A
RS1B
DQS8 DQS DQS DQS4 DQS DQS
DQS8 DQS DQS DQS4 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DM8/DQS17 TDQS TDQS DM4/DQS13 TDQS TDQS
DQS17 TDQS D8 TDQS D17 DQS13 TDQS D4 TDQS D13
CB[7:0] DQ [7:0] DQ [7:0] DQ[39:32] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
ODT
ODT
RAS
RAS
CAS
CAS
CKE
ODT
CKE
ODT
RAS
RAS
CAS
CAS
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CS
CS
CK
CK
CK
CK
CS
CS
DQS3 DQS DQS DQS5 DQS DQS
DQS3 DQS DQS DQS5 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DM3/DQS12 TDQS TDQS DM5/DQS14 TDQS TDQS
DQS12 TDQS D3 TDQS D12 DQS14 TDQS D5 TDQS D14
DQ[31:24] DQ [7:0] DQ [7:0] DQ[47:40] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
ODT
ODT
RAS
RAS
CKE
CKE
CAS
CAS
ODT
ODT
RAS
RAS
CAS
CAS
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CS
CS
CK
CK
CK
CK
CS
CS
DQS2 DQS DQS DQS6 DQS DQS
DQS2 DQS DQS DQS6 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DM2/DQS11 TDQS TDQS DM6/DQS15 TDQS TDQS
DQS11 TDQS D2 TDQS D11 DQS15 TDQS D6 TDQS D15
DQ[23:16] DQ [7:0] DQ [7:0] DQ55:48] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
ODT
ODT
RAS
RAS
CAS
CAS
CKE
ODT
CKE
ODT
RAS
RAS
CKE
CKE
CAS
CAS
WE
WE
WE
WE
CK
CK
CK
CK
CS
CS
CK
CK
CK
CK
CS
CS
DQS1 DQS DQS DQS7 DQS DQS
DQS1 DQS DQS DQS7 DQS DQS
A[O:N]/BA[N:O]
A[N:O]/BA[N:O]
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
DM1/DQS10 TDQS TDQS DM7/DQS16 TDQS TDQS
DQS10 TDQS D1 TDQS D10 DQS16 TDQS D7 TDQS D16
DQ[15:8] DQ [7:0] DQ [7:0] DQ[63:56] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
ODT
ODT
RAS
RAS
CAS
CAS
CKE
CKE
ODT
ODT
RAS
RAS
CAS
CAS
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CS
CS
CK
CK
CK
CK
CS
CS
A[N:O]/BA[N:O]
CKE
ODT
RAS
CKE
CAS
WE
WE
CK
CK
CS
CK
CK
CS
VREFCA D0–D17
VREFDQ D0–D17
VSS D0–D17
RESET RST
RST: SDRAMs D[17:0]
* S[3:2], CK1 and CK1 are NC
/BA[O:N]A
/BA[O:N]B
A[O:N]A
A[O:N]B
RODT0A
RODT0B
RCKE0A
RCKE0B
RCASA
RCASB
RRASA
RRASB
PCK0A
PCK0B
PCK0A
PCK0B
RWEA
RWEB
RS0A
RS0B
DQS8 DQS ZQ DQS17 DQS ZQ DQS4 DQS ZQ DQS13 DQS ZQ
DQS8 DQS DQS17 DQS DQS4 DQS DQS13 DQS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
VSS DM VSS DM VSS DM VSS DM
D8 D17 D4 D13
VSS
VSS
VSS
VSS
CB[3:0] DQ [3:0] CB[7:4] DQ [3:0] DQ[35:32] DQ [3:0] DQ[39:36] DQ [3:0]
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS3 DQS ZQ DQS12 DQS ZQ DQS5 DQS ZQ DQS14 DQS ZQ
DQS3 DQS DQS12 DQS DQS5 DQS DQS14 DQS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
VSS DM VSS DM VSS DM VSS DM
D3 D12 D5 D14
VSS
VSS
VSS
VSS
DQ[27:24] DQ [3:0] DQ[31:28] DQ [3:0] DQ[43:40] DQ [3:0] DQ[47:44] DQ [3:0]
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS2 DQS ZQ DQS11 DQS ZQ DQS6 DQS ZQ DQS15 DQS ZQ
DQS2 DQS DQS11 DQS DQS6 DQS DQS15 DQS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
VSS DM VSS DM VSS DM VSS DM
D2 D11 D6 D15
VSS
VSS
VSS
VSS
DQ[19:16] DQ [3:0] DQ23:20] DQ [3:0] DQ[51:48] DQ [3:0] DQ[55;52] DQ [3:0]
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CKE
CKE
CKE
CKE
CAS
CAS
CAS
CAS
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS1 DQS ZQ DQS10 DQS ZQ DQS7 DQS ZQ DQS16 DQS ZQ
DQS1 DQS DQS10 DQS DQS7 DQS DQS16 DQS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
VSS DM VSS DM VSS DM VSS DM
D1 D10 D7 D16
VSS
VSS
VSS
VSS
DQ[11;8] DQ [3:0] DQ[15:12] DQ [3:0] DQ[59:56] DQ [3:0] DQ[63:60] DQ [3:0]
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
ZQ ZQ
DQS0 DQS DQS9 DQS Vtt
DQS0 DQS DQS9 DQS
A[O:N]/BA[O:N]
A[O:N]/BA[O:N]
VSS DM VSS DM
D0 D9
VSS
VSS
ODT
RAS
RAS
CAS
CAS
CKE
CKE
WE
WE
CK
CK
CK
CK
CS
CS
Vtt
RESET RST
RST: SDRAMs D[17:0]
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground.)
CB[7:0]
DQ[31:24]
DQ[32:16]
DQ[7:0]
TDQS17
DM8/TDQS17
DQS8
DQS8
TDQS12
DM3/TDQS12
DQS3
DQS3
TDQS11
DM2/TDQS11
DQS2
DQS2
TDQS10
DM1/TDQS10
DQS1
DQS1
DM0/TDQS9
DQS0
DQS0
ZQ
ZQ
ZQ
ZQ
ZQ
CS CS CS CS CS CS0
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
RAS RAS RAS RAS RAS WRAS
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
CAS CAS CAS CAS CAS
U6
U5
U4
U3
U2
CKE CKE CKE CKE CKE WCKE0
ODT ODT ODT ODT ODT WODT0
A[N:O] A[N:O] A[N:O] A[N:O] A[N:O] WA[N:0]
BA[N:O] BA[N:O] BA[N:O] BA[N:O] BA[N:O] WBA[N:0]
ZQ
ZQ
ZQ
ZQ
ZQ
CS CS CS CS CS CS1
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
RAS RAS RAS RAS RAS
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
CAS CAS CAS CAS CAS
WE WE WE WE WE
CK CK CK CK CK PCK0
CK CK CK CK CK PCK0
U15
U14
U13
U12
U11
ZQ
ZQ
ZQ
ZQ
ZQ
8GB, 1Gx72 Module(4Rank of x8) - page1
CS CS CS CS CS CS2
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
U24
U23
U22
U21
U20
ZQ
ZQ
ZQ
ZQ
ZQ
CS CS CS CS CS CS3
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
TDQS
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
DQ [7:0]
U33
U32
U31
U30
U29
17
8GB, 1Gx72 Module(4Rank of x8) - page2
WBA[N:0]
WA[N:0]
WCKE01
WODT0
WODT1
WCKE0
WCKE0
WCKE1
WCAS
WRAS
WWE
PCK0
PCK0
PCK2
PCK2
PCK0
PCK0
PCK2
PCK2
VDD
VDD
CS0
CS1
CS2
CS3
CK
CK
CK
CK
CK
CK
CK
CK
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
DQS4 DQS DQS DQS DQS
DQS4 DQS DQS DQS DQS
DM4/TDQS13 TDQS TDQS TDQS TDQS
TDQS13 TDQS
U7 TDQS
U16 TDQS
U25 TDQS
U34
DQ[39:32] DQ [7:0] DQ [7:0] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
CK
CK
CK
CK
CK
CK
CK
CK
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
A[N:O]
BA[N:O]
DQS5 DQS DQS DQS DQS
DQS5 DQS DQS DQS DQS
DM5/TDQS14 TDQS TDQS TDQS TDQS
TDQS14 TDQS
U8 TDQS
U17 TDQS
U26 TDQS
U35
DQ[47:40] DQ [7:0] DQ [7:0] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CK
CK
A[N:O]
CK
CK
A[N:O]
CK
CK
A[N:O]
CK
CK
A[N:O]
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
BA[N:O]
BA[N:O]
BA[N:O]
BA[N:O]
DQS6 DQS DQS DQS DQS
DQS6 DQS DQS DQS DQS
DM6/TDQS15 TDQS TDQS TDQS TDQS
TDQS15 TDQS
U9 TDQS
U18 TDQS
U27 TDQS
U36
DQ[55:48] DQ [7:0] DQ [7:0] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CS
RAS
CAS
CK
CK
A[N:O]
CK
CK
A[N:O]
CK
CK
A[N:O]
CK
CK
A[N:O]
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
WE
CKE
ODT
BA[N:O]
BA[N:O]
BA[N:O]
BA[N:O]
DQS3 DQS DQS DQS DQS
DQS3 DQS DQS DQS DQS
DM3/TDQS12 TDQS TDQS TDQS TDQS
TDQS12 TDQS
U10 TDQS
U19 TDQS
U28 TDQS
U37
DQ[31:24] DQ [7:0] DQ [7:0] DQ [7:0] DQ [7:0]
ZQ ZQ ZQ ZQ
Vtt
VDDSPD Serial PD
VDD U1–U37
Notes:
1. DQ-to-I/O wiring may be changed within a byte. VTT
2. See wiring diagrams for resistor values. VREFCA U1-U37
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms. VREFDQ U1-U37
VSS U1-U37
PAR_IN Err_Out
RESET RST
RST: SDRAMs U[37:2]
DQ[15:12]
DQ[23:20]
DQ[31:28]
CB[7:4]
VSS
VSS
VSS
VSS
VSS
DQS0
DQS0
DM
DM
DM
DM
DM
CS CS CS CS CS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
RS0A
RAS RAS RAS RAS RAS RRASA
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
CAS CAS CAS CAS CAS RCASA
WE WE WE WE WE RWEA
CK CK CK CK CK PCK0A
D0
DM
DM
DM
DM
DM
CS CS CS CS CS RS1A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D18
D28
D29
D30
D35
CK CK CK CK CK PCK1A
CKE CKE CKE CKE CKE RCKE1A
ODT ODT ODT ODT ODT R0DT1A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
Vtt
DQ[7:4]
DQ[11:8]
DQ[19:16]
DQ[27:24]
CB[3:0]
VSS
VSS
VSS
VSS
VSS
DQS9
DQS9
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS8
DQS8
8GB, 1Gx72 Module(2Rank of x4) - page1
DM
DM
DM
DM
DM
CS CS CS CS CS RS0A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D9
D1
D2
D3
D8
CK CK CK CK PCK0A
CK
CKE CKE CKE CKE RCKE0A
CKE
ODT ODT ODT ODT ODT RODT0A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[O:N]A
/BA[O:N]A
DM
DM
DM
DM
DM
CS CS CS CS CS RS1A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D27
D19
D20
D21
D26
CK CK CK CK CK PCK1A
CKE CKE CKE CKE CKE RCKE1A
ODT ODT ODT ODT ODT R0DT1A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
20
8GB, 1Gx72 Module(2Rank of x4) - page2
/BA[N:O]B
/BA[N:O]B
A[N:O]B
A[N:O]B
RODT0B
RODT0B
RCKE0B
R0DT1B
RCKE1B
RCKE0B
R0DT1B
RCKE1B
RCASB
RRASB
PCK0B
RCASB
RRASB
PCK0B
PCK0B
PCK1B
PCK1B
PCK0B
RWEB
PCK1B
PCK1B
RWEB
RS1B
RS0B
RS1B
RS0B
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM DM VSS DM DM
DQ[47:44] DQ [3:0] D14 DQ [3:0] D32 DQ[39:36] DQ [3:0] D13 DQ [3:0] D31
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS4 DQS DQS DQS5 DQS DQS
DQS4 DQS DQS DQS5 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM DM VSS DM DM
DQ[35:32] DQ [3:0] D4 DQ [3:0] D22 DQ[43:40] DQ [3:0] D5 DQ [3:0] D23
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS16 DQS DQS DQS15 DQS DQS
DQS16 DQS DQS DQS15 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM DM VSS DM DM
DQ[63:60] DQ [3:0] D16 DQ [3:0] D34 DQ[55:52] DQ [3:0] D15 DQ [3:0] D33
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CKE
CKE
CKE
CKE
CAS
CAS
CAS
CAS
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
DQS7 DQS DQS DQS6 DQS DQS
DQS7 DQS DQS DQS6 DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM DM VSS DM DM
DQ[59:56] DQ [3:0] D7 DQ [3:0] D25 DQ[51:48] DQ [3:0] D6 DQ [3:0] D24
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
Vtt Vtt
VDDSPD SPD
VDDSPD VDDSPD SA0 SA0
VDD D0–D35
EVENT EVENT SPD with SA1 SA1
VTT D0–D35
SCL SCL Integrated SA2 SA2
VREFCA D0–D35 TS
VREFDQ D0–D35 SDA SDA VSS VSS
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VSS
VSS
VSS
VSS
VSS
DQS0
DQS1
DQS2
DQS3
DQS8
DQS0
DQS1
DQS2
DQS3
DQS8
CB[3:0]
DQ[3:0]
Vtt
DQ[11:8]
DQ[19:16]
DQ[27:24]
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS ARS0A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
RAS RAS RAS RAS RAS ARRASA
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
CAS CAS CAS CAS CAS ARCASA
WE WE WE WE WE ARWEA
D1
D3
D5
D7
D9
CK CK CK CK CK APCK0A
CKE CKE CKE CKE CKE ARCKE0A
ODT ODT ODT ODT ODT ARODT0A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
ARA[N:O]A
/ARBA[N:O]A
VSS
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
CS
DM
CS
DM
CS
DM
CS
DM
DM
CS ARS1A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D0
D2
D4
D6
D8
CK CK CK CK CK
CKE CKE CKE CKE CKE ARCKE1A
ODT ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
VSS
VSS
VSS
VSS
VSS
16GB, 2Gx72 Module(4Rank of x4) - page1
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
BRS2A
RAS RAS RAS RAS RAS BRRASA
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D53
D51
D49
D47
D45
CK CK CK CK CK BPCK0A
CKE CKE CKE CKE CKE BRCKE0A
ODT ODT ODT ODT ODT BRODT1A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
BRA[N:O]A
/BRBA[N:O]A
VSS
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS BRS3A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D52
D50
D48
D46
D44
CK CK CK CK CK
CKE CKE CKE CKE CKE BRCKE1A
ODT ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQS9
DQS9
DQS17
DQS10
DQS11
DQS12
DQS10
DQS11
DQS12
DQS17
CB[7:4]
DQ[7:4]
Vtt
DQ[11:8]
DQ[23:20]
DQ[31:28]
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS ARS0A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
RAS RAS RAS RAS RAS ARRASA
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
CAS CAS CAS CAS CAS ARCASA
WE WE WE WE WE ARWEA
D19
D21
D23
D25
D27
CK CK CK CK CK APCK0A
CKE CKE CKE CKE CKE ARCKE0A
ODT ODT ODT ODT ODT ARODT0A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
ARA[N:O]A
/ARBA[N:O]A
VSS
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
CS
DM
CS
DM
CS
DM
CS
DM
DM
CS ARS1A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D18
D20
D22
D24
D26
CK CK CK CK CK
CKE CKE CKE CKE CKE ARCKE1A
ODT ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
VSS
VSS
VSS
VSS
VSS
16GB, 2Gx72 Module(4Rank of x4) - page2
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
BRS2A
RAS RAS RAS RAS RAS BRRASA
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D71
D69
D67
D65
D63
CK CK CK CK CK BPCK0A
CKE CKE CKE CKE CKE BRCKE0A
ODT ODT ODT ODT ODT BRODT1A
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
BRA[N:O]A
/BRBA[N:O]A
VSS
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
DM
CS CS CS CS CS BRS3A
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D70
D68
D66
D64
D62
CK CK CK CK CK
CKE CKE CKE CKE CKE BRCKE1A
ODT ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQS7
DQS6
DQS5
DQS4
DQS7
DQS6
DQS5
DQS4
Vtt
DQ[59:56
DQ[51:48]
DQ[43:40]
DQ[35:32]
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
CS CS CS CS ARS0B
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
RAS RAS RAS RAS ARRASB
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
CAS CAS CAS CAS ARCASB
WE WE WE WE ARWEB
D17
D15
D13
D11
CK CK CK CK APCK0B
CKE CKE CKE CKE ARCKE0B
ODT ODT ODT ODT ARODT0B
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
ARA[N:O]B
/ARBA[N:O]B
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
CS
DM
CS
DM
CS
DM
DM
CS ARS1B
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D16
D14
D12
D10
CK CK CK CK
CKE CKE CKE CKE ARCKE1B
ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
VSS
VSS
VSS
VSS
16GB, 2Gx72 Module(4Rank of x4) - page3
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
CS CS CS CS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
BRS2B
RAS RAS RAS RAS BRRASB
DQ [3:0]
DQ [3:0]
DQ [3:0]
DQ [3:0]
D37
D39
D41
D13
CK CK CK CK BPCK0B
CKE CKE CKE CKE BRCKE0B
ODT ODT ODT ODT BRODT1B
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
BRA[N:O]B
/BRBA[N:O]B
VSS
VSS
VSS
VSS
ZQ
ZQ
ZQ
ZQ
DM
DM
DM
DM
CS CS CS CS BRS3B
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
CK CK CK CK
CKE CKE CKE CKE BRCKE1B
ODT ODT ODT ODT VDD
A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O] A[N:O]/BA[N:O]
25
16GB, 2Gx72 Module(4Rank of x4) - page4
/ARBA[N:O]B
/BRBA[N:O]B
ARA[N:O]B
BRA[N:O]B
ARODT0B
BRODT1B
ARCKE0B
BRCKE0B
ARCKE1B
BRCKE1B
ARCASB
ARRASB
BRCASB
BRRASB
APCK0B
BPCK0B
APCK0B
BPCK0B
ARWEB
BRWEB
ARS0B
ARS1B
BRS2B
BRS3B
VDD
VDD
VSS ZQ VSS ZQ VSS ZQ VSS ZQ
DQS13 DQS DQS DQS DQS
DQS13 DQS DQS DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS
DQ[39:36]
DM
DQ [3:0]
D29 DM
DQ [3:0]
D28 DM
DQ [3:0]
D61 DM
DQ [3:0]
D60
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
VSS ZQ VSS ZQ VSS ZQ VSS ZQ
DQS14 DQS DQS DQS DQS
DQS14 DQS DQS DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS
DQ[47:44]
DM
DQ [3:0]
D31 DM
DQ [3:0]
D30 DM
DQ [3:0]
D59 DM
DQ [3:0]
D58
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CKE
CKE
CKE
CKE
CAS
CAS
CAS
CAS
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
VSS ZQ VSS ZQ VSS ZQ VSS ZQ
DQS15 DQS DQS DQS DQS
DQS15 DQS DQS DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS
DQ[55:52]
DM
DQ [3:0]
D33 DM
DQ [3:0]
D32 DM
DQ [3:0]
D57 DM
DQ [3:0]
D56
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
VSS ZQ VSS ZQ VSS ZQ VSS ZQ
DQS16 DQS DQS DQS DQS
DQS16 DQS DQS DQS DQS
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS
DQ[63:60]
DM
DQ [3:0]
D35 DM
DQ [3:0]
D34 DM
DQ [3:0]
D55 DM
DQ [3:0]
D54
ODT
ODT
ODT
ODT
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CKE
CKE
CKE
CKE
WE
WE
WE
WE
CK
CK
CK
CK
CK
CK
CK
CK
CS
CS
CS
CS
Vtt
VDDSPD SPD
VDDSPD VDDSPD SA0 SA0
VDD D0–D71
EVENT EVENT SPD with SA1 SA1
VTT Integrated SA2
SCL SCL SA2
VREFCA D0–D71 TS
VREFDQ D0–D71 SDA SDA VSS VSS
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15 Ohms ±5%.
3. See the wiring diagrams for all resistors associated with the command, address and
control bus.
4. ZQ resistors are 240 Ohms ±1%. For all other resistor values refer to the appropriate
wiring diagram.
CK1
120 Ω
±5%
CK1
1. CK0 and CK0 are differentially terminated with a single 120 Ohms ±5% resistor.
2. CK1 and CK1 are differentially terminated with a single 120 Ohms ±5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
4. The module drawing on this page is not drawn to scale.
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs sup-
port Auto Self-Refresh and in Extended Temperature Range and please refer to Hynix component datasheet
and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range
Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.500 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
VDD
VRef(t)
VRef ac-noise
VRef(DC) VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are depen-
dent on VRef.
“VRef ” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
tDVAC
VIL.DIFF.AC.MIN
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.MIN
0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to ?$paratext>? on page 42.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Vix Definition
Delta
TRdiff
vIHdiffmin
vILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Delta TRse
Single Ended Output Voltage(l.e.DQ)
vOH(AC)
V∏
vOl(AC)
Delta TFse
Delta
TRdiff
Differential Output Voltage(i.e. DQS-DQS)
vOHdiff(AC)
vOLdiff(AC)
Delta
TFdiff
VDDQ
25 Ohm
CK, CK DQ
DUT VTT = VDDQ/2
DQS
DQS
M axim um A m plitude
O vershoot A rea
VDD
V olts
(V)
V SS
U ndershoot Area
M axim um A m plitud e
Tim e (ns)
M a x im u m A m p litu d e
O v e rs h o o t A re a
VDDQ
V o lts
(V )
VSSQ
U n d e rs h o o t A re a
M a x im u m A m p litu d e
T im e (n s )
Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes
REF command ACT or
tRFC 90 110 160 300 350 ns
REF command time
Average periodic 0 C TCASE 85 C 7.8 7.8 7.8 7.8 7.8 us
tREFI
refresh interval 85 C TCASE 95 C 3.9 3.9 3.9 3.9 3.9 us 1
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only,
and device functional operation at or above the conditions indicated is not implied. Expousure to absolute
maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
4GB: HMT351R7BFR8C
Pin Symbol Min Max Unit
4GB: HMT351R7BFR4C
Pin Symbol Min Max Unit
8GB: HMT31GR7BFR8C
Pin Symbol Min Max Unit
16GB: HMT42GR7BMR4C
Pin Symbol Min Max Unit
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
VDD VDDQ
RESET
CK/CK
DDR3
SDRAM
CKE DQS, DQS RTT = 25 Ohm
CS DQ, DM, VDDQ/2
RAS, CAS, WE TDQS, TDQS
A, BA
ODT
ZQ
VSS VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Channel
IDDQ IDDQ
IO Power
Simulation Simulation
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
IDD0 PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1 RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P1
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2Q
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3P
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
IDD4R
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
IDD4W
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6 Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Auto Self-Refresh Current (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6TC Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buf-
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC+3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC+3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5 D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
Datab)
CAS
CKE
WE
CS
0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1 D 1 0 0 0 1 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5 D 1 0 0 0 1 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 -
toggling
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 REF 0 0 0 1 0 0 0 0 0 0 0 -
1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
Static High
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
Datab)
CKE
CAS
WE
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
1
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
4*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
4
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Static High
9
toggling
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
128.95
2.10±0.15 SPD/TS
Clock Driver
Registering
4X3.00±0.10
30.00
17.30
Detail A
Detail B Detail C
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
3.43mm max
Detail of Contacts A Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.35
128.95
2.10±0.15 SPD/TS
Detail A
Clock Driver
Registering
4X3.00±0.10
30.00
23.30
17.30
Detail B Detail C
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
3.43mm max
Detail of Contacts A Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3+0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.35
128.95
2.10±0.15 SPD/TS
Clock Driver
Registering
4X3.00±0.10
30.00
23.30
17.30
Detail A
Detail B Detail C
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
3.43mm max
Detail of Contacts A Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.35
Detail B 128.95
SPD/TS
2.10±0.15
Detail A
4X3.00±0.10
30.00
Clock Driver
Registering
23.30
17.30
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
Detail of Contacts A Detail of Contacts D 3.46mm max
Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.75
133.35
127
42.7 2.786
20.9 8
3.69
6.35 5.39 7.74
Clock Driver
Registering
2.15 6.3
10
14.214
22.00
30.20
36.7
1 120
46.46
80.54
119.64
57.2 Back
2.7
Clock Driver
Registering
22.00
15.36
121 240
Side
7.19mm max
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
Front
133.35
Detail B 128.95
SPD/TS
2.10±0.15
Detail A
4X3.00±0.10
30.00
Clock Driver
Registering
23.30
17.30
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
Detail of Contacts A Detail of Contacts D 3.46mm max
Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.75
133.35
127
42.7 2.786
20.9 8
3.69
6.35 5.39 7.74
Clock Driver
Registering
2.15 6.3
10
14.214
22.00
30.20
36.7
1 120
46.46
80.54
119.64
57.2 Back
2.7
Clock Driver
Registering
22.00
15.36
121 240
Side
7.19mm max
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
Front
133.35
Detail B 128.95
SPD/TS
2.10±0.15
Detail A
DDP DDP DDP DDP DDP DDP DDP DDP DDP
Clock Driver
Registering
4X3.00±0.10
30.00
23.30
17.30
DDP DDP DDP DDP DDP DDP DDP DDP DDP
9.50
1 120
2X3.00±0.10 1
Back
240 121
1
Side
Detail of Contacts D 3.66mm max
Detail of Contacts A Detail of Contacts B Detail of Contacts C
1.20± 0.15
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
3± 0.1
0.20
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Front
133.75
133.35
127
42.7 2.786
20.9
4.06 8.2
6.1
6.35 5.16 7.74
12.02
Clock Driver
1.1 10.1
Registering
17.2
2.15 10
14.214
22.00
30.20
36.7
6.8
1 120
46.46
80.54
119.64
Back
57.2
2.7
Clock Driver
Registering
22.00
121 240 15.36
Side
7.35mm max
1.27±010mm
Note: max