MC14513B

BCD-To-Seven Segment
Latch/Decoder/Driver
CMOS MSI
(Low–Power Complementary MOS)
The MC14513B BCD–to–seven segment latch/decoder/driver is http://onsemi.com
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and has output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with seven–segment light emitting
diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal MARKING
readouts either directly or indirectly. DIAGRAMS
18
Applications include instrument (e.g., counter, DVM, etc.) display PDIP–18
driver, computer/calculator display driver, cockpit display driver, and MC14513BCP
P SUFFIX
AWLYYWW
various clock, watch, and timer uses. CASE 707
1
• Low Logic Circuit Power Dissipation
• High–current Sourcing Outputs (Up to 25 mA) A = Assembly Location
• Latch Storage of Binary Input WL or L = Wafer Lot
• Blanking Input YY or Y = Year
WW or W = Work Week
• Lamp Test Provision
• Readout Blanking on all Illegal Input Combinations
• Lamp Intensity Modulation Capability ORDERING INFORMATION
• Time Share (Multiplexing) Capability Device Package Shipping
• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
• Supply Voltage Range = 3.0 V to 18 V
MC14513BCP PDIP–18 20/Rail

• Capable of Driving Two Low–Power TTL Loads, One Low–power This device contains protection circuitry to protect
Schottky TTL Load to Two HTL Loads Over the Rated Temperature the inputs against damage due to high static voltages
Range. or electric fields. However, it is advised that normal
precautions be taken to avoid application of any volt-
MAXIMUM RATINGS (Voltages Referenced to VSS) (1.) age higher than maximum rated voltages to this high–
Symbol Parameter Value Unit impedance circuit. A destructive high current mode
may occur if Vin and Vout are not constrained to the
VDD DC Supply Voltage Range – 0.5 to +18.0 V range VSS v (Vin or Vout)v VDD.
Due to the sourcing capability of this circuit, dam-
Vin Input Voltage Range, All Inputs – 0.5 to VDD + 0.5 V
age can occur to the device if VDD is applied, and the
I DC Current Drain per Input Pin 10 mA outputs are shorted to VSS and are at a logical 1 (See
Maximum Ratings).
PD Power Dissipation, 500 mW
Unused inputs must always be tied to an appropri-
per Package (2.)
ate logic voltage level (e.g., either VSS or VDD).
TA Operating Temperature Range – 55 to +125 °C
Tstg Storage Temperature Range – 65 to +150 °C
IOHmax Maximum Continuous Output 25 mA 1. Maximum Ratings are those values beyond which
Drive Current (Source) per Output damage to the device may occur.
2. Temperature Derating:
POHmax Maximum Continuous Output 50 mW Plastic “P and D/DW” Packages: – 7.0 mW/_C
Power (Source) per Output (3.) From 65_C To 125_C
3. POHmax = IOH (VDD – VOH)

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 3 MC14513B/D
 MC14513B

PIN ASSIGNMENT
B 1 18 VDD
C 2 17 f
LT 3 16 g
a
BI 4 15 a f g b
LE 5 14 b e c
D 6 13 c d
A 7 12 d

RBI 8 11 e
VSS 9 10 RBO

DISPLAY

0 1 2 3 4 5 6 7 8 9

TRUTH TABLE
Inputs Outputs
RBI LE BI LT D C B A RBO a b c d e f g Display
X X X 0 X X X X + 1 1 1 1 1 1 1 8
X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank
0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0
X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1
X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2
X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3
X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4
X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5
X 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 6
X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7
X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8
X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9
X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank
X 1 1 1 X X X X † * *

X = Don’t Care
†RBO = RBI (D C B A), indicated by other rows of table
*Depends upon the BCD code previously applied when LE = 0

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 MC14513B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage — Segment Outputs VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.1 — 4.1 5.0 — 4.1 — Vdc
Vin = 0 or VDD 10 9.1 — 9.1 10 — 9.1 —
15 14.1 — 14.1 15 — 14.1 —
Output Voltage — RBO Output VOL Vdc
“0” Level 5.0 — 0.05 — 0 0.05 — 0.05
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage (4.) “0” Level VIL Vdc
(VO = 3.8 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 8.8 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.8 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
(VO = 0.5 or 3.8 Vdc) “1” Level VIH 5.0 3.5 — 3.5 2.75 — 3.5 — Vdc
(VO = 1.0 or 8.8 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.8 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Voltage — Segments VOH Vdc

(IOH = 0 mA) Source 5.0 4.1 — 4.1 4.57 — 4.1 —
(IOH = 5.0 mA) — — — 4.24 — — —
(IOH = 10 mA) 3.9 — 3.9 4.12 — 3.5 —
(IOH = 15 mA) — — — 3.94 — — —
(IOH = 20 mA) 3.4 — 3.4 3.70 — 3.0 —
(IOH = 25 mA) — — — 3.54 — — —
(IOH = 0 mA) 10 9.1 — 9.1 9.58 — 9.1 — Vdc
(IOH = 5.0 mA) — — — 9.26 — — —
(IOH = 10 mA) 9.0 — 9.0 9.17 — 8.6 —
(IOH = 15 mA) — — — 9.04 — — —
(IOH = 20 mA) 8.6 — 8.6 8.90 — 8.2 —
(IOH = 25 mA) — — — 8.75 — — —
(IOH = 0 mA) 15 14.1 — 14.1 14.59 — 14.1 — Vdc
(IOH = 5.0 mA) — — — 14.27 — — —
(IOH = 10 mA) 14 — 14 14.18 — 13.6 —
(IOH = 15 mA) — — — 14.07 — — —
(IOH = 20 mA) 13.6 — 13.6 13.95 — 13.2 —
(IOH = 25 mA) — — — 13.80 — — —
(continued)

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 MC14513B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Drive Current — RBO Output IOH mAdc
(VOH = 2.5 V) Source 5.0 – 0.40 — – 0.32 – 0.64 — – 0.22 —
(VOH = 9.5 V) 10 – 0.21 — – 0.17 – 0.34 — – 0.12 —
(VOH = 13.5 V) 15 – 0.81 — – 0.66 – 1.30 — – 0.46 —
(VOL = 0.4 V) Sink IOL 5.0 0.18 — 0.15 0.29 — 0.10 — mAdc
(VOL = 0.5 V) 10 0.47 — 0.38 0.75 — 0.26 —
(VOL = 1.5 V) 15 1.80 — 1.50 2.90 — 1.0 —

Output Drive Current — Segments IOL mAdc

(VOL = 0.4 V) Sink 5.0 0.64 — 0.51 0.88 — 0.36 —
(VOL = 0.5 V) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 V) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) Vin = 0 or VDD, 10 — 10 — 0.010 10 — 300
Iout = 0 µA 15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT 5.0 IT = (1.9 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.8 µA/kHz) f + IDD
Per Package) 15 IT = (5.7 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
4. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.
All outputs connected to respective CL loads.
20 ns 20 ns
VDD
90%
A, B, AND C 50%
1 10% VSS
2f
50% DUTY CYCLE
VOH
ANY OUTPUT 50%
VOL

Figure 1. Dynamic Power Dissipation Signal Waveforms

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 MC14513B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

Characteristic Symbol
VDD
Vdc Min
All Types
Typ Max Unit
Output Rise Time — Segment Outputs tTLH ns
5.0 — 40 80
10 — 30 60
15 — 25 50
Output Rise Time — RBO Output tTLH ns
5.0 — 480 960
10 — 240 480
15 — 190 380
Output Fall Time — Segment Outputs (7.) tTHL ns
tTHL = (1.5 ns/pF) CL + 50 ns 5.0 — 125 250
tTHL = (0.75 ns/pF) CL + 37.5 ns 10 — 75 150
tTHL = (0.55 ns/pF) CL + 37.5 ns 15 — 65 130
Output Fall Time — RBO Outputs tTHL ns
tTHL = (3.25 ns/pF) CL + 107.5 ns 5.0 — 270 540
tTHL = (1.35 ns/pF) CL + 67.5 ns 10 — 135 270
tTHL = (0.95 ns/pF) CL + 62.5 ns 15 — 110 220
Propagation Delay Time — A, B, C, D Inputs (7.) tPLH ns
tPLH = (0.40 ns/pF) CL + 620 ns 5.0 — 640 1280
tPLH = (0.25 ns/pF) CL + 237.5 ns 10 — 250 500
tPLH = (0.20 ns/pF) CL + 165 ns 15 — 175 350
tPHL = (1.3 ns/pF) CL + 655 ns tPHL 5.0 — 720 1440 ns
tPHL = (0.60 ns/pF) CL + 260 ns 10 — 290 580
tPHL = (0.35 ns/pF) CL + 182.5 ns 15 — 200 400

Propagation Delay Time — RBI and BI Inputs (7.) tPLH ns

tPLH = (1.05 ns/pF) CL + 547.5 ns 5.0 — 600 750
tPLH = (0.45 ns/pF) CL + 177.5 ns 10 — 200 300
tPLH = (0.30 ns/pF) CL + 135 ns 15 — 150 220

tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL 5.0 — 485 970 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns 10 — 200 400
tPHL = (0.35 ns/pF) CL + 142.5 ns 15 — 160 320

Propagation Delay Time — LT Input (7.) tPLH ns

tPLH = (0.45 ns/pF) CL + 290.5 ns 5.0 — 313 625
tPLH = (0.25 ns/pF) CL + 112.5 ns 10 — 125 250
tPLH = (0.20 ns/pF) CL + 80 ns 15 — 90 180

tPHL = (1.3 ns/pF) CL + 248 ns tPHL 5.0 — 313 625 ns

tPHL = (0.45 ns/pF) CL + 102.5 ns 10 — 125 250
tPHL = (0.35 ns/pF) CL + 72.5 ns 15 — 90 180

Setup Time tsu 5.0 100 — — ns

10 40 — —
15 30 — —
Hold Time th 5.0 60 — — ns
10 40 — —
15 30 — —
Latch Enable Pulse Width tWL(LE) 5.0 520 260 — ns
10 220 110 —
15 130 65 —
7. The formulas given are for the typical characteristics only.

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 MC14513B

20 ns 20 ns
90% VDD

INPUT C 50%
10% VSS
tPLH tPHL
VOH
OUTPUT g
VOL
tTLH tTHL

a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.

20 ns 20 ns
90% VDD
INPUT C 50%
10% VSS
tPLH tPHL
VOH
90%
OUTPUT RBO 50%
10% VOL
tTLH tTHL

b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.

20 ns
VDD
90%
LE 50%
10% VSS
th
tsu
VDD

INPUT C 50%
VSS

VOH
OUTPUT g
VOL

c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.

20 ns
20 ns
VDD
90%
50%
10%
LE VSS
tWL(LE)

d. Pulse Width: Data DCBA strobed into latches.

Figure 2. Dynamic Signal Waveforms

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 MC14513B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

VDD VDD

COMMON
COMMON ANODE LED
CATHODE LED ≈ 1.7 V

≈ 1.7 V

VSS
VSS

INCANDESCENT READOUT FLUORESCENT READOUT

VDD VDD VDD

**
DIRECT
(LOW BRIGHTNESS)

FILAMENT
(SUPPLY)
VSS VSS VSS OR APPROPRIATE
VOLTAGE BELOW VSS.

GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) READOUT

EXCITATION
APPROPRIATE (SQUARE WAVE,
VDD VOLTAGE VDD VSS TO VDD)

1/4 OF MC14070B

VSS VSS
** A filament pre–warm resistor is recommended to reduce
filament thermal shock and increase the effective cold Direct dc drive of LC’s not recommended for life of LC readouts.
resistance of the filament.

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 MC14513B

LOGIC DIAGRAM

BI 4

15 a

A 7
14 b

13 c

B 1 12 d

11 e

17 f
C 2
16 g
LT 30
RBI 8 10 RBO
D 6

LE 5

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 MC14513B

TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

DISPLAYS

a–– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – –– g a–– – – –g

CONNECT TO
RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO
VDD (1) D C B A 1 D C B A 1 D C B A 0 D C B A 0 D C B A 0 D C B A 0

MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

INPUT 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1
CODE (0) (0) (5) (0) (1) (3)

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS

a–– – –– g a –– – –– g a –– – ––g a–– – –– g a –– – ––g a –– – ––g CONNECT TO

0
RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI RBO RBI
D C B A 0 D C B A 0 D C B A 0 D C B A 1 D C B A 1 D C B A VDD (1)

MC14513B MC14513B MC14513B MC14513B MC14513B MC14513B

0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0
(5) (0) (1) (3) (0) (0) INPUT CODE

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 MC14513B

PACKAGE DIMENSIONS

PDIP–18
P SUFFIX
PLASTIC DIP PACKAGE
CASE 707–02
ISSUE C

NOTES:
J 1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
18 10
2. DIMENSION L TO CENTER OF LEADS WHEN
B L FORMED PARALLEL.
1 9 3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. CONTROLLING DIMENSION: INCH.

A M INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.875 0.915 22.22 23.24
C B 0.240 0.260 6.10 6.60
C 0.140 0.180 3.56 4.57
D 0.014 0.022 0.36 0.56
F 0.050 0.070 1.27 1.78
N K G 0.100 BSC 2.54 BSC
H 0.040 0.060 1.02 1.52
F D SEATING J 0.008 0.012 0.20 0.30
PLANE K 0.115 0.135 2.92 3.43
H G L 0.300 BSC 7.62 BSC
M 0_ 15_ 0_ 15 _
N 0.020 0.040 0.51 1.02

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 MC14513B

Notes

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 MC14513B

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