Bahir Dar Institute of Technology

Bahir Dar University

Faculty of Electrical and Computer Engineering

VLSI DESIGN Laboratory Manual

November 2015
VLSI Design Laboratory Manual

Version 1.0

Prepared by: Tesfamichael A.

November 2015

i
Copyright © 2015 by Bahir Dar Institute of Technology, Bahir Dar University

No part of this manual may be reproduced, transmitted by any means, electronic, photocopying, scanning or
otherwise, without the prior written permission or authorization of the owner Bahir Dar Institute of Technology,
Faculty of Electrical Engineering, Bahir Dar University.
Requests for permission can be addressed to, Bahir Dar Institute of Technology-Bahir Dar University,
P.O.Box 26, Bahir Dar-Ethiopia

ii
List of Experiments

Experiments Topics
Familiarization  Introduction to the Xilinx ISE Design Suite
Part- I Basic logic gates
Experiment-1  AND, OR, NOT gates (behavioral description)
 NAND, NOR, XOR gates (behavioral and structural
Experiment -2
descriptions)
 Delay description in VHDL
Experiment -3
o AND, OR, NOT, NAND, NOR, XOR
Part- II Combinational circuits
 Multiplexer
Experiment -4
 Decoder

Experiment -5  Adder

Part-III Sequential circuits

Experiment -6  Latches and Flip-flops

Experiment -7  Registers (4,8, 16 bit)

Experiment -8  Up and down counters

Experiment -9  Implementation and testing on an FPGA (Xilinx FPGA)

Part -IV Microcontroller ALU design

Assignment  ALU design of a microcontroller

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Introduction to the Xilinx ISE Design Suite

The Xilinx ISE webpack (design foundation) is a tool that we are going to use in the design of digital
integrated circuits regardless of the scale of integration.

Creating New Project

1. Open ISE Project Navigator from the desktop shortcut ( ) or from the StartProgram
filesXilinx design tools Project navigator. You will get the following screen.

Figure F.1 Project navigator start up screen

 To create a new project, click the button ‘New Project’ or go to FileNew Project as
shown in figure F.2.

Figure F.2 Options for opening a new project

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2. Clicking the ‘New Project’ command brings new project wizard as shown in figure F.3. Provide
the name of your project and the location where you want to save your project. The working
directory will adjust itself based on the location you provided. You can also write the description
of the project (if you want). The 'top-level source type' option should be 'HDL' (leave the
default).

Figure F.3 New project wizard

3. Click 'Next' after specifying the 'Name' of the project and the location. You will see the
following screen shown in figure F.4

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 Figure F.4 New project wizard showing (FPGA) device selection and other settings
4. Select the preferred language option (shown in figure F.4) to 'VHDL' and leave the rest of the
options in the default setup. Clicking 'Next' shows you the new project and the device selection
summary.

Figure F.5 Summary of the new project

5. Click 'Finish' and you are done creating a new project. You will presented with the following
window (figure F.6)

Project name

FPGA device

Figure F.6 Project navigator window with new project

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Adding VHDL module to your project
The following steps can be followed only if you have already created a new project or you have an
existing project opened. To open a project FileOpen Project then select the project file with .xise
extension. The project navigator will show you a window as shown below.
1. You have two options to add new VHDL module as indicated in the figure F.7 below.
a. Click the 'New Source' icon as shown in the left figure or
b. Right click on the project hierarchy area and click on 'New Source' as indicated on the
right figure.

Figure F.7 Adding new VHDL source to a project

2. Clicking 'New Source' brings the wizard as shown in figure 1.8. Select the 'VHDL module’ and
provide the file name. The location will be automatically set based on the project setup. (Make
sure that the 'Add to project' check box is checked (It's checked by default).

Figure F.8 New Source wizard showing the list of source (file) type for selection

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3. After clicking 'Next', you will be asked to define the ports of the module you have created in the
previous step. If you are already familiar with the VHDL 'entity' construct, then you can define the
ports of the module. Otherwise, let us skip this step for now by clicking 'Next'.

Figure F.9 Entity definition (Module port definition) section of 'New source wizard'

4. Clicking next in the previous window takes you to the 'Summary' page as shown below. Click
'Finish' button to complete the process of adding a new VHDL module into the project. You can
skim the summary and if you want to change something, click 'Back' button.

Figure F.10 Adding new source summary

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5. After completion of 'adding new source', the project navigator will look like the following (Figure
F.11). The two sections that you should note on the project navigator are indicated by callouts.
If you want to add more new modules in the same project, then repeat the steps 1-4 described
above.

The 'New Source' added Automatically generated

in the project VHDL code by project
navigator.

Figure F.11 Look of the project navigator after a new VHDL module is added.

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Simulation
One of the steps of a VLSI design is testing & verification of the functionality of the system, the timing
requirement and others. One way of doing this important step is by performing simulations. Although
simulation is performed in a virtual environment using hardware component models, it provides very
important information about the characteristics of the real hardware after manufacturing.
Xilinx ISE project navigator has an integrated simulator known as ISim. The following few procedures
illustrate how to use the ISE project navigator to perform simulations.
Note: The following procedure assumes that you have an opened project and you have added
VHDL module(s). (You can refer the previous sections to open a new project and to add new
VHDL modules into the project).

1. By default, after you opened a new project the view mode in the project navigator (Design
Hierarchy) is set to be 'Implementation' as shown in figure F.12.

The three small cubes in front of the file

name (of the VHDL module) indicates the
'top' module in the design.

Note: a top module can have other

modules inside of it

These are design implementation

steps on an FPGA

Figure F.12 Project navigator showing the design 'implementation' view mode

2. Before implementation, the design has to be tested. Therefore, to switch the view mode, simply
select 'Simulation radio button' and you will get the view as shown in figure F.13 - which looks
more or less the same view as implementation mode except that in the implementation view
mode, you can't see the test bench modules.

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 Figure F.13 Project navigator showing the design 'Simulation' view mode

3. So far, we have only the design (andGate module). Now, let's create a test bench to check the
functionality of the design by providing different input combinations. This procedure is the same
as adding new VHDL module into the project as can be seen in the previous section. The only
difference is the type of module to be added.
Right click anywhere in the hierarchy and select 'New Source' or click the 'New Source' icon.
You will get the type selection window as shown in figure F.14. Select the 'VHDL Test bench'
and provide the file name and click 'Next'.

Figure F.14 Adding new source wizard

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4. After clicking 'Next' in the previous step, the new source wizard asks you to select the
design/source to be associated to the test bench. For now, you have one design called 'andGate'
and that is what you want to test. (see figure F.15) Clicking 'Next' will give you summary of the
new source and click 'Finish' to complete the process of adding the test bench module.

Figure F.15 Selecting the design module to be associated to the test bench module

5. After adding the test bench module to the project, you will see that the module to be tested is
now under the hierarchy of the test bench module as shown in figure F.16. The project navigator
also adds automatically generated code to the test bench module and it checks the syntax of the
code. Don't worry about the syntax error messages that you see in the lower side of the window.
It'll be gone when you re-write the code later.

ISim simulator options

This is where you see

compilation information

Figure F.16 Project navigator showing the hierarch of the test bench and the associated module

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6. Click (select) the test bench module (tb_andGate). You will see that the ISim simulator appears
in the middle-left of the window (shown in figure F.16) with two options under it.
 Double-click the 'Behavioral Check Syntax’ or 'Right-click on it and click run' to check
if there are syntax problems when you write the VHDL code. The simulator checks the
syntax and if there are errors, warnings and other information, the project navigator informs
you about it in the lower section of the window. You can follow the progress of compilation
process in the 'console' tab and the errors and warnings can be seen in the 'errors' and
'warnings' tab.
 If the syntax checking is successful (indicated by symbol), you can Double-click on
the 'Simulate Behavioral Model' command or 'right-click on it and click run'. ISim will
run in a new window which will look like figure F.17 if you have proper test bench.

You can see the simulation

waveforms for inputs and outputs

Figure F.17 ISim window showing the simulation waveforms

 By analyzing the waveforms in the simulation window, you can verify if the design is working
as desired. If the result obtained during simulation is not as expected, you need to go back and
check your code, modify it and re-run the simulation.

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Implementation
Implementation refers to the process of translating the textual hardware description into logic gates
and mapping the logic in the FPGA device. This process is handled by automation tools like the Xilinx
ISE project navigator. Briefly presented in this section is the process of implementing the design into
the FPGA device. (Detailed explanation will be given during demonstration sessions).
1. Make sure that you have opened project with at least one source (VHDL) module in it.
2. Change the view mode in the project navigator to 'Implementation' as shown in figure F.18 and
select the VHDL module that you want to implement. Clicking the module is not enough when
more than one module is available in the project. Follow the following steps to select the module
for implementation: Right click on the moduleSet as Top Module. This will put the three
little squares in front of the module indicating that the module is ready for implementation.

Figure F.18 Design view mode set to 'Implementation'

3. Before the implementation step, the VHDL code has to be checked and synthesized. To do this,
double-click on 'Synthesize-XST' or right-click on it run as indicated in figure F.19.
4. If there are no errors in the synthesis process (some warnings can be ignored), double-click
on 'Implement Design' or right-click on it run as shown in figure F.20. The implementation
process involves three steps as indicated in the same figure (translate, map and place & route).
This step requires that the target device (FPGA) is set first - otherwise, translation, mapping and
routing your design cannot be done.
5. When the implementation process is completed successfully, the configuration file can be
generated by double-clicking on 'Generate Programming file' command or right-click on it
run. (To successfully complete this process, a user constraint file is necessary)
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6. If the configuration file is successfully generated, the target device can be configured by
'double-clicking on the 'Configure Target Device' option. To successfully execute this process
the FPGA has to be connected to your computer. This will be demonstrated in the lab.

Figure F.19 Synthesizing the design

Target device (FPGA) - this is set

when the project was created.

When the synthesis operation

is completed, you can get the
status of the process here

Figure F.20 Implementation step

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 PART-1: BASIC LOGIC GATES

Experiment -1 Basic logic gates - I

Objectives
 To describe the AND, OR and NOT logic gates using VHDL
 To understand the characteristics of the basic logic gates
Tools required:
 A computer with Xilinx ISE Design Suite (Webpack) installed
Theory:
An AND gate is a logic circuit having two or more inputs and one output. The output of an AND gate
is HIGH only when all of its inputs are in the HIGH state. In all other cases, the output is LOW. The
logic symbol and the truth table of a two-input AND gate are shown in figure 1.1. The AND operation
on two independent logic variables A and B is written as Y=A.B and reads as Y equals A AND B.

Figure 1.1 AND gate symbol and truth table

An OR gate performs an ORing operation on two or more than two logic variables. The OR operation
on two independent logic variables A and B is written as Y=A+B and reads as Y equals A OR B.
The output of an OR gate is LOW only when all of its inputs are LOW. For all other possible input
combinations, the output is HIGH. The circuit symbol and the truth-table of a two-input OR gate is
shown in figure 1.2.

Figure 1.2 OR gate symbol and truth table

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 A NOT gate is a one-input, one-output logic circuit whose output is always the complement of the
input. That is, a LOW input produces a HIGH output, and vice versa. It is also known as a
'complementing circuit' or an 'inverting circuit'. Figure 1.3 shows the circuit symbol and truth-table.

Figure 1.3 NOT gate symbol and truth table

Part-A: AND gate description

Procedure:
1. Open ISE Design Suite (Project navigator) by double clicking the shortcut icon on the desktop or
from the start menu.
2. Create a new project and provide appropriate name for the project.
3. Add new VHDL module with a name 'andGate'.
4. Replace the code automatically generated by the project navigator with the following VHDL code.

1 -----------------------
2 -- AND gate description
3 ------------------------
4 LIBRARY IEEE;
5 USE IEEE.STD_LOGIC_1164.ALL;
6 ----------------------------
7 ENTITY andGate IS
8 PORT(a: IN std_logic;
9 b: IN std_logic;
10 c: OUT std_logic);
11 END andGate;
12 --------------------
13 ARCHITECTURE behav OF andGate IS
14 BEGIN
15 --c<= a AND b;
16 PROCESS (a,b) IS
17 BEGIN
18 IF (a='1' AND b='1') THEN
19 c<='1';
20 ELSE
21 c<='0';
22 END IF;
23 END PROCESS;
24 END behav;
25 --------------------------------

5. Add new test bench module and name it 'tb_andGate'.

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 1 -----------------------------------
2 -- This is a testbench for andGate
3 -----------------------------------
4 LIBRARY ieee;
5 USE ieee.std_logic_1164.ALL;
6 ----------------------------
7 ENTITY tb_andGate IS -- no port description is needed
8 END entity tb_andGate;
9 -------------------------------------
10 ARCHITECTURE behavior OF tb_andGate IS
11 -- Component Declaration for the Unit Under Test (UUT)
12 COMPONENT andGate
13 PORT(a : IN std_logic;
14 b : IN std_logic;
15 c : OUT std_logic );
16 END COMPONENT;
17 --Inputs
18 SIGNAL a : std_logic := '0'; -- initializing a and b to logic '0'.
19 SIGNAL b : std_logic := '0';
20 --Output
21 signal c : std_logic;
22 BEGIN
23 -- Instantiate the Unit Under Test (UUT) - andGate
24 uut: andGate PORT MAP (a => a, b => b, c => c );
25
26 -- Generate test signals
27 a<='0','1' after 20 ns;
28 b<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
29
30 END architecture behavior;
31 -----------------------------------------------------------

6. Simulate the design and verify if the output obtained is as expected.

Exercise:
 Replace the sequential statements in the 'andGate' architecture by the following concurrent
statement ** and compare the simulation result.

13 ARCHITECTURE behav OF andGate IS

14 BEGIN
15 c<= a AND b;
16 END behav;

o Is there a difference between the previous and the current simulation results?

___________________________
** In the previous design, the architecture was described by sequential statements and now it is replaced by
'a concurrent statement' - placed in a 'process' construct.

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Part-B: OR gate description

Procedure
1. Right click on the project name you created in the previous experiment and choose 'new source'
in the dialog menu.
2. Provide the file name 'orGate' for the new VHDL module.
3. Add the following code (modification of the 'andGate' described in part-A)
1 -----------------------
2 -- OR gate description
3 ------------------------
4 LIBRARY IEEE;
5 USE IEEE.STD_LOGIC_1164.ALL;
6 ----------------------------
7 ENTITY orGate IS
8 PORT(a: IN std_logic;
9 b: IN std_logic;
10 c: OUT std_logic);
11 END orGate;
12 --------------------
13 ARCHITECTURE behav OF orGate IS
14 BEGIN
15 --c<= a OR b;
16 PROCESS (a,b) IS
17 BEGIN
18 IF (a='0' AND b='0') THEN
19 c<='0';
20 ELSE
21 c<='1';
22 END IF;
23 END PROCESS;
24 END behav;
25 --------------------------------

4. Also, add a test bench module just like the one shown in part-A with appropriate modifications
on the name of the 'entity', the 'component' declaration and the 'instantiation'.
5. Run the test bench using ISim and verify that the output waveform is as expected.

Exercise:

 Replace the 'process' block by the concurrent statement and re-run the simulation. Are the results
the same?
 Write VHDL description of the NOT logic gate using concurrent statement(s) and sequential
statements. Also, write a test bench to verify the correctness of the description.

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Experiment -2 Basic logic gates - II

Objectives
 To describe the NAND, NOR and XOR logic gates using VHDL
 To understand the characteristics of the logic gates
Tools required:
 A computer with Xilinx ISE Design Suite (Webpack) installed
Theory:
NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a NAND gate. The
output of a NAND gate is a logic '0' or LOW when all its inputs are a logic '1' or HIGH. For all other
input combinations, the output is a logic '1'. The circuit symbol of a two-input NAND gate and the
truth-table are shown in figure 2.1.

Figure 2.1 AND gate symbol and truth table

NOR stands for NOT OR - an OR gate followed by a NOT gate. Its output is a logic '1' when all its
inputs are '0' otherwise, the output logic is '0'. The logic symbol and the truth table are shown in
figure 2.2.

Figure 2.2 NOR gate symbol and truth table

An EXCLUSIVE-OR gate, commonly written as EX-OR or XOR gate, is a two-input, one-output

gate with the logic symbol and truth table as shown below. The output of an XOR gate is '1' when
the inputs are unlike and a logic '0' when the inputs are like.

Figure 2.3 XOR gate symbol and truth table

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Part-A: NAND gate description

Procedure:
1. Create a new VHDL module named 'nandGate' by right clicking the project you created in the
previous experiment. If you don't have an existing project, please follow the procedure in
experiment-1 to create a new project.
2. Replace the auto generated file by the following code. This is behavioral description of the NAND
gate.

1 -----------------------------
2 -- NAND gate description
3 -----------------------------
4 library IEEE;
5 use IEEE.STD_LOGIC_1164.ALL;
6 -----------------------------
7 entity nandGate is
8 port(a: in std_logic;
9 b: in std_logic;
10 c: out std_logic);
11 end nandGate;
12 --------------------------------------
13 architecture behave of nandGate is
14 begin
15 process (a,b) is
16 begin
17 if(a='1' and b='1') then
18 c<='0';
19 else
20 c<='1';
21 end if;
22 end process;
23
24 end behave;
25 --------------------------------------

3. Write test bench to verify that the NAND gate described works as desired. You can take the test
bench code from the previous experiment and make appropriate modification to it.
4. Another way of writing the description of the NAND gate is by considering the structure of the
NAND gate. It can be constructed from an AND gate and a NOT gate (AND gate followed by
NOT gate) as shown in the figure 2.4. Change the previous code with the following VHDL code.

Figure 2.4 NOR gate symbol and truth table

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 1 -----------------------------------
2 -- NAND gate structural description
3 -----------------------------------
4 library IEEE;
5 use IEEE.STD_LOGIC_1164.ALL;
6 -----------------------------
7 entity nandGate is
8 port(a: in std_logic;
9 b: in std_logic;
10 c: out std_logic);
11 end nandGate;
12 ----------------------------------
13 architecture struct of nandGate is
14 component andGate is
15 port(a: in std_logic;
16 b: in std_logic;
17 c: out std_logic);
18 end component;
19 component notGate is
20 port(a: in std_logic;
21 c: out std_logic);
22 end component;
23
24 signal sig: std_logic;
25 begin
26
27 u1: andGate port map(a,b,sig);
28 u2: notGate port map(sig,c);
29
30 end struct;
31 ---------------------------------

Remember: you must have the 'andGate' and the 'notGate' modules in the project for the
description to work.
5. Use the test bench you wrote in procedure 3 to test the structural description of the NAND gate.

Part-B: XOR gate description

Procedure:
1. Create a new VHDL module named 'xorGate' in the same project you have created in part-A.
2. Write the behavioral description of the XOR gate as shown below.

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 1 -----------------------------------
2 -- XOR gate behavioral description
3 -----------------------------------
4 library IEEE;
5 use IEEE.STD_LOGIC_1164.ALL;
6 ----------------------------
7 entity xorGate is
8 port(a: in std_logic;
9 b: in std_logic;
10 c: out std_logic);
11 end xorGate;
12 ----------------------------------
13 architecture behave of xorGate is
14 begin
15 process (a,b) is
16 begin
17 if(a=b) then
18 c<='0';
19 else
20 c<='1';
21 end if;
22 end process;
23 end behave;
24 ----------------------------------

3. Write a test bench for the XOR gate and verify the design. You can use the same test bench
used in the previous experiments with slight modifications.

Exercise:

 Write VHDL description of the NOR gate using

a) behavioral description and
b) structural description
 Write the test bench to verify the NOR gate you've described in (1).
 Using the same test bench, simulate both the behavioral and structural descriptions. You should
get the same result.

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Experiment -3 Delay analysis and Description

Objectives
 To understand the delays associated to the basic gates
 To learn the VHDL construct used to describe delay

Tools required:
 A computer with Xilinx ISE Design Suite (Webpack) installed

Theory:
Delay in logic gates is simply defined as the time taken for a signal to propagate from the inputs
to the outputs through the gates. This is formally called 'propagation delay, '.
Propagation delay defines how quickly the gate responds to a change at its input(s). It is
measured between the 50% transition points of the input and output waveforms as shown in
figure 3.1 (for a not gate). It should be noted that a gate displays different response times for
rising and falling input waveforms. The defines the response time of the gate for low to
high output transition, while refers to a high to low transition. The average of the two defines
the propagation delay of the gate.
+
=
2

Figure 3.1 Propagation delay for an inverter

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Description of the AND gate with delay

Procedure:
1. Open the project you have created in the previous experiments.
2. Change the project view mode to 'Simulation'.
3. Open the 'andGate' file and modify the VHDL code as shown below. [The output 'c' gets its value
5 nanoseconds after the input signals changed -delay of 5 ns].

1 -----------------------
2 -- AND gate description with DELAY
3 ------------------------
4 LIBRARY IEEE;
5 USE IEEE.STD_LOGIC_1164.ALL;
6 ----------------------------
7 ENTITY andGate IS
8 PORT(a: IN std_logic;
9 b: IN std_logic;
10 c: OUT std_logic);
11 END andGate;
12 --------------------
13 ARCHITECTURE behav OF andGate IS
14 BEGIN
15 --c<= a AND b;
16 PROCESS (a,b) IS
17 BEGIN
18 IF (a='1' AND b='1') THEN
19 c<='1' after 5 ns;
20 ELSE
21 c<='0' after 5 ns;
22 END IF;
23 END PROCESS;
24 END behav;
25 --------------------------------

4. Run the simulation using the same test bench written for it`. Compare the waveforms with and
without delay.
5. Repeat the procedures 1 to 4 for other logic gates 'OR' and 'NOT' gates.

Exercise

 Now that you have the VHDL description of the basic logic gates (AND, NOT and OR) with
delays. Run the simulation for the 'NAND' and the 'NOR' gates and analyze the waveforms.
o Estimate what the overall delay will be for the 'NAND' and 'NOR' gates from the schematic
diagram.
o Run the simulation for the 'NAND' and the 'NOR' gates and analyze the waveforms. How
much is the delay for the 'NAND' gate and 'NOR' gate?
o Compare the result you got from the waveform and the estimate. Is it different?

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 PART-II: COMBINATIONAL CIRCUITS

Experiment -4 Combinational circuits (Multiplexer and Decoder)

Objectives
 To learn how combinational circuits are described using VHDL (Multiplexer, decoder and adder)

Tools required:
 A computer with Xilinx ISE Design Suite installed

Theory:
 Multiplexer
The multiplexer allows the selection of one input signal among n signals, where > 1 . Select
lines connected to the multiplexer determine which input signal is selected and passed to the output
of the multiplexer. In general, an n-to-1 multiplexer has n data input lines, s selected lines where =
log , i.e. 2 = , and one output line. For a 2-to-1 multiplexer, there is one select line s to select
between the two inputs, and . When = 0, the input line is selected, and the data present
on is passed to the output . When = 1, the input line is selected and the data on is
passed to . Constructing a larger multiplexer can be done in the similarly.
The truth table, circuit and logic symbol for a 2-to-1 multiplexer are shown in figure 4.1.

= ̅+

Figure 4.1 2-to-1 multiplexer circuit diagram, truth table and symbol

 Decoder
A decoder (also known as demultiplexer) asserts one out of n output lines depending on the value
of an m-bit binary input data. In general, an m-to-n decoder has m input lines, ,…, , and n
output lines, ,…, where = 2 . In addition, it has enable line E for enabling the decoder.

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 When the decoder is disabled with E set to 0, all the output lines are de-asserted. When the decoder
is enabled, the output line whose index is equal to the value of the input binary data is asserted. The
circuit and logic symbol for a 3-to-8 decoder is shown in figure 4.2.

Figure 4.2 3-to-8 decoder circuit diagram and symbol

Multiplexer

Procedure:
1. Open your previous project or create a new project.
2. Add 'New' VHDL source named 'mux2to1'.
3. Replace the auto generated code with the following code.

1 ----------------------------
2 -- 2 to 1 multiplexer description
3 ----------------------------
4 library ieee;
5 use ieee.std_logic_1164.all;
6 ----------------
7 entity mux2to1 is
8 port(in1 : in std_logic;
9 in2 : in std_logic;
10 sel : in std_logic;
11 out1: out std_logic);
12 end entity;
13 -------------------
14 architecture behav of mux2to1 is
15 begin
16 out1<=in1 when sel='0' else in2 ;
17 end architecture behav;
18 --------------------------

4. To test the multiplexer, add a test bench module with a name 'tb_mux2to1' and write the following
code in it.
5. Simulate the description and observe the output waveform.
6. Re-write the description of the multiplexer structurally based on the circuit shown above and run
the same test bench to check the functionality of the design.

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 1 ------------------------------
2 -- test bench for mux2to1
3 ------------------------------
4 LIBRARY ieee;
5 USE ieee.std_logic_1164.ALL;
6 ----------------------------
7 ENTITY tb_mux2to1 IS
8 END tb_mux2to1;
9 ------------------------
10 ARCHITECTURE behavior OF tb_mux2to1 IS
11 -- Component Declaration for the Unit Under Test (UUT)
12 COMPONENT mux2to1
13 PORT(in1 : IN std_logic;
14 in2 : IN std_logic;
15 sel : IN std_logic;
16 out1 : OUT std_logic );
17 END COMPONENT;
18 --Inputs
19 signal in1 : std_logic := '0';
20 signal in2 : std_logic := '0';
21 signal sel : std_logic := '0';
22 --Outputs
23 signal out1 : std_logic;
24
25 BEGIN
26 uut: mux2to1 PORT MAP (in1 => in1,
27 in2 => in2,
28 sel => sel,
29 out1 => out1);
30 in1<=not in1 after 10 ns;
31 in2<=not in2 after 20 ns;
32 sel<='0' after 50 ns, '1' after 400 ns,
'0' after 500 ns;
33 END;
34 ------------------------------------------

Decoder
 Follow the same procedure as above to describe a decoder circuit as shown in the theory section
of this experiment. Describing the decoder circuit structurally is a tedious task especially when
the number of inputs is large. So, behavioral description is a preferred method to handle such
cases.
 Write the VHDL code for a BCD-to-7 segment decoder.
The BCD-to-7 segment decoder accepts the BCD code on its inputs and provides outputs to
drive 7-segment display devices to produce a decimal readout.

Figure 4.3 BCD to seven segment decoder and seven segment display

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Experiment -5 Combinational circuits (Adders)

Objectives
 To learn how combinational circuits are described using VHDL (Adders)

Tools required:
 A computer with Xilinx ISE Design Suite installed

Theory:

 Adder
Adders are important in computers and also in other types of digital systems in which numerical
data are processed.
Half-adder:
A half-adder is an arithmetic circuit block that can be used to add two bits. Such a circuit thus has
two inputs that represent the two bits to be added and two outputs, with one producing the SUM
output and the other producing the CARRY. Figure 5.1 shows the truth table of a half-adder and
symbol. The Boolean expressions for the SUM and CARRY outputs are given by the equations
= . + ̅. = .

Figure 5.1 Half adder circuit, truth table and symbol

Full Adder:
A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM
and CARRY output. Such a building block becomes a necessity when it comes to adding binary
numbers with a large number of bits. The full adder circuit overcomes the limitation of the half-adder,
which can be used to add two bits only. The implementation of full adder using half adders is shown
in figure 5.2.

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 Figure 5.2 Full adder circuit implementation using half adder

Procedure
 The simplest adder circuit is the half-adder which takes only two bits as explained above. Using
the half-adder one can implement more useful circuit called the full adder that accepts three inputs
one of which is the carry input.
 Write the VHDL code that describes the
a) half-adder
b) full-adder
A single full adder circuit can be used to add one-bit binary numbers only. A cascade arrangement of
these adders can be used to construct adders capable of adding binary numbers with a larger number
of bits. For example, a four-bit binary adder would require four full adders connected in cascade.
Figure 5.3 shows the arrangement where and are the two binary numbers to
be added with and representing least significant bits (LSBs) and and representing most
significant bits (MSBs) of the two numbers.

Figure 5.3 Ripple carry adder

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 Write the description of a four-bit adder based on the structure shown above. (You can use the
full adder circuit described earlier). The following VHDL constructs can be used to achieve
compact code.
port( A: in std_logic_vector(3 downto 0); -- this indicates that A is 4 bit binary data
B: in std_logic_vector(3 downto 0);
……….

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 PART-III: SEQUENTIAL CIRCUITS

Experiment -6 Sequential Circuits (Latches and flip-flops)

Objectives
 To learn how sequential circuits are described using VHDL (Latch & Flip-flop)
 To learn concepts of modeling storage elements using VHDL
Tools required:
 A computer with Xilinx ISE Design Suite installed

Theory:
Latches and flip-flops are categories of bistable devices. Bistable devices have two stable states called
SET and RESET - they can retain either of these states indefinitely making them useful as storage
devices. The difference between latches and flip-flops lies on the method used for changing their state
i.e. latches are level-sensitive devices and flip-flops are edge-sensitive. (Flip-flops are edge sensitive
latches). The term edge-sensitivity in context of a clock signal means that output can only change on a
rising edge (LOW-to-HIGH transition) or falling edge (HIGH-to-LOW transition) of the signal.
 Latch: a sequential device that watches the inputs and changes its outputs at any time the clock
signal is high (‘1’).
 Flip-flop: a device that samples its inputs and changes its outputs only at times determined by
clock signal. The most commonly used flip-flop is the D flip-flop. The D stands for 'Data'. The
characteristics of the D flip-flop is that the output of the flip-flop follows the D inputs. Figure 6.1
shows a schematic symbol, truth table and timing diagram for a simple D flip-flop.

Figure 6.1 Flip-flop circuit symbol, truth table and timing diagram

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Latch

Procedure
1. Open your previous project or create a new project.
2. Add 'New' VHDL source named 'latch'.
3. Replace the auto generated code with the following code.

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity latch is
5 Port ( clk : in STD_LOGIC;
6 d : in STD_LOGIC;
7 q : out STD_LOGIC);
8 end latch;
9 architecture Behavioral of latch is
10 begin
11 process (clk,d) is
12 begin
13 if clk='1' then
14 q<=d;
15 end if;
16 end process;
17 end Behavioral;

4. Simulate the model by writing the test bench for it and observe the waveform.

Flip-flop

Procedure
1. Open your previous project or create a new project.
2. Add 'New' VHDL source named 'dff'.
3. Replace the auto generated code with the code shown below.
[Note the VHDL constructs used in the description. clk’event is read as clock-tick-event which
is equivalent to built-in 'rising_edge(clk)' function ]
4. Write the test bench and simulate the model and analyze the waveform.
5. Compare the output waveforms of the latch and flip-flop. Explain their difference.

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 1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 entity dff is
4 Port ( clk : in STD_LOGIC;
5 d : in STD_LOGIC;
6 q : out STD_LOGIC);
7 end dff;
8 architecture Behavioral of dff is
9 begin
10 process (clk) is
11 begin
12 if clk'event and clk='1' then
13 q<=d;
14 end if;
15 end process;
16 end Behavioral;

Exercise
 Re-write the previous code in such a way that the flip-flop can be resettable. Add one addition
port called 'r' and when this signal is '1', the flip-flop resets (q is '0').
 Study other types of flip-flops such as JK flip-flop and others

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Experiment -7 Sequential Circuits (Registers)

Objectives
 To learn how sequential circuits are described using VHDL (Registers)

Tools required:
 A computer with Xilinx ISE Design Suite installed

Theory:
Stated as simply as possible, a register is nothing more than a multi-bit flip-flop. Flip-flops are
single bit storage elements while registers are multi-bit storage elements modeled as a given
number of flip-flops connected in parallel. D flip-flops are usually used to model registers.
Moreover, VHDL models of registers are similar to flip-flop models and only differ in width of the
'data' inputs and outputs. Jumping right into it, figure 7.1 shows the block diagram for a 4-bit
register and the underlying circuit (four D flip flops assembled such that they at as a register)

Figure 7.1 Circuit symbol and implementation of 4-bit register

Procedure
1. Open your previous project or create a new project.
2. Add 'New' VHDL source named 'register4bit'.
3. Replace the auto generated code with the code shown below.
[Note: 'std_logic' data type takes only a single bit, whereas 'std_logic_vector(n-1 downto 0)' is an
array of bits with size n. ]

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 1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 entity register4bit is
4 Port ( clk : in STD_LOGIC;
5 d : in STD_LOGIC_VECTOR (3 downto 0);
6 q : out STD_LOGIC_VECTOR (3 downto 0));
7 end register4bit;
8 architecture Behavioral of register4bit is
9 begin
10 process (clk) is
11 begin
12 if clk'event and clk='1' then
13 q<=d;
14 end if;
15 end process;
16 end Behavioral;

4. Write the test bench and simulate the model and analyze the waveform.

Exercise

 Modify the previous code to model an 8-bit register (or 16-bit register) and simulate the model.
 When simulation begins or power is first applied to a circuit, the output of the flip-flop is unknown.
This is indicated with 'U' in VHDL simulator. Generally, it is a good practice to use resettable
registers so that on power up you can put your system in known state. Modify the previous code
to add the reset operation.
 Write the VHDL code for 4-bit shift register.

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Experiment -8 Sequential Circuits (Counters)

Objectives
 To learn how sequential circuits are described using VHDL (Counters)

Tools required:
 A computer with Xilinx ISE Design Suite installed

Theory:
A counter (actually called a binary counter) is a register that 'counts'. An N-bit counter sequences
through 2 outputs in binary order. Some of the common features of counters include the following:
 resettable: counter value is reset to 0 when 'RESET' is asserted
 loadable: counter value is loaded with N-bit value when 'LOAD' is asserted
 enabled: counter counts only when 'EN' is asserted
 reversible: counter increments or decrements based on 'UP/DOWN' input

One popular term in digital design is the notion of an 'up-down counter'. This counter is nothing more
than a counter that has a control signal that enables the counter to count either up or down. Figure 8.1
shows an 8-bit up-down counter, where 'UP' indicates the control signal that tells the counter to
increment or decrement. The characteristics of this counter are
 The counter overflows when it increments at its maximum value and underflows when decrements
at its minimum value. This is an automatic operation.
 The counter has a signal dedicated to the counter direction. The model indicates that if UP is '1',
the counter counts up. If the UP signal is not asserted, the counter counts down.
 The counter uses the '+' operator for incrementing and the '-' operator for subtraction. [To use the
mathematical operations in VHDL the proper library files must be included: 'use
IEEE.STD_LOGIC_UNSIGNED.ALL;']

Figure 8.1 Up-down counter

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Procedure
1. Open your previous project or create a new project.
2. Add 'New' VHDL source named 'ud_cntr'.
3. Replace the auto generated code with the code shown below.
4. Write the test bench to simulate the model and analyze the resulting waveform.

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_UNSIGNED.ALL;
4
5 entity ud_cntr is
6 Port ( clk : in STD_LOGIC;
7 ud : in STD_LOGIC;
8 count : out STD_LOGIC_VECTOR (7 downto 0));
9 end ud_cntr;
10 architecture Behavioral of ud_cntr is
11 begin
12 process (clk) is
13 variable tmp:std_logic_vector(7 downto 0):=(others=>'0');
14 begin
15 if clk'event and clk='1' then
16 if ud='1' then
17 tmp:=tmp +1;
18 else
19 tmp:=tmp-1;
20 end if;
21 end if;
22 count<=tmp;
23 end process;
24 end Behavioral;

Exercise
 Write the VHDL model of a resettable 8-bit counter. The counter must reset when the 'reset' input
is asserted (HIGH) asynchronously.
 Modify your code in such a way that the counter resets synchronously (with the rising edge of
clock signal)
 Add more features to make the counter general purpose.

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Experiment -9 Implementation and Testing on an FPGA

Objective
 To familiarize with the practical implementation of VHDL designs on the FPGA

Tools required:
 A computer with Xilinx ISE Design Suite installed
 Xilinx FPGA (spartan3 or Virtex-II pro )

Theory

[Refer the first section of the manual on how to implement the VHDL design on the Xilinx FPGA]

[This experiment is to be covered by demonstration]

--------------------------------------------------------------------------------------------------------------------------------

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 PART-IV: ARITHMETIC LOGIC UNIT (ALU) DESIGN

Experiment-10 [Assignment]

Microcontroller ALU design

Identify common ALU operations of an 8-bit microcontroller (say 8051) and write the VHDL model for at
least 10 operations (instructions). If you are interested in the complete operation of the microcontroller,
you can extend the VHDL model for the control unit as well.

---------------------------------------------------END---------------------------------------------------------------

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