MCP37D11 80 Data Sheet DS20006381A

MCP37D11-80
80 Msps, 12-Bit High-Precision Pipelined ADC
Features • Digital Signal Post-Processing (DSPP) Options:

• Sample Rates: - Decimation filters for improved SNR
- 80 Msps for single-channel operation - Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
- 80 Msps/number of channels used
- Noise-Shaping Requantizer (NSR)
• SNR with fIN = 15 MHz and -1 dBFS:
- Phase, Offset and Gain adjust of individual
- 70.9 dBFS (typical) at 80 Msps
channels
• SFDR with fIN = 15 MHz and -1 dBFS:
- Digital Down-Conversion (DDC)
- 92.2 dBc (typical) at 80 Msps
- Continuous wave (CW) beamforming for
• Power Dissipation with LVDS Digital I/O:
octal-channel mode
- 311 mW at 80 Msps
• Serial Peripheral Interface (SPI)
• Power Dissipation with CMOS Digital I/O:
• Auto Sync Mode to synchronize multiple devices
- 248 mW at 80 Msps, Output Clock = 80 MHz
to the same clock
• Power Dissipation Excluding Digital I/O:
• TFBGA-121 package
- 229 mW at 80 Msps
- Dimension: 8 mm x 8 mm x 1.08 mm
• Power-Saving Modes:
- 79 mW during Standby - Includes embedded decoupling capacitors for
reference pins and bandgap output pin
- 22 mW during Shutdown
• Supply Voltage: • AEC-Q100 Qualified (Automotive Applications)
- Digital Section: 1.2V, 1.8V - Temperature Grade 1: -40°C to +125°C
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 VP-P Typical Applications
• Configurable 8-Channel Input MUX: • Communication Instruments
- Single-Channel or Sequential Multi-Channel • Microwave Digital Radio
Sampling • Lidar and Radar
• Input Channel Bandwidth: 500 MHz • High-Speed Test Equipment
• Output Data Format:
• Ultrasound and Sonar Imaging
- Parallel CMOS, DDR LVDS
• Scanners and Low-Power Portable Instruments
• Optional Output Data Randomizer
• Industrial and Consumer Data Acquisition Systems
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
MCP37Dx1-80 Family Comparison(1):

Digital Digital CW Noise-Shaping
Part Number Sample Rate Resolution
Decimation(3) Down-Conversion(3) Beamforming(4) Requantizer(2)
MCP37D11-80 80 Msps 12 Yes Yes Yes Yes
MCP37D21-80 80 Msps 14 Yes Yes Yes No
MCP37D31-80 80 Msps 16(5) Yes Yes Yes No
Note 1: All devices are pin-to-pin compatible.
2: Available in single- and dual-channel modes.
3: Available in single- and dual-channel modes, and octal-channel mode when CW beamforming is enabled.
4: Available in octal-channel mode.
5: 18-bit output is available in MCP37D31-80 with high-order decimation filter setting.
 2020 Microchip Technology Inc. DS20006381A-page 1

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC
Functional Block Diagram
AVDD12 AVDD18 GND DVDD12 DVDD18
Duty Cycle
CLK+ DLL
Clock Correction
CLK- Selection PLL
DCLK+
Output Clock Control
DCLK-
Digital Signal Post-Processing:

(Selectable using Configuration Register Bits)
AIN0+
Input Multiplexer
- Digital Down-Converter (DDC)

AIN0-
Pipelined - Decimation Filter
ADC - Fractional Delay Recovery (FDR)
- Noise-Shaping Requantizer (NSR)
AIN7+
- Continuous Wave (CW) Beamforming
AIN7- - Phase/Offset/Gain Adjustment
VREF+ VREF-
WCK
Output Control:
VCM OVR
Output
- CMOS, DDR LVDS
Data
- Serialized LVDS
SENSE Reference Generator Q [11:0]
Configuration Registers
VBG REF1+ REF1- REF0+ REF0- SDIO SCLK CS SYNC SLAVE
Note 1
Note 1: All external circuit components for REF0/1 and VBG pins are already embedded in the TFBGA-121 package.
DS20006381A-page 2  2020 Microchip Technology Inc.

Description interest. As a result, SNR is improved significantly
within a selected frequency band of interest while
The MCP37D11-80 is an 80 Msps, 12-bit high- SFDR is not affected.
precision pipelined analog-to-digital converter with
configurable input MUX. The differential full-scale analog input range is
programmable up to 2.975 VP-P.
A built-in 8-input multiplexer (MUX) is used to select the
active analog input(s) depending on the user The ADC output data can be coded in two's
configuration. In single-channel operation, the MUX complement or offset binary representation, with or
can be configured to select one of the 8-inputs. In multi- without the data randomizer option. The output data is
channel operation, the selected inputs are sequentially available as full-rate CMOS or Double-Data-Rate
sampled. The input channel selection and the channel (DDR) LVDS.
order are configured using the user-programmable The device also includes various features designed to
configuration register bits. maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
The ADC core operates at up to an 80 Msps rate. In
clock, output data rate control and phase alignment,
single-channel operation, the analog input is sampled
and programmable digital pattern generation. The
at full speed. In multi-channel operation, the effective
device’s operational modes and feature sets are
sample rate per channel is the full speed divided by the
configured using the user-programmable registers.
number of selected channels. For example, if all 8-input
channels are used, each input channel is sampled at AutoSync mode offers a great design flexibility when
10 Msps when the ADC core is running at 80 Msps. multiple devices are used in applications. It allows
Similarly, if only 4-input channels are selected, each multiple devices to sample input synchronously at the
input channel is sampled at 20 Msps when the ADC same clock source.
core is running at 80 Msps. The high dynamic performance with built-in digital
The device features harmonic distortion correction, signal post-processing features makes the device ideal
DAC noise cancellation, power-up calibration, and for various high-performance data acquisition systems,
always-on background calibration which enable high including communications and test equipment,
performance to be maintained consistently across the ultrasound imaging equipment, Lidar, Radar and
extended temperature range. portable instrumentation.
In addition to the data conversion, the device offers The device is available in a lead-free TFBGA-121
exceptional user-selectable built-in digital signal post- package. The device is AEC-Q100 qualified for
processing (DSPP) features that include high-order automotive applications and operates over the
digital decimation filters, digital down-conversion extended temperature range of -40°C to +125°C.
(DDC), fractional delay recovery (FDR), noise-shaping
requantizer (NSR), gain and offset adjustment per Package Type
channel, and continuous wave (CW) beamforming
Bottom View
capability.
SNR can be significantly improved by enabling the
decimation filter and/or noise-shaping requantizer
(NSR) options. The digital down-conversion (DDC)
option can offer great flexibility in advanced RF and
digital communication system designs.
Gain, phase and DC offset can be adjusted
independently for each input channel, allowing for
simplified implementation of continuous wave (CW)
beamforming and ultrasound Doppler imaging
applications.
Dimension: 8 mm x 8 mm x 1.08 mm
In dual or octal-channel mode, the Fractional Delay Ball Pitch: 0.65 mm
Recovery (FDR) feature digitally corrects the difference Ball Diameter: 0.4 mm
in sampling instance between different channels, so
that all inputs appear to have been sampled at the TFBGA-121 Package
same time.
In single or dual-channel mode, the Noise-Shaping
Requantizer (NSR) feature can allow the ADC to
improve SNR beyond a conventional 12-bit ADC. The
NSR reshapes the quantization noise, such that most
of the noise power is pushed outside the frequency of

NOTES:

1.0 PACKAGE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Top View
(Not to Scale)
1 2 3 4 5 6 7 8 9 10 11
A SDIO VCM REF1+ REF1- VBG REF0+ REF0- GND GND AIN4- AIN2+
B SCLK CS GND GND SENSE AVDD12 AVDD12 AVDD18 AVDD18 AIN4+ AIN2-
WCK/ WCK/
C OVR- OVR+ GND GND AVDD12 AVDD12 AVDD12 GND GND AIN6- AIN0+
(WCK) (OVR)
D Q10/Q5- Q11/Q5+ GND GND AVDD12 AVDD12 AVDD12 GND GND AIN6+ AIN0-
E Q8/Q4- Q9/Q4+ GND GND AVDD12 AVDD12 AVDD12 GND GND AIN5+ AIN1+
F Q6/Q3- Q7/Q3+ DVDD18 DVDD18 AVDD12 AVDD12 AVDD12 GND GND AIN5- AIN1-
G Q4/Q2- Q5/Q2+ DVDD18 DVDD18 GND GND AVDD12 AVDD12 GND AIN7- AIN3+
H Q2/Q1- Q3/Q1+ DVDD12 DVDD12 GND GND GND GND GND AIN7+ AIN3-
J Q0/Q0- Q1/Q0+ DVDD12 DVDD12 GND GND GND GND GND VCMIN+ VCMIN-
K TP TP TP DCLK- CAL GND SLAVE ADR0 ADR1 GND GND
L TP TP TP DCLK+ RESET SYNC GND CLK+ CLK- GND AVDD18
Analog
Digital
All others: Supply Voltage
Notes:
• Die dimension: 8 mm x 8 mm x 1.08 mm.
• Ball dimension: (a) Ball Pitch = 0.65 mm, (b) Ball Diameter = 0.4 mm.
• Flip-chip solder ball composition: Sn with Ag 1.8%.
• Solder sphere composition: SAC-405 (Sn/Au 4%/Cu 0.5%).
FIGURE 1-1: TFBGA-121 Package. See Table 1-1 for the pin descriptions. Decoupling capacitors
for reference pins and VBG are embedded in the package. Leave TP pins floating always.

TABLE 1-1: PIN FUNCTION TABLE FOR TFBGA-121 PACKAGE

Ball No. Name I/O Type Description
A1 SDIO Digital Input/ SPI data input/output
Output
A2 VCM Analog Common-mode output voltage (900 mV) for analog input signal
Output Connect a decoupling capacitor (0.1 µF)(1)
A3 REF1+ Differential reference voltage 1 (+/-). Decoupling capacitors are embedded in
A4 REF1- the TFBGA package. Leave these pins floating.
A5 VBG Internal bandgap output voltage
A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave
this pin floating.
A6 REF0+ Differential reference 0 (+/-) voltage. Decoupling capacitors are embedded in
A7 REF0- the TFBGA package. Leave these pins floating.
A8 GND Supply Common ground for analog and digital sections
A9
A10 AIN4- Analog Input Channel 4 differential analog input (-)
A11 AIN2+ Channel 2 differential analog input (+)
B1 SCLK Digital Input SPI serial clock input
B2 CS SPI Chip Select input
B3 GND Supply Common ground for analog and digital sections
B4
B5 SENSE Analog Analog input range selection. See Table 4-2 for SENSE voltage settings.
Input
B6 AVDD12 Supply Supply voltage input (1.2V) for analog section
B7
B8 AVDD18 Supply voltage input (1.8V) for analog section
B9
B10 AIN4+ Channel 4 differential analog input (+)
Analog Input
B11 AIN2- Channel 2 differential analog input (-)
C1 WCK/OVR- Digital WCK: Word clock sync digital output
(WCK) Output OVR: Input overrange indication digital output(2)
C2 WCK/OVR+
(OVR)
C3 GND Supply Common ground for analog and digital sections
C4
C5 AVDD12 Supply voltage input (1.2V) for analog section
C6
C7
C8 GND Common ground pin for analog and digital sections
C9
C10 AIN6- Channel 6 differential analog input (-)
Analog Input
C11 AIN0+ Channel 0 differential analog input (+)
D1 Q10/Q5- Digital Digital data output(3)
Output CMOS = Q10
DDR LVDS = Q5-
D2 Q11/Q5+ Digital data output(3)
CMOS = Q11
DDR LVDS = Q5+
D3 GND Supply Common ground for analog and digital sections
D4

TABLE 1-1: PIN FUNCTION TABLE FOR TFBGA-121 PACKAGE (CONTINUED)
D5 AVDD12 Supply Supply voltage input (1.2V) for analog section
D6
D7
D8 GND Common ground for analog and digital sections
D9
D10 AIN6+ Channel 6 differential analog input (+)
Analog Input
D11 AIN0- Channel 0 differential analog input (-)
E1 Q8/Q4- Digital Digital data output(3)
Output CMOS = Q8
DDR LVDS = Q4-
E2 Q9/Q4+ Digital data output(3)
CMOS = Q9
DDR LVDS = Q4+
E3 GND Supply Common ground for analog and digital sections
E4
E5 AVDD12 Supply voltage input (1.2V) for analog section
E6
E7
E8 GND Common ground for analog and digital sections
E9
E10 AIN5+ Channel 5 differential analog input (+)
Analog Input
E11 AIN1+ Channel 1 differential analog input (+)
F1 Q6/Q3- Digital Digital data output(3)
Output CMOS = Q6
DDR LVDS = Q3-
F2 Q7/Q3+ Digital data output(3)
CMOS = Q7
DDR LVDS = Q3+
F3 DVDD18 Supply Supply voltage input (1.8V) for digital section.
F4 All digital input pins are driven by the same DVDD18 potential.
F5 AVDD12 Supply voltage input (1.2V) for analog section
F6
F7
F8 GND Common ground for analog and digital sections
F9
F10 AIN5- Channel 5 differential analog input (-)
Analog Input
F11 AIN1- Channel 1 differential analog input (-)
G1 Q4/Q2- Digital Digital data output(3)
Output CMOS = Q4
DDR LVDS = Q2-
G2 Q5/Q2+ Digital data output(3)
CMOS = Q5
DDR LVDS = Q2+
G3 DVDD18 Supply Supply voltage input (1.8V) for digital section
G4 All digital input pins are driven by the same DVDD18 potential
G5 GND Common ground for analog and digital sections
G6

G7 AVDD12 Supply Supply voltage input (1.2V) for analog section
G8
G9 GND Common ground for analog and digital sections
G10 AIN7- Channel 7 differential analog input (-)
Analog Input
G11 AIN3+ Channel 3 differential analog input (+)
H1 Q2/Q1- Digital Digital data output(3)
Output CMOS = Q2
DDR LVDS = Q1-
H2 Q3/Q1+ Digital data output(3)
CMOS = Q3
DDR LVDS = Q1+
H3 DVDD12 Supply Supply voltage input (1.2V) for digital section
H4
H5 GND Common ground for analog and digital sections
H6
H7
H8
H9
H10 AIN7+ Channel 7 differential analog input (+)
Analog Input
H11 AIN3- Channel 3 differential analog input (-)
J1 Q0/Q0- Digital Digital data output(3)
Output CMOS = Q0
DDR LVDS = Q0-
J2 Q1/Q0+ Digital data output(3)
CMOS = Q1
DDR LVDS = Q0+
J3 DVDD12 Supply DC supply voltage input pin for digital section (1.2V)
J4
J5 GND Common ground for analog and digital sections
J6
J7
J8
J9
J10 VCMIN+ Analog Input Common-mode voltage input for auto-calibration(4)
These two pins should be tied together and connected to VCM voltage.
J11 VCMIN-
K1 TP Digital Output test pints. Leave these pins floating always(8)
K2 Output
K3
K4 DCLK- LVDS: Differential digital clock output (-)
CMOS: Not used (leave floating)
K5 CAL Digital Calibration status flag digital output(5)
Output High: Calibration is complete
Low: Calibration is not complete
K6 GND Supply Common ground pin for analog and digital sections
K7 SLAVE Digital Input Slave or Master selection pin in AutoSync (10). If not used, tie to GND.
K8 ADR0 SPI address selection pin (A0 bit). Tie to GND or DVDD18(6)
K9 ADR1 SPI address selection pin (A1 bit). Tie to GND or DVDD18(6)

K10 GND Supply Common ground for analog and digital sections
K11
L1 TP Digital Output test pints. Leave these pins floating always(8)
L2 Output
L3
L4 DCLK- LVDS: Differential digital clock output (+)
CMOS: Digital clock output(7)
L5 RESET Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(9)
L6 SYNC Digital Input/ Digital synchronization pin for AutoSync.(10)
Output If not used, leave it floating.
L7 GND Supply Common ground for analog and digital sections
L8 CLK+ Analog Input Differential clock input (+)
L9 CLK- Differential clock input (-)
L10 GND Supply Common ground for analog and digital sections
L11 AVDD18 Analog Input Supply voltage input (1.8V) for analog section
Notes:
1. When the VCM output is used for the Common-mode voltage of analog inputs (i.e. by connecting to the center-tap of
a balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+ and VCMIN-
pins.
2. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High” when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. See Section 4.12.4 “Word Clock (WCK)” for further
WCK description.
3. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10) appear when DCLK+ is “High”. The odd data bits (Q1, Q3, Q5, Q7,
Q9, Q11) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68 (Register 5-26) for output
polarity control. See Figure 2-2 for LVDS output timing diagram.
4. VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another Common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
5. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain the
prior condition.
6. If the SPI address is dynamically controlled, the Address pin must be held constant while CS is “Low”.
7. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. Also
see Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
8. Do not tie to ground or supply.
9. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
10. a) SLAVE = “High”: The device is selected as slave and the SYNC pin becomes input pin.
(b) SLAVE = “Low”: The device is selected as master and the SYNC pin becomes output pin. In SLAVE/SYNC
operation, master and slave devices are synchronized to the same clock.

NOTES:

2.0 ELECTRICAL SPECIFICATIONS
2.1 Absolute Maximum Ratings†

Analog and Digital Supply Voltage (AVDD12, DVDD12) ..................................................................................................... -0.3V to 1.32V
Analog and Digital Supply Voltage (AVDD18, DVDD18) ..................................................................................................... -0.3V to 1.98V
All Inputs and Outputs with respect to GND ...................................................................................................... -0.3V to AVDD18 + 0.3V
Differential Input Voltage ................................................................................................................................................ |AVDD18 - GND|
Current at Input Pins .................................................................................................................................................................... ±2 mA
Current at Output and Supply Pins ......................................................................................................................................... ±250 mA
Storage Temperature ................................................................................................................................................... -65°C to +150°C
Ambient Temperature with Power Applied (TA) ............................................................................................................ -55°C to +125°C
Maximum Junction Temperature (TJ) ..........................................................................................................................................+150°C
ESD Protection.............................................................. 2 kV HBM on all pins, CDM: 750V on corner pins and 250V on all other pins
Solder Reflow Profile .............................................................................................. See Microchip Application Note AN233 (DS00233)
Notice†: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2.2 Electrical Specifications

TABLE 2-1: ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD18 = DVDD18 = 1.8V,
AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12, Single-channel mode, Differential Analog Input (AIN) = Sine wave with
amplitude of -1 dBFS, fIN = 15 MHz, Clock Input = 80 MHz, fS = 80 Msps (ADC Core), PLL and decimation filters are disabled, Output
load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical value.
Parameters Sym. Min. Typ. Max. Units Conditions
Power Supply Requirements
Analog Supply Voltage AVDD18 1.71 1.8 1.89 V
AVDD12 1.14 1.2 1.26 V
Digital Supply Voltage DVDD18 1.71 1.8 1.89 V Note 1
DVDD12 1.14 1.2 1.26 V
Analog Supply Current During Conversion
at AVDD18 pin IDD_A18 — 12.5 20 mA
at AVDD12 pin IDD_A12 — 132 170 mA TA = -40°C to +85°C
— 132 173 TA = +85°C to +125°C
Digital Supply Current
Digital Supply Current IDD_D12 — 58 105 mA TA = -40°C to +85°C
During Conversion — 58 149 TA = -40°C to +125°C
at DVDD12 Pin
Digital I/O Current in IDD_D18 — 8 14 mA at DVDD18 pin
CMOS Output Mode DCLK = 80 MHz
Digital I/O Current in IDD_D18 Measured at DVDD18 Pin
LVDS Mode — 41 — LVDS_IMODE<2:0> = 3.5 mA
— 29 — mA LVDS_IMODE<2:0> = 1.8 mA
— 53 — LVDS_IMODE<2:0> = 5.4 mA
Supply Current during Power-Saving Modes
Standby Mode ISTANDBY_AN — 43 — mA Address 0x00<4:3> = 1,1(2)
ISTANDBY_DIG — 23 —
Shutdown Mode IDD_SHDN — 23 — mA Address 0x00<7,0> = 1,1(3)

TABLE 2-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
PLL Circuit
PLL Circuit Current IDD_PLL — 17 — mA PLL enabled. Included in
analog supply current
specification.
Total Power Dissipation(4)
Power Dissipation PDISS_ADC — 229 — mW
During Conversion,
Excluding Digital I/O
Total Power Dissipation PDISS_CMOS — 248 — mW fS = 80 Msps,
During Conversion with DCLK = 80 MHz
CMOS Output Mode
Total Power Dissipation PDISS_LVDS — 311 — mW LVDS_IMODE<2:0> = 3.5 mA
During Conversion with — 289 — LVDS_IMODE<2:0> = 1.8 mA
LVDS Output Mode
— 332 — LVDS_IMODE<2:0> = 5.4 mA
During Standby Mode PDISS_STANDBY — 79 — mW Address 0x00<4:3> = 1,1(2)
During Shutdown Mode PDISS_SHDN — 22 — mW Address 0x00<7,0> = 1,1(3)
Power-on Reset (POR) Voltage
Threshold Voltage VPOR — 800 — mV Applicable to AVDD12 only
Hysteresis VPOR_HYST — 40 — mV (POR tracks AVDD12)
Power-on Reset TPOR-S — 218 — Clocks 218 sample clocks after
Stabilization Time Power-on Reset
SENSE Input(5,7)
SENSE Input Voltage VSENSE GND — AVDD12 V VSENSE selects reference
SENSE Pin Input RIN_SENSE — 500 —  To virtual ground at 0.55V.
Resistance 400 mV < VSENSE < 800 mV
Current Sink into SENSE ISENSE — 4.5 — µA SENSE = 1.2V
Pin — 636 — SENSE = 0.8V
— -2 — SENSE = 0V
Reference and Common-Mode Voltages
Internal Reference Voltage VREF — 0.74 — V VSENSE = GND
(Selected by VSENSE) — 1.49 — VSENSE = AVDD12
— 1.86 x VSENSE — 400 mV < VSENSE < 800 mV
Common-Mode VCM — 0.9 — V Available at VCM pin
Voltage Output
Reference Voltage VREF1 — 0.4 — V VSENSE = GND
Output(7,8) — 0.8 — VSENSE = AVDD12
— 0.4 - 0.8 — 400 mV < VSENSE < 800 mV
VREF0 — 0.7 — V VSENSE = GND
— 1.4 — VSENSE = AVDD12
— 0.7 - 1.4 — 400 mV < VSENSE < 800 mV
Bandgap Voltage Output VBG — 0.55 — V Available at VBG pin

Analog Inputs
Full-Scale Differential AFS — 1.4875 — VP-P VSENSE = GND
Analog Input Range(5,7) — 2.975 — VSENSE = AVDD12
— 3.71875 x — 400 mV < VSENSE < 800 mV
VSENSE
Analog Input Bandwidth fIN_3dB — 500 — MHz AIN = -3 dBFS
Differential Input CIN 5 6 7 pF Note 5, Note 9
Capacitance
Analog Input Leakage ILI_AH — — +1 µA VIH = AVDD12
Current (AIN+, AIN- Pins)
ILI_AL -1 — — µA VIL = GND
ADC Conversion Rate(10)
Conversion Rate fS — — 80 Msps Optimized at 80 Msps
See Figure 3-30 and Figure 3-33
Clock Inputs (CLK+, CLK-)(11)
Clock Input Frequency fCLK — 80 250 MHz Note 5
Differential Input Voltage VCLK_IN 300 — 800 mVP-P Note 5
Clock Jitter CLKJITTER — 175 — fSRMS Note 5
Clock Input Duty Cycle(5) 49 50 51 % Duty cycle correction
disabled
30 50 70 % Duty cycle correction
enabled
Input Leakage Current at ILI_CLKH — — +180 µA VIH = AVDD12
CLK Input Pin
ILI_CLKL VIL = GND
-20 — — µA TA = -40°C to +85°C
-30 TA = -40°C to +125°C
Converter Accuracy(6)
ADC Resolution — — 12 bits
(with no missing code)
Offset Error — ±0.31 — LSb
Gain Error GER — ±0.5 — % of
FS
Integral Nonlinearity INL — ±0.125 — LSb
Differential Nonlinearity DNL — ±0.03 — LSb
Analog Input CMRRDC — 70 — dB DC measurement
Common-Mode
Rejection Ratio

(6,14)
Dynamic Accuracy
Spurious Free Dynamic SFDR 78 92.2 — dBc fIN = 15 MHz
Range 94.1 — dBc fIN = 4.3 MHz
Signal-to-Noise Ratio SNR 69.5 70.9 — dBFS fIN = 15 MHz
— 71.4 — dBFS fIN = 4.3 MHz
Effective Number of Bits ENOB — 11.5 — bits fIN = 15 MHz
(ENOB)(12) — 11.6 — bits fIN = 4.3 MHz
Total Harmonic Distortion THD -79 -89.1 — dBc fIN = 15 MHz
(for all resolutions, first 13 -79 -92.4 — dBc fIN = 4.3MHz
harmonics)
Worst Second or HD2 or HD3 — -93.5 — dBc fIN = 15 MHz
Third Harmonic Distortion — -92.4 — dBc fIN = 4.3 MHz
SNR improvement when NSR is enabled: See Section 4.8.2, Noise-Shaping Requantizer (NSR) for details and
Figure 3-13 to Figure 3-18 as examples.
— 76.9 — dBFS NSR Filter # = 47
Signal-to-Noise Ratio SNR fIN = 14.7 MHz@-1 dBFS
— 77 — dBFS NSR Filter # = 52
fIN = 14.7 MHz@-1 dBFS
— 77.2 — dBFS NSR Filter # = 63
fIN = 4 MHz@-1 dBFS
Digital Logic Input and Output (Except LVDS Output)
Schmitt Trigger High-Level VIH 0.7 — DVDD18 V
Input Voltage DVDD18
Schmitt Trigger Low-Level VIL GND — 0.3 V
Input Voltage DVDD18
Hysteresis of Schmitt VHYST — 0.05 DVDD18 — V
Trigger Inputs
(All Digital Inputs)
Low-Level Output Voltage VOL — — 0.3 V IOL = -3 mA, all digital I/O pins
High-Level Output Voltage VOH DVDD18 – 1.8 — V IOL = +3 mA, all digital I/O pins
0.5
Digital Data Output (CMOS Mode)
Maximum External Load CLOAD — 10 — pF From output pin to GND
Capacitance
Internal I/O Capacitance CINT — 4 — pF Note 5
Digital Data Output (LVDS Mode)(5)
LVDS High-Level VH_LVDS 200 300 400 mV LVDS_IMODE<2:0> = 3.5 mA
Differential Output Voltage
LVDS Low-Level VL_LVDS -400 -300 -200 mV LVDS_IMODE<2:0> = 3.5 mA
Differential Output Voltage
LVDS Common-Mode VCM_LVDS 1 1.15 1.4 V
Voltage
Output Capacitance CINT_LVDS — 4 — pF Internal capacitance from
output pin to GND

Differential Load RLVDS — 100 —  Across LVDS output pairs
Resistance (LVDS)
Input Leakage Current on Digital I/O Pins
Data Output Pins ILI_DH — — +1 µA VIH = DVDD18
ILI_DL VIL = GND
-1 — — µA TA = -40°C to +85°C
-1.2 — — TA = -40°C to +125°C
I/O Pins except Data ILI_DH — — +6 µA VIH = DVDD18
Output Pins
ILI_DL -35 — — µA VIL = GND(13)
Notes:
1. This 1.8V digital supply voltage is used for the digital I/O circuit, including SPI, CMOS and LVDS data output drivers.
2. Standby Mode: Most of the internal circuits are turned off, except the internal reference, clock, bias circuits and
SPI interface.
3. Shutdown Mode: All circuits including reference and clock are turned off except the SPI interface.
4. Power dissipation (typical) is calculated by using the following equation:
(a) During operation:
PDISS = VDD18 x (IDD_A18 + IDD_D18) + VDD12 x (IDD_A12 + IDD_D12), where IDD_D18 is the digital I/O current for
LVDS or CMOS output. VDD18 = 1.8V and VDD12 = 1.2V are used for typical value calculation.
(b) During Standby mode:
PDISS_STANDBY = (ISTANDBY_AN + ISTANDBY_DIG) x 1.2V
(c) During Shutdown mode:
PDISS_SHDN = IDD_SHDN x 1.2V
5. This parameter is ensured by design, but not 100% tested in production.
6. This parameter is ensured by characterization, but not 100% tested in production.
7. See Table 4-2 for details.
8. Differential reference voltage output at REF1+/- and REF0+/- pins. VREF1 = VREF1+ – VREF1-.
VREF0 = VREF0+ – VREF0-. These references should not be driven.
9. Input capacitance refers to the effective capacitance between one differential input pin pair.
10. The ADC core conversion rate. In multi-channel mode, the conversion rate of an individual channel is fS/N, where
N is the number of input channels used.
11. See Figure 4-8 for the details of the clock input circuit.
12. ENOB = (SINAD - 1.76)/6.02.
13. This leakage current is due to the internal pull-up resistor.
14. Dynamic performance is characterized with CH(n)_DIG_GAIN<7:0> = 0011-1000.

TABLE 2-2: TIMING REQUIREMENTS - LVDS AND CMOS OUTPUTS

amplitude of -1 dBFS, fIN = 15 MHz, Clock Input = 80 MHz, fS = 80 Msps (ADC Core), PLL and decimation filters are disabled,
Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical
value.

Aperture Delay tA — 1 — ns Note 1
Out-of-Range Recovery Time tOVR — 1 — Clocks Note 1
Output Clock Duty Cycle — 50 — % Note 1
Pipeline Latency TLATENCY — 28 — Clocks Note 2, Note 4
(1)
System Calibration
Power-Up Calibration Time TPCAL — 227 — Clocks First 227 sample clocks after
TPOR-S
Background Calibration Update TBCAL — 230 — Clocks Per 230 sample clocks after
Rate TPCAL
RESET Low Time TRESET 5 — — ns See Figure 2-6 for details(1)
(1,6)
AutoSync
Sync Output Time Delay TSYNC_OUT — 1 — Clocks
Maximum Recommended ADC — 80 — MHz
Clock Rate for AutoSync
LVDS Data Output Mode (1,5)
Input Clock to tCPD — 5.7 — ns
Output Clock Propagation Delay
Output Clock to tDC — 0.5 — ns
Data Propagation Delay
Input Clock to tPD — 5.8 — ns
Output Data Propagation Delay
CMOS Data Output Mode
Input Clock to tCPD — 3.8 — ns
Output Clock Propagation Delay
Output Clock to tDC — 0.7 — ns
Data Propagation Delay
Input Clock to tPD — 4.5 — ns
Output Data Propagation Delay
Note 1: This parameter is ensured by design, but not 100% tested in production.
2: This parameter is ensured by characterization, but not 100% tested in production.
3: tRISE = approximately less than 10% of duty cycle.
4: Output latency is measured without using fractional delay recovery (FDR), decimation filter or digital
down-converter options.
5: The time delay can be adjusted with the DCLK_PHDLY_DLL<2:0> setting.
6: Characterized with a single slave device. The maximum ADC sample rate for AutoSync mode may be
reduced if multiple slave devices are used. See Figure 2-7 - Figure 2-9, and Figure 4-28 for details.

S-1
Input Signal:
S+1 S+L
S S+L-1
*S = Sample Point
tA
Latency = L Cycles
Input Clock:
CLK-
CLK+
tCPD
Digital Clock Output:
DCLK
tDC
tPD
Output Data:
Q<N:0> S-L-1 S-L S-L+1 S-1 S
Over-Range Output:
OVR S-L-1 S-L S-L+1 S-1 S
FIGURE 2-1: Timing Diagram - CMOS Output.
S-1
Input Signal:
S+1
S+L
S S+L-1
*S = Sample Point
tA
Latency = L Cycles
Input Clock:
CLK-
CLK+
Digital Clock Output: tCPD
DCLK-
DCLK+
tDC
tPD
Output Data:
Q-[N:0]
EVEN ODD EVEN ODD EVEN EVEN ODD EVEN
S-L-1 S-L-1 S-L S-L S-L+1 S-1 S-1 S
Q+[N:0]
Word-CLK/
Over-Range Output:
WCK/OVR-
WCK OVR WCK OVR WCK WCK OVR WCK
S-L-1 S-L-1 S-L S-L S-L+1 S-1 S-1 S
WCK/OVR+
FIGURE 2-2: Timing Diagram - LVDS Output with Even Bit First Option.

TABLE 2-3: SPI SERIAL INTERFACE TIMING SPECIFICATIONS
amplitude of -1 dBFS, FIN = 15 MHz, Clock Input = 80 MHz, fS = 80 Msps (ADC Core), PLL and decimation filters are disabled,
Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical
value. All timings are measured at 50%.
Serial Clock frequency, fSCK = 50 MHz
CS Setup Time tCSS 10 — — ns
CS Hold Time tCSH 20 — — ns
CS Disable Time tCSD 20 — — ns
Data Setup Time tSU 2 — — ns
Data Hold Time tHD 4 — — ns
Serial Clock High Time tHI 8 — — ns
Serial Clock Low Time tLO 8 — — ns Note 1
Output Valid from SCK Low tDO — — 20 ns
Output Disable Time tDIS — — 10 ns Note 1
Note 1: This parameter is ensured by design, but not 100% tested.
tCSD
CS
tCSS tSCK
tHI tLO tCSH
SCLK
tSU tHD
SDIO
(SDI) MSb in LSb in
FIGURE 2-3: SPI Serial Input Timing Diagram.
CS
tSCK tCSH
tHI tLO
SCLK
tDO tDIS
SDIO MSb out LSb out

(SDO)
FIGURE 2-4: SPI Serial Output Timing Diagram.

Power-on Reset (VPOR)

1.2V
0.8V
AVDD12
TPOR-S
TPCAL
(218 clock cycles)
(227 clock cycles)
POR Stabilization Period: Power-Up calibration complete:

• AVDD18, DVDD18, and DVDD12 must • Registers are initialized.
be applied and stabilized before or • Device is ready for correct conver-
within this period.
FIGURE 2-5: Internal Power-Up Sequence Events.
RESET Pin
tRESET
Power-Up Calibration Time
(TPCAL)
Stop ADC conversion Start register initialization Recalibration complete:

and ADC recalibration • CAL Pin: High
• ADC_CAL_STAT = 1
FIGURE 2-6: RESET Pin Timing Diagram.
A. Master Device (SLAVE Pin = 0)

POR (Power-On Reset)
(~ 220 clock cycles)
Toggle to High at the 2nd rising edge of Clock Input
TSYNC_OUT
SYNC Output
CAL Pin (Output) TPCAL
Data Output Invalid Data Valid Data
Clock Input 1 2
B. Slave Device(s) (SLAVE Pin = 1)

SYNC Input
1 2
Clock Input
FIGURE 2-7: Figure 2-5Sync Timing Diagram with Power-On Reset.

RESET Pin
TSYNC_OUT
SYNC Output
1 2
Clock Input
SYNC Input
Clock Input
FIGURE 2-8: Sync Timing Diagram with RESET Pin Operation.

POR
(~ 220 clock cycles) Toggle to High at the 2nd rising edge of Clock Input after POR
Toggle to High at the 2nd rising edge of Clock Input
after SOFT_RESET = 1
SYNC Output TSYNC_OUT
SPI SOFT RESET Control

SOFT_RESET = 0 SOFT_RESET = 1
TPCAL
Invalid Valid No Output

Data Data
1 2 1 2
Clock Input

SYNC Input
TPCAL
Invalid Valid No Output

Data Output Data Data
Invalid Data Valid Data
1 2 1 2
Clock Input
FIGURE 2-9: Sync Timing Diagram with SOFT_RESET Bit Setting.

TABLE 2-4: TEMPERATURE CHARACTERISTICS

amplitude of -1 dBFS, FIN = 15MHz, Clock Input = 80 MHz, fS = 80 Msps (ADC Core), PLL and decimation filters are disabled,
Output load: CMOS data pin = 10 pF, LVDS = 100 termination, LVDS driver current setting = 3.5 mA, +25°C is applied for typical
value.
(1)
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C
(2)
Thermal Package Resistances
Junction-to-Ambient Thermal Resistance JA — 40.2 — °C/W
Junction-to-Case Thermal Resistance JC — 8.4 — °C/W
Note 1: Maximum allowed power-dissipation (PDMAX) = (TJMAX - TA)/JA.
2: This parameter value is achieved by package simulations.

NOTES:

3.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise specified, all plots are at +25°C, AVDD18 = DVDD18 = 1.8V, AVDD12 = DVDD12 = 1.2V, GND = 0V, SENSE = AVDD12,
Single-channel mode, Differential Analog Input (AIN) = Sine wave with amplitude of -1 dBFS, fIN = 14.7 MHz, Clock Input = 80 MHz,
fS = 80 Msps (ADC Core), PLL and decimation filters are disabled. When NSR option is used, 12-bit mode is applied and the noise is
calculated within the NSR bandwidth (25% of sampling frequency).
0
Mode = Single-Channel
-20 fCLK = 80 MHz
Amplitude (dBFS)
fS = 80 Msps
-40 fIN = 4.3 MHz @ -4.0 dBFS
SNR = 67.4 dB (71.4 dBFS)
SFDR = 94.2 dBc
-60 THD = -91.2 dBc
Resolution = 12-bit
-80
2 3 5 6 7
-100 8
9
4
-120
0 10 20 30 40
Frequency (MHz)
FIGURE 3-1: FFT for 4.3 MHz Input FIGURE 3-4: FFT for 4.3 MHz Input
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS. Signal: fS = 80 Msps, Single Ch., AIN = -4 dBFS.
0 0
New Data New Data

Mode = Dual-Channel Mode = Dual-Channel
-20 fCLK = 80 MHz -20 fCLK = 80 MHz
Amplitude (dBFS)
Amplitude (dBFS)
fS = 40 Msps fS = 40 Msps
-40 fIN = 4.3 MHz @ 1.0 dBFS -40 fIN = 4.3 MHz @ -4.0 dBFS
SNR = 70.4 dB (71.4 dBFS) SNR = 67.5 dB (71.5 dBFS)
SFDR = 91.2 dBc SFDR = 94.1 dBc
-60 THD = -89.4 dBc
-60 THD = -91.8 dBc
Resolution = 12-bit Resolution = 12-bit
-80 -80
3
2 6 2 3
-100 9 8 7 4
5
-100 9
6 4 5
8
7
-120 -120
0 5 10 15 20 0 5 10 15 20
Frequency (MHz) Frequency (MHz)
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS. Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.
New Data New Data
Signal: fS = 20 Msps, Quad-Ch., AIN = -1 dBFS. Signal: fS = 20 Msps, Quad-Ch., AIN = -4 dBFS.

0 0
Mode = Octal-Channel Mode = Octal-Channel
Amplitude (dBFS)
Amplitude (dBFS)
Take New Data

-40 fIN = 4.3 MHz @ -1.0 dBFS -40 fIN = 4.3 MHz @ -4.0 dBFS
-60
SNR = 70.5 dB (71.5 dBFS)
SFDR = 90.4 dBc
THD = -86.7 dBc
Resolution = 12-bit
-60 Take New Data
SNR = 67.7 dB (71.7 dBFS)
SFDR = 94.8 dBc
THD = -90.6 dBc
Resolution = 12-bit
-80 -80
3 6
8
7 52 4 2 34 6
-100 9 -100 8
7
59
-120 -120
0 1 2 3 4 5 0 1 2 3 4 5
Signal: fS = 10 Msps, Octal-Ch., AIN = -1 dBFS. Signal: fS = 10 Msps, Octal-Ch., AIN = -4 dBFS.
0 0
Mode = Single-Channel Mode = Single-Channel
Amplitude (dBFS)
Amplitude (dBFS)
-40 fIN = 14.7 MHz @ -1.0 dBFS -40 fIN = 14.7 MHz @ -4.0 dBFS
SNR = 69.9 dB (70.9 dBFS) SNR = 67.1 dB (71.1 dBFS)
Take New Data

-60 -60
New Data
THD = -89.1 dBc THD = -91.9 dBc
Resolution = 12-bit Resolution = 12-bit
-80 -80
2 3
2 3
-100 5 9
6 4
7
8
-100 4
5 9 8
7
6
-120 -120
0 10 20 30 40 0 10 20 30 40
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS. Signal: fS = 80 Msps, Single-Ch., AIN = -4 dBFS.
0
Mode = Dual-Channel
-20 fCLK = 80 MHz
Amplitude (dBFS)
fS = 40 Msps
-40 fIN = 14.7 MHz @ -1.0 dBFS
New Data
SNR = 69.9 dB (70.9 dBFS)
New Data
SFDR = 93.8 dBc
-60 THD = -90.7 dBc
Resolution = 12-bit
-80
3 2
-100 8 5 6 7
9 4
-120
0 5 10 15 20
Frequency (MHz)
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS. Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.

Note: From Figure 3-13 through Figure 3-18, SNR is calculated within its NSR BW.
0 0
fCLK = 80 MHz fCLK = 80 MHz
-20 fS = 80 Msps -20
Data will be collected with new circuit
fS = 80 Msps
Amplitude (dBFS)
Amplitude (dBFS)
fIN = 14.7 MHz @ -1 dBFS fIN = 14.7 MHz @ -4 dBFS
-40 SNR = 75.9 dB (76.9 dBFS) -40 SNR = 73.5 dB (77.5 dBFS)
-60 Data will be collected with new circuit
THD = -102.1 dBc
-60 THD = -100.2 dBc
3
3
-80 -80 2
2
-100 5 -100 7
6 4 7 5 4
-120 -120
0 10 20 30 40 0 10 20 30 40
FIGURE 3-13: FFT for 14.7 MHz Input @-1 FIGURE 3-16: FFT for 14.7 MHz Input @-4
dBFS with NSR enabled: NSR Filter # = 47, dBFS with NSR enabled: NSR Filter # = 47,
fCenter = 15 MHz, NSR BW (25% of fS) = 20 MHz. fCenter = 15 MHz, NSR BW (25% of fS) = 20 MHz.
0 0
Data will be collected with

f =new circuit
80 MHz
CLK
fCLK = 80 MHz
-20 -20
Amplitude (dBFS)
Amplitude (dBFS)

-40 -40 SNR = 73.7 dB (77.7 dBFS)
SNR = 76 dB (77 dBFS)
THD = -94 dBc -60 THD = -97.1 dBc
-60
-80 3 -80 3
2
5 6 2
-100 7 -100
5 7
4
6 4
-120 -120
0 10 20 30 40 0 10 20 30 40
FIGURE 3-14: FFT for 14.7 MHz Input @-1 FIGURE 3-17: FFFT for 14.7 MHz Input @-
dBFS with NSR enabled: NSR Filter # = 52, 4 dBFS with NSR enabled: NSR Filter # = 52,
fCenter = 20 MHz, NSR BW (25% of fS) = 20 MHz. fCenter = 20 MHz, NSR BW (25% of fS) = 20 MHz.
0 0
fCLK = 80 MHz fCLK = 80 MHz
-20 Data will be collected with new circuit
fS = 80 Msps -20
fS = 80 Msps
Amplitude (dBFS)
Amplitude (dBFS)
fIN = 4 MHz @ -1 dBFS fIN = 4 MHz @ -4 dBFS

-40 SNR = 76.2 dB (77.2 dBFS) -40 SNR = 73.3 dB (77.3 dBFS)
THD = -90 dBc THD = -93.4 dBc
-60 -60
-80 -80
2
3 7
2
-100 -100 3
7
5 4 5
6 6
-120 -120
0 10 20 30 40 0 10 20 30 40
FIGURE 3-15: FFT for 4 MHz Input @-1 FIGURE 3-18: FFT for 4 MHz Input @-4
dBFS with NSR enabled: NSR Filter # = 63, dBFS with NSR enabled: NSR Filter # = 63,
fCenter = 12 MHz, NSR BW (29% of fS) = 23.2 fCenter = 12 MHz, NSR BW (29% of fS) = 23.2
MHz. MHz.

SNR (dBc, dBFS), SFDR (dBc, dBFS)

120 120
110 SFDR (dBFS) 110 SFDR (dBFS)
100 100
90 SFDR (dBc) 90 SFDR (dBc)
80 SNR (dBFS) 80 SNR (dBFS)
70 70
60 60
50 SNR (dBc) 50 SNR (dBc)
40 40
30 30 SENSE = 1.2V
SENSE = 1.2V fIN = 4.3 MHz
20 20
fIN = 14.7 MHz
10 -50 -40 -30 -20 -10 0
-50 -40 -30 -20 -10 0
Input Amplitude (dBFS) Input Amplitude (dBFS)
FIGURE 3-19: SNR/SFDR vs. Analog Input FIGURE 3-22: SNR/SFDR vs. Analog Input
Amplitude: fS = 80 Msps, fIN = 14.7 MHz, Amplitude: fS = 80 Msps, fIN = 4.3 MHz,
High-Reference Mode (SENSE = AVDD12). High-Reference Mode (SENSE = AVDD12).

120 120
110 SFDR (dBFS) 110
SFDR (dBFS)
100 100
90 90
80 SFDR (dBc) 80 SNR (dBFS) SFDR (dBc)
SNR (dBFS)
70 70
60 60
SNR (dBc)
50 50 SNR (dBc)
40 40
30 SENSE = 0V 30 SENSE = 0V
20 f = 14.7 MHz fIN = 4.3 MHz
IN 20
10 10
-50 -40 -30 -20 -10 0 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS) Input Amplitude (dBFS)
FIGURE 3-20: SNR/SFDR vs. Analog Input FIGURE 3-23: SNR/SFDR vs. Analog Input
Amplitude: fS = 80 Msps, fIN = 14.7 MHz, Amplitude: fS = 80 Msps, fIN = 4.3 MHz,
Low-Reference Mode (SENSE = GND). Low-Reference Mode (SENSE = GND).
SNR (dBc), SFDR( dBc), SFDR (dBFS)
80 120
79 SFDR (dBFS) 100
Waiting for Data

SNR (dBFS)
Waiting for Data

$PSOLWXGH G%
78 80
SNR (dBFS)

77 60
SFDR (dBc)
SNR (dBc)
76 40

NSR: Enabled
75 f = 4.3 MHz
IN 20
SENSE = AV
DD12
74 0
-100 -80 -60 -40 -20 0
)UHTXHQF\ 0+]
Input Amplitude (dBFS)
FIGURE 3-21: SNR/SFDR vs. Analog Input FIGURE 3-24: Input Bandwidth.
Amplitude: fS = 80 Msps, fIN = 4.3 MHz,
High-Reference Mode (SENSE = AVDD12) with
NSR enabled. AIN  0.8 dBFS for NSR.

76 110
73 110
SNR (dBFS)
Take New Data

74 SFDR (dBFS) 105 SNR (dBFS)
SFDR (dBFS)
72 100
72 100
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
70 95
SNR (dBFS)
68 90 Input
71
Freq. = 4 Mhz, 14.7 MHz, 20 MHz, ... 100 MHz
90
66 85
64 80 70 80
62 fIN = 15.3 MHz @ -1 dBFS 75 Sample Rate = 80 Msps
Input Amplitude = -1 dBFS
60 70 69 70
0 0.2 0.4 0.6 0.8 1 1.2 0 10 20 30 40 50 60 70
SENSE Pin Voltage (V) Input Frequency (MHz)
FIGURE 3-25: SNR/SFDR vs. SENSE Pin FIGURE 3-28: SNR/SFDR vs. Input
Voltage: fIN = 15.3 MHz. Frequency, fS = 80 Msps.
74 110 74 110
SNR (dBFS) SNR (dBFS)

SFDR (dBFS) 105 SFDR (dBFS) 105
72 72
100 100
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
70 95 SNR (dBFS) 70 95
90 90
68 68
85 85
66 80 66 80
20 40 60 80 100 20 30 40 50 60 70 80 90 100
Sample Rate (Msps) Sample Rate (Msps)
FIGURE 3-26: SNR/SFDR vs. Sample FIGURE 3-29: SNR/SFDR vs. Sample
Rate (Msps): fIN = 4.3 MHz, AIN = -1 dBFS. Rate: fIN = 15.3 MHz, AIN = -1 dBFS.
72.7 94.5 -90

SNR (dBFS) HD2 (dBFS)
SFDR (dBFS) HD3 (dBFS)
72.6 94 -92
72.5 93.5
-94
SFDR (dBFS)
HDN (dBFS)
SNR (dBFS)
72.4 93
-96
72.3 92.5
-98
72.2 92
-100
72.1 fIN = 14.7 MHz @ -1 dBFS 91.5
fIN = 14.7 MHz @ -1 dBFS
72 91 -102
1.08/1.62 1.14/1.71 1.2/1.8 1.26/1.89 1.32/1.98 1.08/1.62 1.14/1.71 1.2/1.8 1.26/1.89 1.32/1.98
Supply Voltage (V) Supply Voltage (V)
FIGURE 3-27: SNR/SFDR vs. Supply FIGURE 3-30: HD2/HD3 vs. Supply
Voltage: fS = 80 Msps, fIN = 14.7 MHz. Voltage: fS = 80 Msps, fIN = 14.7MHz.

Data Acquired
71.8 96 1.385
SFDR (dBFS) AVDD18 = 1.9V
71.4 94 AVDD18 = 1.8V
AVDD18 = 1.7V
1.38
SNR (dBFS)
SFDR (dBFS)
71 92
SNR (dBFS)
VREF0 (V)
70.6 90
1.375
70.2 88
fIN = 14.7 MHz @ -1 dBFS 1.37

69.8 86
69.4 84
-40 -25 -10 5 20 35 50 65 80 95 110 125 1.365
o -55 -35 -15 5 25 45 65 85 105 125
Temperature ( C) Temperature (°C)
FIGURE 3-31: SNR/SFDR vs. FIGURE 3-33: VREF0 vs. Temperature.

Temperature: fS = 80 Msps, fIN = 14.7 MHz,
VSENSE = AVDD12, AIN = -1 dBFS.
74 100 0.5 0.3

SNR (dBFS) Gain Error (%)
0.4 Offset (LSB)
SFDR (dBFS) 0.2
Offset Error (LSB)

72 90
Gain Error (%) 0.3
0.1
SFDR (dBFS)
0.2
SNR (dBFS)
0.1 0
70 80
0
-0.1
-0.1
68 70
-0.2
-0.2
fIN = 15.3 MHz @ -1 dBFS
-0.3 -0.3
66 60 -40 -25 -10 5 20 35 50 65 80 95 110 125
0 0.2 0.4 0.6 0.8 1 1.2
Temperature (°C)
External VCM (V)
FIGURE 3-32: SNR/SFDR vs. VCM Voltage FIGURE 3-34: Gain and Offset Error Drifts
(Externally Applied): fS = 80 Msps, vs. Temperature Using Internal Reference, with
fIN = 15.3 MHz. Respect to +25°C: fS = 80 Msps, AIN = -1 dBFS.

0.2 0.1
DNL Error (LSB)

0.1 0.05
INL Error (LSB)
0 0
-0.1 -0.05
-0.2 -0.1
0 1024 2048 3072 4096 0 1024 2048 3072 4096
Output Code Output Code
FIGURE 3-35: INL Error vs. Output Code: FIGURE 3-37: DNL Error vs. Output Code:
fS = 80 Msps, fIN = 4.3 MHz, AIN = -1 dBFS. fS = 80 Msps, fIN = 4.3 MHz, AIN = -1 dBFS.
160 300
AIN = -1 dBFS
IDD_A12
140 280
Power Consumption (mW)

120 260
Current (mA)
100 240
80 Total Power for ADC Core 220

(Except I/O)
60 IDD_D18 200
40 180
IDD_D12
IDD_A18
20 160
0 140
20 30 40 50 60 70 80 90 100
Sample Rate (Msps)
FIGURE 3-36: Shorted Input Histogram. FIGURE 3-38: Power Consumption vs.
Sample Rate (LVDS Mode).

NOTES:

4.0 THEORY OF OPERATION The output data can be coded in two’s complement or
offset binary format, and randomized using the user
The MCP37D11-80 is a high-precision, 12-bit, 80 Msps option. Data can be output using either the CMOS or
Analog-to-Digital Converter (ADC) with built-in features LVDS (Low-Voltage Differential Signaling) interface.
including Harmonic Distortion Correction (HDC), DAC
Noise Cancellation (DNC), Dynamic Element Matching 4.1 ADC Core Architecture
(DEM) and flash error calibration.
Figure 4-1 shows the simplified block diagram of the
In addition to the analog-to-digital data conversion, the ADC core. The first stage consists of a 17-level flash
device offers various built-in digital signal post- ADC, multi-level Digital-to-Analog Converter (DAC)
processing (DSPP) features, such as high-order FIR and a residue amplifier with a gain of 8. Stages 2 to 6
decimation filters, Digital Down-Conversion (DDC), consist of a 9-level (3-bit) flash ADC, multi-level DAC
Fractional Delay Recovery (FDR), continuous wave and a residue amplifier with a gain of 4. The last stage
(CW) beamforming, and digital gain and offset is a 9-level 3-bit flash ADC. Dither is added in each of
corrections per individual channel. These built-in the first three stages.The digital outputs from all seven
advanced digital signal post-processing sub-blocks, stages are combined in a digital error correction logic
which are individually controlled using Configuration block and digitally processed for the final output.
register bit settings, can be used for various special
The first three stages include patented digital
applications such as I/Q demodulation, digital down-
calibration features:
conversion, and ultrasound imaging.
• Harmonic Distortion Correction (HDC) algorithm
When the device is first powered-up, it performs an
that digitally measures and cancels ADC errors
internal power-up calibration by itself and runs with
arising from distortions introduced by the residue
default settings. From this point, the user can configure
amplifiers
the device registers using the SPI command.
• DAC Noise Cancellation (DNC) algorithm that
The input channel is selected by setting-up the user- corrects DAC’s nonlinearity errors
control configuration register bits. In single-channel
• Dynamic Element Matching (DEM) which
operation, one of the 8-analog inputs can be selected.
randomizes DAC errors, thereby converting
In multi-channel mode, the inputs are sequentially
harmonic distortion to white noise
multiplexed by the input MUX defined by the scan
order. The input channel selection and the sequential These digital correction algorithms are first applied
scan order for the selected input channel are during the Power-on Reset sequence and then operate
programmed using the configuration register bits. in the background during normal operation of the
pipelined ADC. These algorithms automatically track
The device samples the analog input on the rising edge
and correct any environmental changes in the ADC.
of the clock. The digital output code is available after
More details of the system correction algorithms are
28 clock cycles of data latency. Latency will increase if
shown in Section 4.13 “System Calibration”.
any of the digital signal post-processing (DSPP)
options are enabled.
REF0 Clock Generation

Reference Generator
REF1
REF0 REF1 REF1 REF1 REF1 REF1 REF1

AIN0+
AIN0-
Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline 3-bit Flash
Input Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Stage 7
MUX (3-bit) (2-bit) (2-bit) (2-bit) (2-bit) (2-bit) (3-bit)
AIN7+
AIN7 - HDC1, DNC1 HDC2, DNC2 HDC3, DNC3
Digital Error Correction
User-Programmable Options Programmable Digital Signal Post-Processing (DSPP)
12-Bit Digital Output
FIGURE 4-1: ADC Core Block Diagram.

4.2 Supply Voltage (DVDD, AVDD, GND) 4.3 Input Sample Rate
The device operates from two sets of supplies and a In single-channel mode, the device samples the input
common ground: at full speed. In multi-channel mode, the core ADC is
• Digital Supplies (DVDD) for the digital section: multiplexed between the selected channels. The
1.8V and 1.2V resulting effective sample rate per channel is shown in
Equation 4-1.
• Analog Supplies (AVDD) for the analog section:
1.8V and 1.2V For example, with 80 Msps operation, the input is
• Ground (GND): Common ground for both digital sampled at the full 80 Msps rate if a single channel is
and analog sections. used, or at 10 Msps per channel if all eight channels
are used.
The supply pins require an appropriate bypass
capacitor (ceramic) to attenuate the high-frequency
noise present in most application environments. The EQUATION 4-1: SAMPLE RATE PER
ground pins provide the current return path. These CHANNEL
ground pins must be connected to the ground plane of
Full ADC Sample Rate  fs 
the PCB through a low-impedance connection. A Sample Rate/Channel = ---------------------------------------------------------------------
Number of Channel Used
ferrite bead can be used to separate analog and digital
supply lines if a common power supply is used for both
analog and digital sections. 4.4 Analog Input Channel Selection
The voltage regulators for each supply need to have
The analog input is auto-multiplexed sequentially as
sufficient output current capabilities to support a stable
defined by the channel-order selection bit setting. The
ADC operation.
user can configure the input MUX using the following
4.2.1 POWER-UP SEQUENCE registers:
• SEL_NCH<2:0> in Address 0x01 (Register 5-2):
Figure 2-5 shows the internal power-up sequence
Select the total number of input channels to be
events of the device. The power-up sequence of the
used.
device is initiated by a Power-on reset (POR) circuit
which monitors the analog 1.2V supply voltage • Addresses 0x7D – 0x7F (Registers 5-38–5-40):
(AVDD12): Select auto-scan channel order.
(a) Once the AVDD12 reaches the Power-on Reset The user can select up to eight input channels. If all
threshold (~ 0.8V), there will be a Power-on Reset eight input channels are to be used, SEL_NCH<2:0> is
stabilization period (218 clock cycles) before triggering set to 000 and the input channel sampling order is set
the power-up calibration (TPCAL). using Addresses 0x7D – 0x7F (Registers 5-38–5-40).
(b) All other supply voltages (AVDD18, DVDD18, Regardless of how many channels are selected, all
DVDD12) must be stabilized before or within the POR eight channels must be programmed in Addresses
stabilization period (TPOR-S). The order that these 0x7D – 0x7F (Registers 5-38–5-40) without duplica-
supply voltages are applied and stabilized will not affect tion. Program the addresses of the selected channels
the power-up sequence. in sequential order, followed by the unused channels.
The order of the unused channels has no effect. The
device samples the first N-Channels listed in
Addresses 0x7D – 0x7F (Registers 5-38–5-40)
sequentially, where N is the total number of channels to
be used, defined by the SEL_NCH<2:0>. Table 4-1
shows examples of input channel selection using
Addresses 0x7D – 0x7F (Registers 5-38–5-40).

TABLE 4-1: EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
No. of Selected Channel
Address 0x7F Address 0x7E Address 0x7D
Channels(1) Channels Order(2)
b b b b b b
7 0 7 0 7 0
Channel Order Bit Settings
5th Ch. 4th Ch. 6th Ch. 3rd Ch. 7th Ch. 2nd Ch. 8th Ch. 1st Ch.
[0 1 2 3 4 5 6 7] [0 1 2 3 4 5 6 7] 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0
8 (Default)
[7 6 5 4 3 2 1 0] [7 6 5 4 3 2 1 0] 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1
[0 2 4 6 1 3 5 7] [0 2 4 6 1 3 5 7] 0 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0
[1 3 5 7 0 2 4 6] [1 3 5 7 0 2 4 6] 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 1
Unused 4th Ch. 5th Ch. 3rd Ch. 6th Ch. 2nd Ch. 7th Ch. 1st Ch.
7
[0 1 2 3 4 5 6] [0 1 2 3 4 5 6 7] 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0
[0 2 4 6 1 3 5] [0 2 4 6 1 3 5 7] 1 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0
Unused Unused 4th Ch. 3rd Ch. 5th Ch. 2nd Ch. 6th Ch. 1st Ch.
6
[0 1 2 3 4 5] [0 1 2 3 4 5 6 7] 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0
[0 2 4 6 1 3] [0 2 4 6 1 3 5 7] 1 1 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0
Unused Unused Unused 3rd Ch. 4th Ch. 2nd Ch. 5th Ch. 1st Ch.
5
[0 1 2 3 4] [0 1 2 3 4 5 6 7] 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 0
[0 2 4 6 1] [0 2 4 6 1 3 5 7] 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0
Unused Unused Unused Unused 3rd Ch. 2nd Ch. 4th Ch. 1st Ch.
[0 1 2 3] [0 1 2 3 4 5 6 7] 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0
4
[4 5 6 7] [4 5 6 7 0 1 2 3] 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0
[0 2 4 6] [0 2 4 6 1 3 5 7] 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0
[1 3 5 7] [1 3 5 7 0 2 4 6] 1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1
Unused Unused Unused Unused Unused 2nd Ch. 3rd Ch. 1st Ch.
3
[0 1 2] [0 1 2 3 4 5 6 7] 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0
[0 2 4] [0 2 4 6 1 3 5 7] 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0
Unused Unused Unused Unused Unused Unused 2nd Ch. 1st Ch.
[0 1] [0 1 2 3 4 5 6 7] 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 0
2
[2 3] [2 3 0 1 4 5 6 7] 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 0
[4 5] [4 5 0 1 2 3 6 7] 0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0
[6 7] [6 7 0 1 2 3 4 5] 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.

TABLE 4-1: EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
No. of Selected Channel
Address 0x7F Address 0x7E Address 0x7D
Channels(1) Channels Order(2)
b b b b b b
7 0 7 0 7 0
Unused Unused Unused Unused Unused Unused Unused 1st Ch.
[0] [0 1 2 3 4 5 6 7] 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0
[1] [1 0 2 3 4 5 6 7] 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1
[2] [2 0 1 3 4 5 6 7] 1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0
1
[3] [3 0 1 2 4 5 6 7] 1 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1
[4] [4 0 1 2 3 5 6 7] 0 1 1 0 1 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0
[5] [5 0 1 2 3 4 6 7] 0 1 1 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1
[6] [6 0 1 2 3 4 5 7] 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0
[7] [7 0 1 2 3 4 5 6] 0 1 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.

4.5 Analog Input Circuit 4.5.1 ANALOG INPUT DRIVING CIRCUIT
The MCP37D11-80 has differential analog inputs. 4.5.1.1 Differential Input Configuration
Figure 4-2 shows the equivalent input structure of the The device achieves optimum performance when the
device. input is driven differentially, where Common-mode
The input impedance of the device is mostly governed noise immunity and even-order harmonic rejection are
by the input sampling capacitor (CS = 6 pF) and input significantly improved. If the input is single-ended, it
sampling frequency (fS). The performance of the must be converted to a differential signal in order to
device can be affected by the input signal conditioning properly drive the ADC input. The differential
network (see Figure 4-3). The analog input signal conversion and Common-mode application can be
source must have sufficiently low output impedance to accomplished by using an RF transformer or balun with
charge the sampling capacitors (CS = 6 pF) within one a center-tap. Additionally, one or more anti-aliasing
clock cycle. A small external resistor (e.g., 5Ω) in series filters may be added for optimal noise performance and
with each input is recommended, as it helps reduce should be tuned such that the corner frequency is
transient currents and dampens ringing behavior. A appropriate for the system.
small differential shunt capacitor at the chip side of the Figure 4-3 shows an example of the differential input
resistors may be used to provide dynamic charging circuit with transformer. Note that the input-driving
currents and may improve performance. The resistors circuits are terminated by 50 near the ADC side
form a low-pass filter with the capacitor and their values through a pair of 25 resistors from each input to the
must be determined by application requirements and Common-mode (VCM) from the device. The RF
input frequency. transformer must be carefully selected to avoid
artificially high harmonic distortion. The transformer
The VCM pin provides a Common-mode voltage
can be damaged if a strong RF input is applied or an RF
reference (0.9V), which can be used for a center-tap
input is applied while the MCP37D11-80 is powered-
voltage of an RF transformer or balun. If the VCM pin
off. The transformer has to be selected to handle
voltage is not used, the user may create a Common-
sufficient RF input power.
mode voltage at mid-supply level (AVDD18/2).
Figure 4-4 shows an input configuration example when
a differential output amplifier is used.
MCP37D11-80 1 VCM
AVDD18
0.1 µF
Sample Hold AIN+

AIN+ 5
MCP37D11-80
Analog
CS = 6 pF Input MABAES0060 100 pF 25
50 10
3 4 6 1 0.1 µF
3 pF 6.8 pF
VCM 1 6 4 3 3.3 pF
AVDD18
MABAES0060 10
100 pF 25
5 AIN-
AIN- Sample Hold
FIGURE 4-3: Transformer Coupled Input
50 CS = 6 pF Configuration.
3 pF 50 VCM
0.1 µF
MCP37D11-80
High-Speed 100 AIN+

FIGURE 4-2: Equivalent Input Circuit. Differential
Amplifier
+
Analog 6.8 pF
CM
Input - 100 AIN-
MCP6D11
FIGURE 4-4: DC-Coupled Input

Configuration with Preamplifier: the external
signal conditioning circuit and associated
component values are for reference only.
Typically, the amplifier manufacturer provides
reference circuits and component values.

4.5.1.2 Single-Ended Input Configuration 4.5.2 SENSE VOLTAGE AND INPUT
Figure 4-5 shows an example of a single-ended input FULL-SCALE RANGE
configuration. This single-ended input configuration is The device has a bandgap-based differential internal
not recommended for the best performance. SNR and reference voltage. The SENSE pin voltage is used to
SFDR performance degrades significantly when the select the reference voltage source and configure the
device is operated in a single-ended configuration. The input full-scale range. A comparator detects the
unused negative side of the input should be SENSE pin voltage and configures the full-scale input
AC-coupled to ground using a capacitor. range into one of the three possible modes which are
summarized in Table 4-2. Figure 4-6 shows an
example of how the SENSE pin should be driven.
VCM
The SENSE pin can sink or source currents as high as
10 µF 0.1 µF 500 µA across all operational conditions. Therefore, it
Analog 1 k
may require a driver circuit, unless the SENSE
MCP37D11-80
Input R AIN+
reference source provides sufficient output current.
0.1 µF VCM
50
C MCP1700
1 k
0.1 µF R1
10 µF 0.1 µF R AIN-
MCP37D11-80
SENSE
R2
FIGURE 4-5: Singled-Ended Input
0.1 µF
Configuration. (Note 1)
Note 1: This voltage buffer can be removed if the SENSE

reference is coming from a stable source (such as
MCP1700) which can provide a sufficient output
current to the SENSE pin.
FIGURE 4-6: SENSE Pin Voltage Setup.
TABLE 4-2: SENSE PIN VOLTAGE AND INPUT FULL-SCALE RANGE

SENSE Pin Selected
Full-Scale Input Voltage LSb Size
Voltage Reference Voltage Condition
Range (AFS) (Calculated with AFS)
(VSENSE) (VREF)
Tied to GND 0.7V 1.4875 VP-P(1) 363.16 µV Low-Reference
Mode(4)
0.4V – 0.8V 0.7V – 1.4V 1.4875 VP-P to 2.975 VP-P(2) Adjustable Sense Mode(5)
Tied to AVDD12 1.4875V 2.975 VP-P(3) 726.32 µV High-Reference
Mode(4)
Note 1: AFS = (17/16) x 1.4 VP-P = 1.487 VP-P.
2: AFS = (17/16) x 2.8 VP-P x (VSENSE)/0.8 = 1.4875 VP-P to 2.975 VP-P.
3: AFS = (17/16) x 2.8 VP-P = 2.975 VP-P.
4: Based on internal bandgap voltage.
5: Based on VSENSE.

4.5.2.1 SENSE Selection Vs. SNR/SFDR • Low-Reference Mode
Performance This mode is enabled by setting the SENSE pin to
The SENSE pin is used to configure the full-scale input ground. This mode is suitable for applications which
range of the ADC. Depending on the application have a smaller input full-scale range. This mode
conditions, the SNR, SFDR and dynamic range provides improved SFDR characteristics, but SNR is
performance are affected by the SENSE pin reduced by -3 dB compared to the High-Reference
configuration. Table 4-3 summarizes these settings. Mode.
Figure 3-24 shows SNR/SFDR performance versus • SENSE Mode
SENSE Pin Voltage.
This mode is enabled by driving the SENSE pin with an
• High-Reference Mode external voltage source between 0.4V and 0.8V. This
This mode is enabled by setting the SENSE pin to mode allows the user to adjust the input full-scale
AVDD12 (1.2V). This mode provides the highest input range such that SNR and dynamic range are optimized
full-scale range (2.975 VP-P) and the highest SNR in a given application system environment.
performance. In this mode, the internal thermal noise is • NSR Mode
less than 1 LSb of the 12-bit ADC (726 µV). This has
The use of the Noise-Shaping Requantizer (NSR),
the consequence of making it difficult to resolve small
further described in Section 4.8.2 “Noise-Shaping
input signals unless some dither is added to the ADC
Requantizer (NSR)”, is best suited for applications
input. In typical applications, thermal noise generated
which require a high SNR and a wide dynamic range as
by the system driving the ADC will provide the
well as a relatively narrow bandwidth.
necessary dithering effect. Figure 3-19 and Figure 3-
22 show SNR/SFDR versus input amplitude in When the NSR is enabled, the noise level in a selected
High-Reference mode. portion of the frequency band is reduced to a level
below that of a conventional 12-bit ADC, while the
Note: Adding dither to the ADC has a negative noise level outside of this band remains significantly
side effect of reducing the maximum higher. The SNR achievable in this mode is about
achievable SNR. 78 dBFS when integrated across 50% of the Nyquist
bandwidth. This is an optimum selection for
applications where the full Nyquist bandwidth of the
ADC is not needed, and where the digital signal
post-processing of the ADC data is capable of
removing the out-of-band noise added by the NSR.
Figure 3-21 shows the SNR/SFDR versus input
amplitude with NSR enabled.
TABLE 4-3: SENSE VS. SNR/SFDR PERFORMANCE

SENSE Descriptions
High-Reference Mode High-input full-scale range (2.975 VP-P) and optimized SNR
(SENSE pin = AVDD12)
Low-Reference Mode Low-input full-scale range (1.4875 VP-P) and reduced SNR, but optimized SFDR
(SENSE pin = ground)
Sense Mode Adjustable-input full-scale range (1.4875 VP-P - 2.975 VP-P). Dynamic trade-off
(SENSE pin = 0.4V to 0.8V) between High-Reference and Low-Reference modes can be used.
Noise-Shaping Requantizer Optimized SNR, but reduced usable bandwidth.
(NSR) NSR can be employed in any SENSE pin configuration.

4.5.3 INTERNAL VOLTAGE REFERENCE 4.6 External Clock Input
AND BANDGAP OUTPUT
For optimum performance, the MCP37D11-80 requires
4.5.3.1 Internal Voltage Reference Output a low-jitter differential clock input at the CLK+ and
CLK− pins. Figure 4-8 shows the equivalent clock input
Pins (REF1 and REF0 Pins)
circuit.
The device has two internal voltage references, and
these references are available at pins REF0 and REF1.
REF0 is the internal voltage reference for the ADC
input stage, and REF1 is for all remaining stages. AVDD12 AVDD12
The decoupling capacitors for each reference pin are
already embedded in the device’s TFBGA-121 ~300 fF
package. Figure 4-7 shows the embedded circuit for CLK+
the REF1 and REF0 pins. Therefore, no additional
external circuit is required on the customer’s 300 100 fF
application PCB.
Clock
4.5.3.2 Bandgap Output Voltage Pin (VBG) AVDD12 12 k 2 pF Buffer
The bandgap circuit is a part of the reference circuit and
the output is available at the VBG pin. The package 300
CLK-
includes a 2.2 µF decoupling capacitor for the VBG pin
100 fF
as shown in Figure 4-7.
~300 fF
MCP37D11-80
MCP37D11-80 Silicon
REF1+ REF1- REF0+ REF0- VBG

FIGURE 4-8: Equivalent Clock Input
2.2 µF 2.2 µF
Circuit.
2.2 µF
22 nF 22 nF
The clock input amplitude range is between 300 mVP-P
220 nF 220nF
and 800 mVP-P. When a single-ended clock source is
220 nF
used, an RF transformer or balun can be used to
220 nF
convert the clock into a differential signal for the best
ADC performance. Figure 4-9 shows an example clock
TFBGA-121 Embedded External Circuit
input circuit. The Common-mode voltage is internally
generated and a center-tap is not required. The
FIGURE 4-7: Embedded Decoupling back-to-back Schottky diodes across the transformer’s
Circuit in TFBGA-121 Package for Voltage secondary current limit the clock amplitude to
Reference and VBG pins. No external circuit is approximately 0.8 VP-P differential. This limiter helps
required on an application PCB. prevent large voltage swings of the input clock while
preserving the high slew rate that is critical for low jitter.
CLK+
Clock Coilcraft
Source WBC1-1TL
MCP37D11-80
6 1
Schottky
50 Diodes
4 3 (HSMS-2812)
0.1 µF
CLK-
FIGURE 4-9: Transformer-Coupled

Differential Clock Input Configuration.

4.6.1 CLOCK JITTER AND SNR
PERFORMANCE
In a high-speed pipelined ADC, the SNR performance
is directly limited by thermal noise and clock jitter.
Thermal noise is independent of input clock and
dominant term at low-input frequency. On the other
hand, the clock jitter becomes a dominant term as input
frequency increases. Equation 4-2 shows the SNR
jitter component, which is expressed in terms of the
input frequency (fIN) and the total amount of clock jitter
(TJitter), where TJitter is a sum of the following two
components:
• Input clock jitter (phase noise)
• Internal aperture jitter (due to noise of the clock
input buffer).
EQUATION 4-2: SNR VS.CLOCK JITTER

SNR Jitter  dBc  = – 20  log 10  2   f IN  T Jitter 
where the total jitter term (Tjitter) is given by:
2 2
T Jitter =  t Jitter , Clock Input  +  t Aperture , ADC 
The clock jitter can be minimized by using a high-

quality clock source and jitter cleaners as well as a
band-pass filter at the external clock input, while a
faster clock slew rate improves the ADC aperture jitter.
With a fixed amount of clock jitter, the SNR degrades
as the input frequency increases. This is illustrated in
Figure 4-10. If the input frequency increases from
10 MHz to 20 MHz, the maximum achievable SNR
degrades about 6 dB. For every decade (e.g. 10 MHz
to 100 MHz), the maximum achievable SNR due to
clock jitter is reduced by 20 dB.
160
Jitter = 0.0625 ps
140 Jitter = 0.125 ps
120 Jitter = 0.25 ps
Jitter = 0.5 ps
SNR (dBc)
100
Jitter = 1 ps
80
60
40
20
0
1 10 100 1000
Input Frequency (fIN, MHz)
FIGURE 4-10: SNR vs. Clock Jitter.

4.7 ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Table 4-4 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-4: ADC CLOCK SELECTION (EXAMPLE)

Features
Operating Conditions Control Bit Settings(1) Input Clock Duty DCLK Output Phase
Cycle Correction Delay Control
CLK_SOURCE = 0 (Default)(2)
• DLL output is not used EN_DLL = 0 Not Available Not Available
• Decimation is not used EN_DLL_DCLK = 0
(Default)(3) EN_PHDLY = 0
EN_DLL = 1 Available
EN_DLL_DCLK = 0
EN_PHDLY = 0
• DLL output is used EN_DLL = 1 Available Available
• Decimation is not used EN_DLL_DCLK = 1
EN_PHDLY = 1
• DLL output is not used EN_DLL = 0 Not Available
• Decimation is used(4) EN_DLL_DCLK = X
EN_PHDLY = 1
EN_DLL = 1 Available
EN_DLL_DCLK = 0
EN_PHDLY = 1
CLK_SOURCE = 1(5)
• Decimation is not used EN_DLL = X Not Available Available
EN_DLL_DCLK = X
EN_PHDLY = 0
• Decimation is used(4) EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1: See Addresses 0x52, 0x53, and 0x64 for bit settings.
2: The sampling frequency (fS) of the ADC core comes directly from the input clock buffer
3: Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
4: While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
5: The sampling frequency (fS) is generated by the PLL circuit. The external clock input is used as the reference input
clock for the PLL block.

fS
EN_DLL RESET_DLL EN_DLL_DCLK = 0

Clock Input (fCLK): < 250 MHz
EN_DLL = 0
DLL Circuit EN_PHDLY
DCLK DCLK
if CLK_SOURCE = 0 Phase Delay
EN_CLK Input Clock Buffer Duty Cycle Correction (DCC)
EN_DUTY DCLK_PHDLY_DLL<2:0>
EN_DLL_DCLK
DLL Block
See Address 0x52 and 0x64<7> for details
if digital decimation is used
if CLK_SOURCE = 1
See Address 0x7A, 0x7B, 0x7C, and 0x81
Digital Output DCLK

EN_PHDLY Digital Output
Clock Phase Delay Control
DCLK_PHDLY_DEC<2:0> (when decimation filter is used) Clock Rate Control
OUT_CLKRATE<3:0>
fREF Digital Clock Output Control Block

See Address 0x64 and 0x02
(5 MHz to 250 MHz)
for control parameters
EN_PLL EN_PLL_BIAS
Loop Filter Control Parameters:

if digital decimation is used
C1: PLL_CAP1<4:0>
See Address 0x7A, 0x7B, 0x7C, and 0x81
C3 C2 C1 C2: PLL_CAP2<4:0>
R1 C3: PLL_CAP3<4:0>
PLL_REFDIV<9:0> R1: PLL_RES<4:0> fS
÷R (80 MHz - 250 MHz)
EN_PLL_REFDIV
fQ EN_PLL_OUT
Current fVCO DCLK

Phase/Freq. Loop Filter
Charge Output/Div DCLK Delay
Detector Pump (3rd Order)
VCO
EN_PLL_CLK
Loop Filter Control PLL_OUTDIV<3:0> DCLK_DLY_PLL<2:0>
PLL_CHAGPUMP<3:0>
÷N
PLL Output Control Block
See Address 0x55 and 0x6D
PLL_PRE<11:0>
for control parameters
PLL Block
See Address 0x54 - 0x5D for Control Parameters
Note: VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with fREF = 5 MHz - 250 MHz range.
N
f = ----  f =  1.075 – 1.325  GHz
VCO R REF
FIGURE 4-11: Timing Clock Control Blocks.

4.7.1 USING DLL MODE
Using the DLL block is the best option when output
clock phase control is needed while the clock
multiplication and digital decimation are not required.
When the DLL block is enabled, the user can control
the input clock Duty Cycle Correction (DCC) and the
output clock phase delay.
See the DLL block in Figure 4-11 for details. Table 4-5
summarizes the DLL control register bits. In addition,
see Table 4-24 for the output clock phase control.
TABLE 4-5: DLL CONTROL REGISTER BITS

Control Parameter Register Descriptions
CLK_SOURCE 0x53 CLK_SOURCE = 0: external clock input becomes input of the DLL block
EN_DUTY 0x52 Input clock duty cycle correction control bit(1)
EN_DLL 0x52 EN_DLL = 1: enable DLL block
EN_DLL_DCLK 0x52 DLL output clock enable bit
EN_PHDLY<2:0> 0x52 Phase delay control bits of digital output clock (DCLK) when DLL or
decimation filter is used(2)
RESET_DLL 0x52 Reset control bit for the DLL block
Note 1: Duty cycle correction is not recommended when a high-quality external clock is used.
2: If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in
Address 0x64.
4.7.1.1 Input Clock Duty Cycle Correction 4.7.1.2 DLL Block Reset Event
The ADC performance is sensitive to the clock duty The DLL must be reset if the clock frequency is
cycle. The ADC achieves optimum performance with changed. The DLL reset is controlled by using the
50% duty cycle, and all performance characteristics are RESET_DLL bit in Address 0x52 (Register 5-7). The
ensured when the duty cycle is 50% with ±1% DLL has an automatic reset with the following events:
tolerance. • During power-up: Stay in reset until the
When CLK_SOURCE = 0, the external clock is used RESET_DLL bit is cleared.
as the sampling frequency (fS) of the ADC core. When • When a SOFT_RESET command is issued while
the external input clock is not high-quality (for example, the DLL is enabled: the RESET_DLL bit is
duty cycle is not 50%), the user can enable the internal automatically cleared after reset.
clock duty cycle correction circuit by setting the
EN_DUTY bit in Address 0x52 (Register 5-7). When
duty cycle correction is enabled (EN_DUTY=1), only
the falling edge of the clock signal is modified (rising
edge is unaffected).
Because the duty cycle correction process adds
additional jitter noise to the clock signal, this option is
recommended only when an asymmetrical input clock
source causes significant performance degradation or
when the input clock source is not stable.
Note: The clock duty cycle correction is only

applicable when the DLL block is enabled
(EN_DLL = 1). It is not applicable for the PLL
output.

4.7.2 USING PLL MODE When the PLL is locked, it tracks the input frequency
The PLL block is mainly used when clock multiplication (fREF) with the ratio of dividers (N/R). The PLL operat-
is needed. When CLK_SOURCE = 1, the sampling ing status is monitored by the PLL status indication bits:
frequency (fS) of the ADC core is coming from the <PLL_VCOL_STAT> and <PLL_VCOH_STAT> in
internal PLL block. Address 0xD1 (Register 5-81).
The external clock input is used as the PLL reference Equation 4-3 shows the VCO output frequency (fVCO) as
frequency. The range of the clock input frequency is a function of the two dividers and reference frequency:
from 5 MHz to 250 MHz. EQUATION 4-3: VCO OUTPUT
FREQUENCY
4.7.2.1 PLL Output Frequency and Output N
f VCO =  ---- fREF = 1.075  GHz  to 1.325  GHz 
Control Parameters R
Where:
The internal PLL can provide a stable timing output
ranging from 50 MHz to 250 MHz. Figure 4-11 shows the N = 1 to 4095 controlled by PLL_PRE<11:0>
PLL block using a charge-pump-based integer N PLL R = 1 to 1023 controlled by PLL_REFDIV<9:0>
and the PLL output control block. The PLL block
includes various user control parameters for the desired See Addresses 0x54 to 0x57 (Registers 5-9 – 5-12) for
output frequency. Table 4-6 summarizes the PLL control these bits settings.
register bits and Table 4-7 shows an example of register The tuning range of the VCO is 1.075 GHz to
bit settings for the PLL charge pump and loop filter. 1.325 GHz. N and R values must be chosen so the
The PLL block consists of: VCO is within this range. In general, lower values of the
• Reference Frequency Divider (R) VCO frequency (fVCO) and higher values of the charge
pump frequency (fQ) should be chosen to optimize the
• Prescaler - which is a feedback divider (N)
clock jitter. Once the VCO output frequency is
• Phase/Frequency Detector (PFD)
determined to be within this range, set the final ADC
• Current Charge Pump sampling frequency (fS) with the PLL output divider
• Loop Filter - a 3rd order RC low-pass filter using PLL_OUTDIV<3:0>. Equation 4-4 shows how to
• Voltage-Controlled Oscillator (VCO) obtain the ADC core sampling frequency:
The external clock at the CLK+ and CLK- pins is the EQUATION 4-4: SAMPLING FREQUENCY
input frequency to the PLL. The range of input fVCO
frequency (fREF) is from 5 MHz to 250 MHz. This input f S =  -------------------------------------- = 50 MHz to 250 MHz
 PLL_OUTDIV
frequency is divided by the reference frequency
divider (R) which is controlled by the 10-bit-wide Table 4-8 shows an example of generating fS = 80 MHz
PLL_REFDIV<9:0> setting. In the feedback loop, the output using the PLL control parameters.
VCO frequency is divided by the prescaler (N) using
PLL_PRE<11:0>. 4.7.2.2 PLL Calibration
The ADC core sampling frequency (fS) is obtained The PLL should be recalibrated following a change in
after the output frequency divider clock input frequency or in the PLL Configuration
(PLL_OUTDIV<3:0>). For stable operation, the user register bit settings (Addresses 0x54 - 0x57;
needs to configure the PLL with the following limits: Registers 5-9 – 5-12).
• Input clock frequency (fREF) = 5 MHz to 250 MHz The PLL can be calibrated by toggling the PLL_-
• Charge pump input frequency = 4 MHz to 50 MHz CAL_TRIG bit in Address 0x6B (Register 5-27) or by
(after PLL reference divider) sending a SOFT_RESET command (See Address
0x00, Register 5-1). The PLL calibration status is
• VCO output frequency = 1.075 to1.325 GHz
observed by the PLL_CAL_STAT bit in Address 0xD1
• PLL output frequency after = 50 MHz to 250 MHz (Register 5-81).
output divider
The charge pump is controlled by the PFD, and forces
4.7.2.3 Monitoring of PLL Drifts
sink (DOWN) or source (UP) current pulses onto the The PLL drifts can be monitored using the status
loop filter. The charge pump bias current is controlled monitoring bits in Address 0xD1 (Register 5-81).
by the PLL_CHAGPUMP<3:0> bits, approximately Under normal operation, the PLL maintains a lock
25 µA per step. The loop filter consists of a 3rd order across all temperature ranges. It is not necessary to
passive RC filter. Table 4-7 shows the recommended actively monitor the PLL unless extreme variations in
settings of the charge pump and loop filter parameters, the supply voltage are expected or if the input
depending on the charge pump input frequency range reference clock frequency has been changed.
(output of the reference frequency divider).

TABLE 4-6: PLL CONTROL REGISTER BITS
PLL Global Control Bits
EN_PLL 0x59 Master enable bit for the PLL circuit
EN_PLL_OUT 0x5F Master enable bit for the PLL output
EN_PLL_BIAS 0x5F Master enable bit for the PLL bias
EN_PLL_REFDIV 0x59 Master enable bit for the PLL reference divider
PLL Block Setting Bits
PLL_REFDIV<9:0> 0x54-0x55 PLL reference divider (R) (See Table 4-8)
PLL_PRE<11:0> 0x56-0x57 PLL prescaler (N) (See Table 4-8)
PLL_CHAGPUMP<3:0> 0x58 PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step
PLL_RES<4:0> 0x5A PLL loop filter resistor value selection (See Table 4-7)
PLL_CAP3<4:0> 0x5B PLL loop filter capacitor 3 value selection (See Table 4-7)
PLL_CAP2<4:0> 0x5D PLL loop filter capacitor 2 value selection (See Table 4-7)
PLL_CAP1<4:0> 0x5C PLL loop filter capacitor 1 value selection (See Table 4-7)
PLL Output Control Bits
PLL_OUTDIV<3:0> 0x55 PLL output divider (See Table 4-8)
DCLK_DLY_PLL<2:0> 0x6D Delay DCLK output up to 15 cycles of VCO clocks
EN_PLL_CLK 0x6D EN_PLL_CLK = 1 enable PLL output clock to the ADC circuits
PLL Drift Monitoring Bits
PLL_VCOL_STAT 0xD1 PLL drift status monitoring bit
PLL_VCOH_STAT 0xD1 PLL drift status monitoring bit
PLL Block Calibration Bits
PLL_CAL_TRIG 0x6B Forcing recalibration of the PLL
SOFT_RESET 0x00 PLL is calibrated when exiting soft reset mode
PLL_CAL_STAT 0xD1 PLL auto-calibration status indication

TABLE 4-7: RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS
PLL Charge Pump and Loop Filter fQ = fREF/PLL_REFDIV
Parameter fQ<5 MHz 5 MHz ≤ fQ < 25 MHz fQ ≥ 25 MHz
PLL_CHAGPUMP<3:0> 0x04 0x04 0x04
PLL_RES<4:0> 0x1F 0x1F 0x07
PLL_CAP3<4:0> 0x07 0x02 0x07
PLL_CAP2<4:0> 0x07 0x01 0x08
PLL_CAP1<4:0> 0x07 0x01 0x08
TABLE 4-8: EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 80 MHz WITH fREF = 40 MHz
PLL Control Parameter Value Descriptions
fREF 40 MHZ fREF is coming from the external clock input
Target fS(1) 80 MHZ ADC sampling frequency
Target fVCO(2) 1.2 GHZ Range of fVCO = 1.0375 GHz – 1.325 GHz
Target fQ(3) 10 MHZ fQ = fREF/PLL_REFDIV (See Table 4-7)
PLL Reference Divider (R) 4 PLL_REFDIV<9:0> = 0x004
PLL Prescaler (N) 120 PLL_PRE<11:0> = 0x078
PLL Output Divider 15 PLL_OUTDIV<3:0> = 0xF
Note 1: fS = fVCO/PLL_OUTDIV = 1.2 GHz/15 = 80 MHz
2: fVCO = (N/R) x fREF = (30) x 40 MHz = 1.2 GHz
3: fQ should be maximized for the best noise performance.

4.8 Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the Configuration bits. Table 4-9
summarizes the digital signal post-processing (DSPP)
options that are available for each device family.
TABLE 4-9: DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS

Digital Signal Post Processing Option Available Operating Mode
Fractional Delay Recovery (FDR) Dual and octal-channel modes
FIR Decimation Filters • Single and dual-channel modes
• CW octal-channel mode
• DDC for I and Q data
Noise-Shaping Requantizer (NSR) Single and dual-channel modes
Digital Gain and Offset correction per channel Available for all channels
Digital-Down Conversion (DDC) • Single and dual-channel modes
• CW octal-channel mode
Continuous Wave (CW) Beamforming CW octal-channel mode
4.8.1 FRACTIONAL DELAY RECOVERY

FOR DUAL- AND OCTAL-CHANNEL
FIR
MODES Decimation Filters
ADC Output for
The fractional delay recovery (FDR) feature is available dual or octal-channel
in dual and octal-channel modes only. When FDR is Noise-Shaping
enabled, the built-in high-order, band-limited Requantizer
interpolation filter compensates for the time delay (NSR)
Fractional Delay
between input samples of different channels. Due to Recovery Digital
the finite bandwidth of the interpolation filter, the (FDR) Down-Conversion (DDC)
fractional delay recovery is not guaranteed for input
frequencies near the Nyquist frequency (fS/2). For FDR Control Digital Gain/Offset
example, in dual-channel mode, FDR can operate Correction per Channel
correctly for input frequencies in the range from 0 to
0.45*fS (or from 0.55*fs to fS if the input is in the 2nd CW
Nyquist band). In octal-channel mode, FDR can Beamforming
operate correctly for input frequencies in the range ADC output data after
from 0 to 0.38*fS. See Table 4-11 for the summary of sampling time delay between
the input bandwidth requirement for FDR. The FDR channels is removed.
process takes place in the digital domain and requires FIGURE 4-12: Simplified Block Diagram for
59 clock cycles of processing time. Therefore, the ADC Output Data Path with Fractional Delay
output data latency is also increased by 59 clock
Recovery Option. Note that Fractional Delay
periods.
Recovery occurs prior to other DSPP features.
Figure 4-12 shows the simplified block diagram for the
ADC output data path with FDR. The related
Configuration register bits are listed in Table 4-10.
Table 4-11 shows the input bandwidth limits of the FDR
feature for distortion less than 0.1 mdB (0.1 × 10-3 dB),
where fS is the sampling frequency per channel.
Figures 4-13 and 4-14 show the responses of the dual-
channel and octal-channel FDRs, respectively.

TABLE 4-10: CONTROL PARAMETERS FOR FRACTIONAL DELAY RECOVERY (FDR)
Channel Operation Control Parameter Register Descriptions
Global control for both EN_FDR = 1 0x7A Enable FDR features
dual and octal-channel FDR_BAND 0x81 Select 1st or 2nd Nyquist band
modes
Dual-channel SEL_FDR = 0 0x81 Select FDR for dual-channel mode
EN_DSPP_8 = 0 0x81 Select digital signal post-processing feature for
dual-channel mode
EN_DSPP_2 = 1 0x79 Enable all digital post-processing functions for
dual-channel operation
Octal-channel SEL_FDR = 1 0x81 Select FDR for octal-channel mode
EN_DSPP_8 = 1 0x81 Select digital signal post-processing feature for
octal-channel operation
TABLE 4-11: INPUT BANDWIDTH
In-Band Ripple
REQUIREMENT FOR FDR 0.0005
0
Bandwidth
(2)
in percentage Nyquist Band -0.0005
0 fS/2 fS
of fS(1) Interpolation Filter Frequency Response
0
Dual-Channel Mode
1st Nyquist Band (FDR_BAND = 0)
Amplitude (dBc)
0 – 45% -30
55 – 100% 2nd Nyquist Band (FDR_BAND = 1)

-60
45 – 55% Avoid
Octal-Channel Mode -90
st
0 – 38% 1 Nyquist Band (FDR_BAND = 0)
-120
Note 1: fs is sampling frequency per channel. 0 fS/2 fS
Frequency
Distortion is less than 0.1 mdB.
2: See Address 0x81 for FDR_BAND bit FIGURE 4-13: Response of the Dual-
setting Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
In-Band Ripple
0.0005
-0.0005
0 fS/2 fS 2×fS 3×fS 4×fS
Frequency
0
Amplitude (dBc)
-30
-60
-90
-120
0 fS/2 fS 2×fS 3×fS 4×fS
Frequency
FIGURE 4-14: Response of the Octal-

Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.

4.8.2 NOISE-SHAPING REQUANTIZER EQUATION 4-5: NSR BANDWIDTH FOR
(NSR) 11-BIT OPTION
The device includes 11-bit and 12-bit digital (a) 22% BW:
Noise-Shaping Requantizer (NSR) options. When this f Center 0.22
---------------- = 0.12 + ----------  NSR
function is enabled (see Register 5-33), output data is fS 20
requantized to 11-bit or 12-bit, respectively. The NSR
where 0  NSR  20
reshapes the requantization noise function and
pushes most of the noise outside the frequency band (b) 25% BW:
of interest. As a result, the noise floor within the f Center 0.25
selected bandwidth is substantially lower than that of a ---------------- = 0.125 + ----------   NSR – 21 
fS 20
typical 12-bit ADC.
To ensure the stability of the NSR, the input signal to
the NSR should be limited to less than -0.8 dBFS NSR represents the NSR filter number. See Tables 4-
(~90% of full scale). This can be achieved either by 13 and 4-14 for details.
limiting the analog input level or by adjusting the digital
gain control. See Section 4.9 “Digital Offset and EQUATION 4-6: NSR BANDWIDTH FOR
Digital Gain Settings” and Registers 5-63 to 5-70 for 12-BIT OPTION
details on the digital gain control. Input levels higher
than -0.8 dBFS may corrupt the NSR output and (a) 25% BW:
should be avoided. f Center 0.25
---------------- = 0.125 + ----------   NSR – 42 
The NSR feature is available only for the single- and fS 20
dual-channel modes and can be independently
controlled per channel via the register settings. Two
NSRs are used:
(b) 29% BW:
• NSRA for channel A
fCenter 0.29
• NSRB for channel B ---------------- = 0.15 + ----------   NSR – 63 
fS 12
In single-channel mode, only NSRA is used. In
dual-channel mode, both NSRA and NSRB are used:
NSRA is used for the first selected channel, and
NSRB is used for the second selected channel. Both NSR represents the NSR filter number. See Tables 4-
have 11-bit and 12-bit options. Each NSR block 13 and 4-14 for details.
consists of a series of filters which are selectable using The center frequency of the band is tuned such that
the NSRA<6:0> and NSRB<6:0> register bit settings. the frequency spectrum of interest can be placed
Each filter is defined by a specific percentage anywhere within the Nyquist band. Figure 4-15 shows
bandwidth and center frequency. The available a graphical demonstration of the NSR bandwidth,
percentage bandwidths are: which is a percentage of the ADC sampling frequency.
• 11-bit mode: 22% and 25% of the sampling
frequency

• 12-bit mode: 25% and 29% of the sampling I,1
frequency

The center frequency of the band is tunable such that
the frequency band of interest can be placed
$PSOLWXGH G%)6

anywhere within the Nyquist band. Table 4-12 lists all
the NSR-related registers. Equations 4-5 and 4-6
describe the NSR bandwidth of the 11-bit and 12-bit
options, respectively.
I/ I&HQWHU I+
ELWQRLVHIORRU
WKHUPDOQRLVHIORRU
I%
I6 I6
)UHTXHQF\
FIGURE 4-15: Graphical demonstration of the

NSR filter’s transfer function. Note that fB is controlled
as a percentage of the sampling frequency (fS).

Tables 4-13 and 4-14 show the NSR filter selections. When the NSR block is disabled, the ADC data is
The selectable filters (tuning word) for each mode are: provided directly to the output.
• 11-bit mode: 0 to 41
• 12-bit mode: 42 to 76
NSR does not affect harmonic distortion. Various FFT
spectrum plots when NSR is applied are shown in
Figure 3-13 to Figure 3-18. As shown in these plots,
high SNR can be achieved by utilizing the NSR
feature. The SNR is calculated within the defined NSR
bandwidth. SNR and SFDR performance versus input
amplitude when NSR is enabled is shown in Figure 3-
21. When the NSR block is disabled, the ADC data is
provided directly to the output.
TABLE 4-12: REGISTER CONTROL PARAMETERS FOR NSR

NSR Enable bits
<EN_NSRA_11> 0x7A Enable 11-bit NSR for channel A
<EN_NSRA_12> 0x7A Enable 12-bit NSR for channel A
<EN_NSRB_11> 0x7A Enable 11-bit NSR for channel B
<EN_NSRB_12> 0x7A Enable 12-bit NSR for channel B
NSR Settings
NSRA<6:0> 0x78 NSR A settings for single-channel or channel A for dual-channel mode
NSRB<6:0> 0x79 NSR B settings for channel B in dual-channel mode
NSR Block Reset Control
<EN_NSR_RESET> 0x78 Resets NSR in the event of overload
Digital Post Processing (DPP) Function Block Settings
EN_DPPDUAL 0x79 Enable DPP block for dual-channel mode
TABLE 4-13: 11-BIT NSR FILTER TABLE 4-14: 12-BIT NSR FILTER
SELECTION(1) SELECTION(1)
NSR Filter No. fB NSRA<6:0> NSR Filter No. fB NSRA<6:0>
fCenter/fS f /f
(Tuning Word) (% of fS) NSRB<6:0> (Tuning Word) Center S (% of fS) NSRB<6:0>
0 0.12 22 000-0000 42 0.125 25 010-1010
1 0.133 22 000-0001 43 0.1375 25 010-1011
2 0.146 22 000-0010 44 0.15 25 010-1100
— —
— 61 0.3625 25 011-1101
19 0.367 22 001-0011 62 0.375 25 011-1110
20 0.38 22 001-0100 63 0.15 29 011-1111
21 0.125 25 001-0101 64 0.1667 29 100-0000
22 0.1375 25 001-0110 65 0.1833 29 100-0001
23 0.15 25 001-0111 —
— —
— 75 0.35 29 100-1011
40 0.3625 25 010-1000 76 0.3667 29 100-1100
41 0.375 25 010-1001 Note 1: Filters 42 - 76 are used for 12-bit mode
Note 1: Filters 0 - 41 are used for 11-bit mode only. If these are used for 11-bit mode, the
only. If these are used for 12-bit mode, the output becomes unknown state.
output becomes unknown state.

4.8.3 DECIMATION FILTERS 4.8.3.1 Output Data Rate and Clock Phase
The decimation feature is available in single and dual- Control When Decimation is Used
channel modes and CW octal-channel mode. When decimation is used, it also reduces the output
Figure 4-16 shows a simplified decimation filter block, clock rate and output bandwidth by a factor equal to
and Table 4-16 shows the register settings. The the decimation rate applied: the output clock rate is
decimation rate is controlled by FIR_A<8:0> and therefore no longer equal to the ADC sampling clock.
FIR_B<7:0> register settings (Addresses 0x7A – The user needs to adjust the output clock and data
0x7C: Registers 5-35 - 5-37). These registers are rates in Address 0x02 (Register 5-3) based on the
thermometer encoded. decimation applied. This allows the output data to be
In single-channel mode, FIR B is disabled and only synchronized to the output data clock.
FIR A is used. In this mode, the maximum Phase shifts in the output clock can be achieved using
programmable decimation rate is 512x using nine DCLK_PHDLY_DEC<2:0> in Address 0x64
cascaded decimation stages. (Register 5-22). Only four output sampling phases are
In dual-channel mode or when using the Digital Down- available when a decimation rate of 2x is used, while
Conversion (DDC) in I/Q mode, both FIR A and FIR B all eight clock phases are available for other
are used (see Figure 4-16). In this case, both channels decimation rates. See Section 4.12.8 “Output Data
are set to the same decimation rate. Note that stage and Clock Rates” for more details.
1A in FIR A is unused: the user must clear FIR_A<0> 4.8.3.2 Using Decimation with CW
in Address 0x7A (Register 5-35). In dual-channel
Beamforming and Digital Down-
mode, the maximum programmable decimation rate is
Conversion
up to 256x, which is half the single-channel decimation
rate (512x). Decimation can be used in conjunction with CW octal-
channel mode or DDC. In CW octal-channel mode
The overall SNR performance can be improved with
operation, the eight input channels are summed into a
higher decimation rate, but limited to about 73.7 dBFS
single channel prior to entering the decimation filters.
after 16x. This limitation is mainly due to the relative
When DDC is enabled, the I and Q outputs can be
quantization noise level with respect to the 12-bit LSB
decimated using the same signal path for the dual-
size. Decimation rates beyond 16x do not further improve
channel mode: I and Q data are fed into Channel A
SNR but do serve to filter the output data and reduce the
and B, respectively.
overall output data rate. Table 4-15 summarizes
decimation rate versus SNR. In DDC mode, the half-band filter already includes a
2x decimation rate. Therefore, the maximum
TABLE 4-15: DECIMATION RATE VS. SNR decimation rate setting for I/Q filtering is 128x for the
PERFORMANCE FIR_A<8:1> and FIR_B<7:0>. See Section 4.8.4
“Digital Down-Conversion” for details.
Decimation Rate SNR (dBFS)
2x 71.4 Note: Fractional Delay Recovery, Digital
4x 72.2 Gain/Offset adjustment and DDC for I/Q
8x 72.9 data options occur prior to the decimation
filters if they are enabled.
16x 73.3
32x
64x
128x 73.7
256x
512x
Note: The above data is validated with
fS = 80 Msps, fIN = 5 MHz, AIN = -1 dBFS.
Note: SNR can be further improved by using

NSR in combination with the Decimation
Filters.

TABLE 4-16: REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS
Decimation Filter Settings
FIR_A<8:0> 0x7A, 0x7B Channel A FIR configuration for single- or dual-channel mode
FIR_B<7:0> 0x7C Channel B FIR configuration for single- or dual-channel mode
Output Data Rate and Clock Rate Settings(1)
OUT_DATARATE<3:0> 0x02 Output data rate: Equal to decimation rate
OUT_CLKRATE<3:0> 0x02 Output clock rate: Equal to decimation rate
Output Clock Phase Control Settings(2)
EN_PHDLY 0x64 Enable digital output phase delay when decimation filter is used
DCLK_PHDLY_DEC<2:0> 0x64 Digital output clock phase delay control
Digital Signal Post-Processing (DSPP) Function Block Settings
EN_DSPP_2 = 1 0x79 Enable dual-channel decimation
Note 1: The output data and clock rates must be updated when decimation rates are changed.
2: Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0>
bit settings.
I
D2 D4 D8
Single-channel operation Single Single Single
Single Stage 3A Stage 9A D512
Stage 1A Stage 2A 2 2
Ch. 2 2 FIR Single
FIR FIR FIR
Input
(Note 1) (Note 3)
Dual Ch. A Stage 9B
Input Stage 2B 2 Stage 3B 2 2 Output
Ch. DeMUX FIR FIR MUX D256
Ch. B FIR
Input
(Note 2) Dual
Dual-channel operation
Output Output D4 Output
MUX MUX Dual MUX D128
D2
Input for DDC Ch. A I/Q
Input Dual
DeMUX
Ch. B
DDC I/Q filtering
Note 1: Stage 1A FIR is the first stage of the FIR A filter.

2: (a) Single-channel mode: Only Channel A is used and controlled by FIR_A<8:0>.
(b) Dual-channel mode or I/Q filtering in DDC mode: Both Channel A and Channel B are used: Channel A is used for
the first channel or I data, and Channel B is used for the second channel or Q data.
3: Maximum decimation rate:
(a) When I/Q filtering in DDC mode is not used: 512x for single-channel and 256x for dual-channel mode.
(b) I/Q filtering in DDC mode: 128x each for FIR_A<8:1> and FIR_B<7:0>.
FIGURE 4-16: Simplified Block Diagram of Decimation Filters.

4.8.4 DIGITAL DOWN-CONVERSION Example:
The Digital Down-Conversion (DDC) feature is If the ADC is sampling an input at 80 Msps, but the user
available in single, dual, and CW octal-channel modes. is only interested in a 2.5 MHz span which is centered
This feature can be optionally combined with the at 20 MHz, the digital down-conversion may be used to
decimation filter and used to: mix the sampled ADC data with 20 MHz to convert it to
• translate the input frequency spectrum to a lower DC. The resulting signal can then be decimated by 16x
frequency band such that the bandwidth of the ADC output is 2.5 MHz
(80 Msps/16x decimation gives 5 Msps with 2.5 MHz
• remove the unwanted out-of-band portion
Nyquist bandwidth). If fS/8 mode is selected, then a
• output the resulting signal as either I/Q data or as single 10 Msps channel is output (corresponding to 5
a real signal centered at 25% of the output data MHz Nyquist bandwidth), where 2.5 MHz in the output
rate. data corresponds to 20 MHz at the ADC input. If I/Q
Figure 4-17 and Figure 4-18 show the DDC mode is selected, then two 5 Msps channels are
configuration for single- and dual-channel DDC mode, output, where DC corresponds to 20 MHz and the
respectively. The DDC includes a 32-bit, complex channels represent in-phase (I) and quadrature (Q)
numerically controlled oscillator (NCO), a selectable components of the down-conversion.
(high/low) half-band filter, optional decimation, and two
output modes (I/Q or fS/8). 4.8.4.1 Single-Channel DDC
Frequency translation is accomplished with the NCO. Figure 4-17 shows the single-channel DDC
The NCO frequency is programmable from 0 Hz to fS. configuration. Each of these processing sub-blocks are
Phase and amplitude dither can be enabled to improve individually controlled. Examples of setting registers for
spurious performance of the NCO. selected output type are shown in Tables 4-17 and 4-18.
This DDC feature can be used in a variety of high-

speed signal-processing applications, including digital
radio, sonar, radar, cable modems, digital video, MRI
imaging, etc.
(Note 5) I or IDEC
Q or QDEC
FIR_A<8:1>
(Note 3)
I
FIR A
CH. A Decimation Filter
Half-Band Filter A fS/8
ADC DATA NCO ( )
Q LP/HP FIR B DER Real
Decimation Filter or
EN_DDC_FS/8 RealDEC
COS SIN HBFILTER_A FIR_B<7:0>
(Note 4)
NCO (32-bit) EN_NCO EN_DDC2
(Note 2) EN_DDC1
Down-Converting and Decimation (Note 1) Decimation and Output Frequency Translation (Note 1)
Note 1: See Address 0x80 - 0x81 (Registers 5-41 – 5-42) for the control parameters.
2: See Figure 4-19 for details of NCO control block.
3: Half-band Filter A includes a single- stage decimation filter.
4: See Figure 4-16 for details.
5: Switches are closed if decimation filter is not used, and open if decimation filter is used.
FIGURE 4-17: Simplified DDC Block Diagram for Single-Channel Mode. See Tables 4-17 and 4-18
for Using This DDC Block.

4.8.4.2 Dual-Channel DDC band filter is up-converted by fS/8 for each channel.
Otherwise, I/Q of each channel will be output
Figure 4-18 shows the dual-channel DDC
separately, similar to a four-channel input device with
configuration. Each channel includes the same
the WCK output pin toggling synchronously with the I-
processing elements as shown in the single-channel
data of Channel A. Note that the NCO phase can be
DDC, however the I/Q outputs cannot be separately
adjusted uniquely for each of the two input channels
decimated since the device only supports two channels
(see Figure 4-19). Examples of setting registers for
of decimation (four would be required for I/Q of
selected output type are shown in Tables 4-19 and 4-
Channel A and I/Q of Channel B). The decimation
20.
option can be used if the DDC output after the half-
IA
ADC QA
Data: (Note 3)
IA
Half-Band Filter A
CH. A QA LP/HP
RealA
COS SIN HBFILTER_A
NCO (32-bit) EN_NCO EN_DDC_FS/8 NCO (fS/8)

(Note 2) EN_DDC2
COS SIN (Note 3)
CH. B QB
RealB
Half-Band Filter B
IB LP/HP
HBFILTER_B IB
EN_DDC1
QB
Down-Converting and Decimation (Note 1) Output Frequency Translation and Decimation (Note 1)
Note 1: See Address 0x80 – 0x81 for the Control Parameters.

2: See Figure 4-19 for details of NCO control block.
3: Half-band Filter A and B include a single-stage decimation filter.
FIGURE 4-18: Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-19 and 4-20 for
Using this DDC Block.

4.8.4.3 Numerically Controlled Oscillator Figure 4-19 shows the control signals associated with
(NCO) the NCO. In octal- or dual-channel mode, the NCO
allows the output phase to be adjusted on a
The on-board Numerically Controlled Oscillator (NCO)
per-channel basis.
provides the frequency reference for the in-phase and
quadrature mixers in the digital down-converter (DDC).
Note: The NCO is only used for DDC or CW octal-
The NCO serves as a quadrature local oscillator, channel mode. It should be disabled when
capable of producing an NCO frequency of between 0 not in use.
Hz and fS with a resolution of fS/232, where fS is the
ADC core sampling frequency.
EN_PHSDITH EN_AMPDITH
CH(n) NCO_PHASE<15:0> Phase Offset Control Phase Dither Amplitude Dither
EN_LFSR EN_LFSR
Sine/Cosine
EN_NCO NCO Tuning NCO Output
Signal Generator
NCO_TUNE<31:0>
FIGURE 4-19: NCO Block Diagram.

• NCO Frequency Control: 4.8.4.4 NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
The NCO frequency is programmed from 0 Hz to fS,
Address 0x80 (Register 5-41) can be used for
using the 32-bit-wide unsigned register variable
amplitude and phase dithering, respectively. In
NCO_TUNE<31:0> in Addresses 0x82 – 0x85
principle, these will dither the quantization error created
(Registers 5-43 – 5-46).
by the use of digital circuits in the mixer and local
The following equation is used to set the oscillator, thus reducing spurs at the expense of noise.
NCO_TUNE<31:0> register: In practice, the DDC circuitry has been designed with
sufficient noise and spurious performance for most
EQUATION 4-7: NCO FREQUENCY applications. In the worst-case scenario, the NCO has
Mod  fNCO f S  an SFDR of greater than 116 dB when the amplitude
NCO_TUNE<31:0> = round  2
32

 -----------------------------------
-
 dither is enabled, and 112 dB when disabled. Although
fS
Where: the SNR (≈ 93 dB) of the DDC is not significantly
affected by the dithering option, using the NCO with
fS = sampling frequency (Hz) dithering options enabled is always recommended for
fNCO = desired NCO frequency (Hz) the best performance.
Mod (fNCO, fS) = gives the remainder of fNCO/fS
4.8.4.5 NCO for fS/8 and fS/(8xDER)
The output of the first down-conversion block (DDC1)
Mod() is a remainder function. For example, is a complex signal (comprising I and Q data) which can
Mod(5,2) = 1 and Mod(1.999, 2) = 1.999. then be optionally decimated further up to 128x to
Example 1: provide both a lower output data rate and input channel
filtering. If fS/8 mode is enabled, a second mixer stage
If fNCO is 40 MHz and fS is 80 MHz:
(DDC2) will convert the I/Q signals to a real signal
centered at half of the current Nyquist frequency; i.e., if
the output data rate in I/Q mode is 10 Msps per channel
Mod  f NCO f S  = Mod  40 80  = 40
(5 MHz Nyquist), then in fS/8 mode the output data rate
32 Mod  40 80 
NCO_TUNE<31:0> = round  2  --------------------------------- would be 20 Msps (10 Msps each for I and Q), and the
80 signal would be re-centered around 5 MHz. In
= 0x8000 0000
single-channel mode, this is done at the output of the
Example 2: decimation filters (if used). In dual-channel mode, this
must be done prior to the decimation.
If fNCO is 79.99999994 MHz and fS is 80 MHz:
When decimation is enabled, the I/Q outputs are up-
converted by fS/(8xDER), where DER is the additional
Mod  f NCO f S  = Mod  79.99999994 80  = 79.99999994 decimation rate added by the FIR decimation filters.
32 Mod  79.99999994 80  This provides a decimated output signal centered at
NCO_TUNE<31:0> = round  2  -----------------------------------------------------------------
80 fS/8 or fS/(8xDER) in the frequency domain.
= 0xFFFF FFFD

4.8.4.6 NCO Phase Offset Control 4.8.4.8 Half-Band Filter
The user can add phase offset to the NCO frequency The frequency translation is followed by a half-band
using the NCO phase offset control registers digital filter, which is used to reduce the sample rate by
(Addresses 0x86 to 0x95, Registers 5-47 – 5-62). a factor of two while rejecting aliases that fall into the
CH(n)_NCO_PHASE<15:0> is the 16-bit-wide NCO band of interest.
phase offset control parameter for Channel n. A The user can select high- or low-pass half-band filter
0x0000 value in the register corresponds to no offset, using the HBFILTER_A and HBFILTER_B bits in
and a 0xFFFF corresponds to an offset of 359.995°. Address 0x80 (Register 5-41). These filters provide
The phase offset can be controlled with 0.005° per greater than 90 dB of attenuation in the attenuation
step. The following equation is used to program the band and less than 1 mdB (10-3 dB) of ripple in the
NCO phase offset register: passband region of 20% of the input sampling rate.
For example, for an ADC sample rate of 80 MSPS,
EQUATION 4-8: NCO PHASE OFFSET these filters provide less than 1 mdB of ripple over a
bandwidth of 16 MHz.
16 Offset Value (  
CH(n)_NCO_PHASE<15:0> = 2  --------------------------------------- The filter responses shown in Figures 4-16 and 4-17
360
Where: indicate a ripple of 0.5 mdB and an alias rejection of
90 dB. The output of the half-band filter is a
n = channel number DC-centered complex signal (I and Q). This I and Q
Offset Value () = desired phase offset value in signal is then carried to the next down-conversion
degrees stage (DDC2) for frequency translation (up-
conversion), if the DDC is enabled.
A decimal number is used for the binary contents of
Note: The half-band filter delays the data output
CH(n)_NCO_PHASE<15:0>.
by 80 clock cycles: 2 (due to decimation) x
4.8.4.7 In-Phase and Quadrature Signals 40 cycles (due to group delay)
When the first down-conversion is enabled, it produces

In-Band Ripple
In-phase (I) and Quadrature (Q) components as shown 0.0005
in Equation 4-9: 0
-0.0005
0 0.1 0.2 0.3 0.4 0.5
EQUATION 4-9: I AND Q SIGNALS Half-Band Filter Frequency Response
0
I = ADC  COS  2  fNCO t +   (a)

Amplitude (dBc)
-30
Q = ADC  SIN  2  fNCO t +   (b)
-60
where:
CH(n)_NCO_PHASE<15:0> (c)
 = 360  ----------------------------------------------------------------------
16
- -90
2
= 0.005493164   CH(n)_NCO_PHASE<15:0> -120
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
where:
FIGURE 4-20: High-Pass (HP) Response
ADC = output of the ADC block
of Half-Band Filter.
 = NCO phase offset of selected channel, which
is defined by CH(n)_NCO_PHASE<15:0> in In-Band Ripple
0.0005
Addresses 0x86 - 0x95
0
t = k/fS, with k =1, 2, 3,..., n
-0.0005
fNCO = NCO frequency 0 0.1 0.2 0.3 0.4 0.5
Half-Band Filter Frequency Response
0
I and Q outputs are interleaved where I data is output

Amplitude (dBc)
-30
on the rising edge of the WCK. If I and Q outputs are
selected in dual-channel mode with DDC enabled, I -60
data of Channel 0 is output at the rising edge of WCK,
followed by Q data of Channel 0, then I and Q data of
-90
Channel 1 in the same way.
-120
0 0.1 0.2 0.3 0.4 0.5
Fraction of Input Sample Rate
FIGURE 4-21: Low-Pass (LP) Response of

Half-Band Filter.

4.8.5 EXAMPLES OF REGISTER
SETTINGS FOR USING DDC AND
DECIMATION
The following tables show examples of setting registers
for using decimation and digital down-conversion
(DDC) depending on the output type selection.
TABLE 4-17: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS

FOR SINGLE-CHANNEL MODE – EXAMPLE
(by FIR A and FIR B)(1)
Dual-Channel
FIR A Filter FIR B Filter DDC1 DDC2
DSPP Control
Decimation Rate
0x80<5,1,0>(3)
0x81<6,3,2>(4)
(EN_DSPP_2)
(FIR_A<8:1>)
(FIR_B<7:0>)
DDC Addr. (FIR_A<0>)
Output
0x7A<6>
0x79<7>
Mode 0x02(2)
0x7B
0x7C
0 Disabled 0x00 0 0x00 0x00 0,0,0 0,0,0 0 ADC
8 Disabled 0x33 1 0x03 0x00 0,0,0 0,0,0 0 ADC with decimation
(÷8)
512 Disabled 0x99 1 0xFF 0x00 0,0,0 0,0,0 0 ADC with decimation
(÷512)
0 I/Q 0x00(5) 0 0x00 0x00 1,0,1 0,0,0 0 I/Q Data
8 I/Q 0x33 0 0x07 0x07 1,0,1 0,0,0 0 Decimated I/Q (÷8)
0 fS/8 0x11(6) 0 0x00 0x00 1,1,1 0,0,0 0 Real without
additional decimation
8 fS/8 0x44 0 0x07 0x07 1,0,1 1,0,0 0 Real with decimation
(÷16)
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-I/Q option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
6: The Half-Band Filter A includes decimation of 2.

TABLE 4-18: OUTPUT TYPE VS. CONTROL PARAMETERS FOR SINGLE-CHANNEL DDC
(EXAMPLE)
Output Type Control Parameter Register Descriptions
Complex: I and Q EN_DDC1 = 1 0X80 Enable DDC1 block
EN_NCO = 1 0X80 Enable 32-bit NCO
HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation
EN_DDC_FS/8 = 0 0X80 NCO(fS/8/DER) is disabled
EN_DDC2 = 0 0X81 DDC2 is disabled
FIR_A<8:1> = 0x00 0X7B FIR A decimation filter is disabled
FIR_B<7:0> = 0x00 0X7C FIR B decimation filter is disabled
OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change)
Decimated I and EN_DDC1 = 1 0X80 Enable DDC1 block
Q:IDEC, QDEC EN_NCO = 1 0X80 Enable 32-bit NCO
FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(1)
FIR_B<7:0> 0X7C Program FIR B filter for extra decimation(1)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the decimation rate
Real: RealA after EN_DDC1 = 1 0X80 Enable DDC1 block
DDC(fS/8/DER) EN_NCO = 1 0X80 Enable 32-bit NCO
without using
Decimation Filter
EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8(2)
EN_DDC2 = 1 0X81 DDC2 is enabled
FIR_A<8:1> = 0x00 0X7B Decimation filter FIR A is disabled
FIR_B<7:0> = 0x00 0X7C Decimation filter FIR B is disabled
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to divided by 2(3)
= 0001
Decimated Real: EN_DDC1 = 1 0X80 Enable DDC1 block
RealA_DEC EN_NCO = 1 0X80 Enable 32-bit NCO
after Decimation
Filter and
DDC(fS/8/DER) EN_DDC_FS/8 = 1 0X80 NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8/DER(2)
FIR_A<8:1> 0X7B Program FIR B filter for extra decimation(4)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the
input is already decimated by 2x in the Half-Band Filter. See Figure 4-16 for details.
2: DER is the decimation rate setting of the FIR A and FIR B filters.
3: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
4: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).

TABLE 4-19: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS FOR DUAL-CHANNEL
MODE EXAMPLE
Dual-Channel
(by FIR A and FIR B)(1)
FIR A Filter FIR B Filter DDC1 DDC2 DSPP

Decimation Rate
Address 0x02(2)
DDC-Mode Control
0x80<5,1,0>(3)
0x81<6,3,2>(4)
(EN_DSPP_2)
(FIR_A<8:1>)
(FIR_B<7:0>)
Output
(FIR_A<0>)
0x7A<6>
0x79<7>
0x7B
0x7C
0 Disabled 0x00 0 0x00 0x00 0,0,0 0,0,0 0 ADC
8 Disabled 0x33 0 0x07 0x07 0,0,0 0,0,0 0 ADC with decimation (÷8)
256 Disabled 0x88 0 0xFF 0xFF 0,0,0 0,0,0 0 ADC with decimation (÷256)
0 I/Q 0x00(5) 0 0x00 0x00 1,0,1 0,0,0 1 I/Q data
0 fS/8 0x11(6) 0 0x00 0x00 1,1,1 0,0,0 1 Real without additional
decimation
8 fS/8 0x44 0 0x0E 0x0E(7) 1,1,1 0,0,0 1 Real with decimation filter
(÷16)
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-fS/2 option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of fS bandwidth. The combined bandwidth is the same as the fS bandwidth. Therefore the data rate
adjustment is not needed.
6: The Half-Band Filter A/B includes decimation of 2.
7: 0x0E takes into account the stages 1 and 2 are bypassed. See Figure 4-16 for “dual-channel Input” for DDC.

TABLE 4-20: OUTPUT TYPE VS. CONTROL PARAMETERS FOR DUAL-CHANNEL DDC EXAMPLE
Output Type Control Parameter Register Descriptions
Complex: I and Q EN_DSPP_2 = 1 0X79 Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 1 0X80 Enable DDC1 block
HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation
FIR_A<8:1> = 0x00 0X7B FIR A decimation filter is disabled
FIR_B<7:0> = 0x00 0X7C FIR B decimation filter is disabled
OUT_CLKRATE<3:0> 0X02 Output clock rate is not affected (no need to change)
Real: RealA for EN_DSPP_2 = 1 0X79 Enable all digital post-processing functions for dual-channel
Channel A operations
and RealB for EN_DDC1 = 1 0X80 Enable DDC1 block
Channel B after
NCO(fS/8/DER)
Without Using HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation
Decimation Filter HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation
from DC to fS/8(1)
FIR_A<8:1> = 0x00 0X7B Decimation filter FIR A is disabled
FIR_B<7:0> = 0x00 0X7C Decimation filter FIR B is disabled
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to divided by 2(2)
= 0001
Decimated Real: EN_DSPP_2 = 1 0X79 Enable all digital signal post-processing functions for dual-
RealA_DEC for channel operation
Channel A and EN_DDC1 = 1 0X80 Enable DDC1 block
RealB_DEC for
Channel B after
NCO(fS/8/DER) and HBFILTER_A = 1 0X80 Enable Half-Band Filter A, includes 2x decimation
Decimation Filter HBFILTER_B = 1 0X80 Enable Half-Band Filter B, includes 2x decimation
from DC to fS/8/DER(1)
FIR_A<8:1> 0X7B Program FIR A filter for extra decimation(3)
OUT_CLKRATE<3:0> 0X02 Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: DER is the decimation rate setting of the FIR A and FIR B filters.
2: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
3: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).

4.9 Digital Offset and Digital Gain 4.9.2 DIGITAL GAIN SETTINGS
Settings CH(N)_DIG_GAIN<7:0> in Addresses 0x96 – 0x9D
(Registers 5-63 – 5-70) is used to adjust the digital gain
Figure 4-22 shows a simplified block diagram of the
per channel.
digital offset and gain settings. Offset is applied prior to
the gain. Offset and gain adjustments occur prior to
DDC, Decimation or FDR when these features are Note 1: Digital Offset Setting: Register mapping
used. (0x9E – 0xA7) to the corresponding
channel is not sequential to the channel
4.9.1 DIGITAL OFFSET SETTINGS order defined by CH_ORDER<23:0>,
except for the octal-channel mode. See
The offset can be corrected using a 16-bit-wide global Table 4-21 for details.
offset correction register (0x66) for all channels, offset
correction registers for individual channels (0x9E- 2: Gain and NCO Phase Offset: Register
0xA7) or by combining both global and individual offset mapping to the corresponding channel is
correction registers. The offset control for individual sequential to the channel order defined
channels can be used with DIG_OFFSET_WEIGHT by CH_ORDER<23:0>.
<1:0> in 0xA7. The corresponding registers for each
correction are shown in Figure 4-22.
Note that, except for the octal-channel mode, the offset
setting registers for individual channels, 0x9E-0xA7
(Registers 5-71 – 5-79), do not sequentially
correspond to the channel order defined by
CH_ORDER<23:0>. Table 4-21 shows the details of
the offset registers that correspond to the actual
channels, depending on the number of channels used.
ADC Corrected
Output ADC Output
Global Digital Offset Control Digital Offset Control Digital Gain Control
for all channels for individual channel for individual channel
DIG_OFFSET_GLOBAL<15:0> CH(n)_DIG_OFFSET<7:0> CH(n)_DIG_GAIN<7:0>
(See Address 0x66) (See Addresses 0x9E – 0xA5) (See Addresses 0x96 – 0x9D)
DIG_OFFSET_WEIGHT<1:0>
(See Address 0xA7)
FIGURE 4-22: Simplified Block Diagram for Digital Offset and Gain Settings.
TABLE 4-21: REGISTER ASSIGNMENT FOR OFFSET SETTING

Channel Used
Register Address for Offset Setting

Number of
1st Channel 2nd Channel 3rd Channel 4th Channel 5th Channel 6th Channel 7th Channel 8th Channel
1 0x9F ─ ─ ─ ─ ─ ─ ─
2 0xA0 0x9F ─ ─ ─ ─ ─ ─
3 0xA1 0x9F 0xA0 ─ ─ ─ ─ ─
4 0xA2 0x9F 0xA0 0xA1 ─ ─ ─ ─
5 0xA3 0x9F 0xA0 0xA1 0xA2 ─ ─ ─
6 0xA4 0x9F 0xA0 0xA1 0xA2 0xA3 ─ ─
7 0xA5 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 ─
8 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5

4.10 Continuous Wave (CW) Digital beamforming is a digital signal processing
Beamforming and Ultrasound technique that requires summing all input signals from
different channels after correcting for time delay. The
Doppler Signal Processing Using
time-delay correction involves the phase alignment of
CW Octal-Channel Mode the detected signals with respect to a reference.
(MCP37D11-80 only)
Along with beamforming, many modern medical
In modern ultrasound medical applications, large ultrasound devices support Doppler imaging, which
numbers of transducers are often used. The signals processes phase information in addition to the classical
from these sensors are then coherently combined for magnitude detection (for brightness imaging).
higher transducer gain and directivity. The signals from Ultrasound Doppler signal processing is used to
each sensor arrive at the detection device with a determine movement in the body as represented by
different time delay. Also, in multi-channel scanning blood flow, which can help diagnose the functioning of
operations using the MUX, there is a time delay a heart valve or blood vessel, etc. In a traditional
between acquiring input signals (see Section 4.8.1 ultrasound system, all of these functions are typically
“Fractional Delay Recovery for Dual- and Octal- accomplished with discrete components. Figure 4-24
Channel Modes”). These time delays may need to be shows an example of an ultrasound system
corrected before all input signals are combined for the implementation using various specialized components.
signal processing.
HV Beamformer Central
Amp DAC Isolation
Control Processor
LNA-VGA-ADC Array (up to 256 Channels)
AAF
HV MUX and T/R
T/R Switches
LNA VGA ADC
Switcher Digital RX Beamformer
Clocks
Transducer
Array
Amp ADC Image and Color
CW
I/Q Doppler Motion Doppler
Processing Processing Video
Processing Processing
(B Mode) (F Mode) Compression
Amp ADC
Video DAC/ Amp/

Video Encoder Filter
Audio
DAC Amp
FIGURE 4-23: Example of Ultrasound System Building Block.

4.10.1 BEAMFORMING 4.10.2 ULTRASOUND DOPPLER SIGNAL
Beamforming is achieved by scanning all inputs while PROCESSING
correcting the phase of each channel with respect to a Doppler shift measurement requires summing the input
reference. This can be done using: signals from multiple transducer channels and mixing
• Fractional Delay Recovery (FDR) them with a phase-controlled local oscillator frequency.
The resulting low-frequency output is then centered
• Phase offset settings of each individual channel
near DC and can measure a Doppler shift produced by
• Gain setting per channel moving objects, such as blood flow and changes in
While the CW input channel is multiplexed sequentially, blood pressure in arteries, etc. In traditional Doppler
the phase offset can be added to the NCO output (each measurement, many discrete analog components are
channel individually). CH(n)_NCO_PHASE<15:0>, in typically used along with a high-resolution ADC.
Addresses 0x86 to 0x95 (Registers 5-47 – 5-62), This device has unique built-in features that are
corrects the time delay of the incoming signals with suitable for ultrasound Doppler shift measurements. By
respect to the reference. utilizing these features, system engineers can reduce
The phase-compensated input signal is then down- many discrete components which are otherwise
converted by a wide dynamic range I/Q demodulator. necessary for an ultrasound Doppler measurement
The digital beamforming of the inputs is then obtained system.
by summing I and Q data from individual channels. The The following built-in digital signal post-processing
combined I and Q data are fed to the half-band filter. (DSPP) features in the MCP37D11-80 can be
Equation 4-10 shows the I and Q data of an individual effectively used for the ultrasound Doppler signal
channel with phase correction (phase offset), and the processing applications:
resulting digital beamforming signal.
• Fractional Delay Recovery (FDR): Correct the
The processing blocks after the digital beamforming time delay of signal sampled between channels.
are the same as the sub-blocks used in single-channel See details in Section 4.8.1 “Fractional Delay
operation described in Section 4.8.4.1 “Single- Recovery for Dual- and Octal-Channel
Channel DDC”, except only limited decimation rates of Modes”.
the FIR A and FIR B filters are used due to the
• Digital Gain and Offset adjustment for each
processing time requirement for summing the input
channel: See details in Section 4.9 “Digital
signals from all channels.
Offset and Digital Gain Settings”.
• Down-Conversion for each channel with a
EQUATION 4-10: BEAMFORMING SIGNALS
unique phase of the same NCO frequency prior to
I CH  n  = ADC  COS  2  f NCO t +   n   summing the eight channels as shown in
Figure 4-24.
Q CH  n  = ADC  SIN  2  f NCO t +   n  
• After down-conversion by the DDC, the resulting
N signal can then be decimated to achieve very high
I =
 ICH  n  SNR in a narrow bandwidth.
n=0
N
Q =
 QCH n 
n=0
CH(n)_NCO_PHASE<15:0>
  n  = 360   ----------------------------------------------------------------------
16
-
2
= 0.005493164   CH(n)_NCO_PHASE<15:0>
Where:
(n) = NCO phase offset of channel n
ADC = the output of the ADC block
The NCO phase offset can be controlled by

0.005493164° per step. See Section 4.8.4.6 “NCO
Phase Offset Control” for details.

I
I or IDEC
(Note 1)
Q or QDEC
MUX
HBFILTER_A FIR_A<8:1>
ADC ICH(n)
Data: FIR A
Half-Band Filter A Decimation Filter fS/8
CH. 0 NCO ( )
LP/HP FIR B DER Real
Decimation Filter
EN_DDC_FS/8 or
CH. 1 COS SIN QCH(n) RealDEC
FIR_B<7:0>
EN_AMPDITH EN_DDC2
NCO Amplitude Dither
CH. 2 EN_LFSR
Sine/Cosine Decimation and Output Frequency Translation

Signal Generator
EN_PHSDITH
NCO Phase Dither
CH. 7 EN_LFSR
NCO Phase Offset Control CH(n) NCO_PHASE<15:0>
NCO (32-bit) EN_NCO
NCO_TUNE<31:0>
EN_DDC1
(2)
Channel Multiplexing/Down-Converting/Digital Beamforming/Decimation (2x)
Note 1: Switches are closed if a decimation filter is not used, and open if a decimation filter is used.
2: Digital Gain and Offset adjustments are applied prior to the Digital Down-Converter and
are not shown here.
FIGURE 4-24: Simplified Block Diagram of CW Beamforming and I/Q Signal Processing.

4.11 Output Data format Table 4-22 shows the relationship between the analog
input voltage, the digital data output bits and the
The device can output the ADC data in offset binary or
overrange bit. By default, the output data format is
two’s complement. The data format is selected by the
two’s complement.
DATA_FORMAT bit in Address 0x62 (Register 5-20).
TABLE 4-22: ADC OUTPUT CODE VS. INPUT VOLTAGE (12-BIT MODE)
Input Range Offset Binary(1) Two’s Complement(1) Overrange (OVR)
AIN > AFS 1111-1111-1111 0111-1111-1111 1
AIN = AFS 1111-1111-1111 0111-1111-1111 0
AIN = AFS – 1 LSb 1111-1111-1110 0111-1111-1110 0
AIN = AFS – 2 LSb 1111-1111-1100 0111-1111-1100 0
•
•
AIN = AFS/2 1100-0000-0000 0100-0000-0000 0
AIN = 0 1000-0000-0000 0000-0000-0000 0
AIN = -AFS/2 0011-1111-1111 1011-1111-1111 0
•
•
AIN = -AFS + 2 LSb 0000-0000-0010 1000-0000-0010 0
AIN = -AFS + 1 LSb 0000-0000-0001 1000-0000-0001 0
AIN = -AFS 0000-0000-0000 1000-0000-0000 0
AIN < -AFS 0000-0000-0000 1000-0000-0000 1
Note 1: MSb is sign bit
4.12 Digital Output 4.12.2 DOUBLE DATA RATE LVDS MODE
The device can operate in one of the following two In double-data-rate LVDS mode, the output is a
digital output modes: parallel data stream which changes on each edge of
the output clock. See Figure 2-2 for details.
• Full-Rate CMOS
• Double-Data-Rate (DDR) LVDS In multi-channel configuration, the data is output
sequentially with the WCK that is synchronized to the
The outputs are powered by DVDD18 and GND. The
first sampled channel.
digital output mode is selected by the
OUTPUT_MODE<1:0> bits in Address 0x62 The device outputs the following LVDS output pairs:
(Register 5-20). Figures 2-1 – 2-2 show the timing • Output Data: Q5+/Q5- through Q0+/Q0-
diagrams of the digital output. • OVR/WCK
4.12.1 FULL RATE CMOS MODE • DCLK+/DCLK-
In full-rate CMOS mode, the data outputs (Q11 to Q0, A 100Ω differential termination resistor is required for
overrange indicator (OVR), word clock (WCK) and the each LVDS output pin pair. See <LVDS_LOAD> bit
data output clock (DCLK+, DCLK–) have CMOS out- option in Register 0x63 for using internal terminator.
put levels. The digital output should drive minimal The termination resistor should be located as close as
capacitive loads. If the load capacitance is larger than possible to the LVDS receiver. By default, the outputs
10 pF, a digital buffer should be used. are standard LVDS levels: 3.5 mA output current with
a 1.15V output Common-mode voltage on a 100 dif-
ferential load. See Address 0x63 (Register 5-21) for
more details of the LVDS mode control.
Note: Output Data Rate in LVDS Mode: In octal-

channel mode, the input sample rate per
channel is fS/8. Therefore, the output data
rate required to shift out all 12 bits in DDR is
still equivalent to fS. For example, if fS =
80 Msps, each channel’s sample rate is
fS/8 = 10 Msps, and the output clock rate
(DCLK) for 12-bit DDR output is 80 MHz.

4.12.3 OVERRANGE BIT (OVR) Address 0x63 (Register 5-21). The internal termination
helps absorb any reflections caused by imperfect
The input overrange status bit is asserted (logic high)
impedance termination at the receiver.
when the analog input has exceeded the full-scale
range of the ADC in either the positive or negative
4.12.8 OUTPUT DATA AND CLOCK RATES
direction. In LVDS DDR Output mode, the OVR bit is
multiplexed with the word clock (WCK) output bit such The user can reduce output data and output clock rates
that OVR is output on the falling edge of the data output using Address 0x02 (Register 5-3). When decimation
clock and WCK on the rising edge. or digital down-conversion (DDC) is used, the output
data rate has to be reduced to synchronize with the
The OVR bit has the same pipeline latency as the reduced output clock rate.
ADC data bits. In multi-channel mode, the OVR is
output independently for each input channel and is 4.12.9 PHASE SHIFTING OF OUTPUT
synchronized to the data. See Address 0x68 CLOCK (DCLK)
(Register 5-26) for OVR and WCK control options.
In full-rate CMOS mode, the data output bit transition
If DSPP options are enabled, OVR pipeline latency will occurs at the rising edge of DCLK+, so the falling edge
be unaffected; however, the data will incur additional of DCLK+ can be used to latch the output data.
delay. This has the effect of allowing the OVR indicator
to precede the affected data. In double-data-rate LVDS mode, the data transition
occurs at both the rising and falling edges of DCLK+.
4.12.4 WORD CLOCK (WCK) For adequate setup and hold time when latching the
data into the external host device, the user can shift the
The word clock output bit indicates the start of a new
phase of the digital clock output (DCLK+/DCLK-)
data set. In single-channel mode, this bit is disabled
relative to the data output bits.
except for I/Q output mode. In DDR output with multi-
channel mode, it is always asserted coincidentally with The output phase shift (delay) is controlled by each
the data from the first sampled channel, and unique register depending on which timing source is
multiplexed with the OVR bit. See Address 0x07 used or if decimation is used. Table 4-24 shows the
(Register 5-5) and Address 0x68 (Register 5-26) for output clock phase control registers for each
OVR and WCK control options. Configuration mode: (a) when DLL is used, (b) when
decimation is used, and (c) when PLL is used.
4.12.5 LVDS OUTPUT POLARITY Figure 4-25 shows an example of the output clock
CONTROL phase delay control using the DCLK_PHD-
In LVDS mode, the output polarity can be controlled LY_DLL<2:0> when DLL is used.
independently for each LVDS pair. Table 4-23
summarizes the LVDS output polarity control register
bits.
TABLE 4-23: LVDS OUTPUT POLARITY
CONTROL
Control
Register Descriptions
Parameter
POL_LVDS<7:0> 0x65 Control polarity of LVDS
data pairs
POL_WCK_OVR 0x68 Control polarity of WCK
and OVR bit pair
4.12.6 PROGRAMMABLE LVDS OUTPUT

In LVDS mode, the default output driver current is
3.5 mA. This current can be adjusted by using the
LVDS_IMODE<2:0> bit setting in Address 0x63
(Register 5-21). Available output drive currents are
1.8 mA, 3.5 mA, 5.4 mA and 7.2 mA.
4.12.7 OPTIONAL LVDS DRIVER

INTERNAL TERMINATION
In most cases, using an external 100Ω termination
resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by setting the LVDS_LOAD bit in

TABLE 4-24: OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS

Control Parameter Register Operating Condition(1)
When DLL is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DLL<2:0> 0x52 DCLK phase delay control when DLL is used. Decimation is not used.
When decimation is used:
EN_PHDLY 0x64 EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DEC<2:0> DCLK phase delay control when decimation filter is used. The phase delay
is controlled in digital clock output control block.
When PLL is used:
DCLK_DLY_PLL<2:0> 0x6D DCLK delay control when PLL is used.
Note 1: See Figure 4-11 for details.
LVDS Data Output:
Phase Shift:
DCLK_PHDLY_DLL<2:0>
0° (Default)(1) = 0 0 0
45° + Default 0 0 1
90° + Default 0 1 0
135° + Default 0 1 1
Output Clock
(DCLK+) 180° + Default 1 0 0
225° + Default 1 0 1
270° + Default 1 1 0
315° + Default 1 1 1
Note 1: Default value may not be 0° in all operations.
FIGURE 4-25: Example of Phase Shifting of Digital Output Clock (DCLK+) when DLL is Used.

4.12.10 DIGITAL OUTPUT RANDOMIZER To decode the randomized data, the reverse operation
is applied: an exclusive-OR operation is applied
Depending on PCB layout considerations and power
between the LSb (D0) and all other bits. The DCLK,
supply coupling, SFDR may be improved by
OVR, WCK and LSb (D0) outputs are not affected.
decorrelating the ADC input from the ADC digital output
Figure 4-26 shows the block diagram of the data ran-
data. The device includes an output data randomizer
domizer and decoder logic. The output randomizer is
option. When this option is enabled, the digital output is
enabled by setting the EN_OUT_RANDOM bit in
randomized by applying an exclusive-OR logic
Address 0x07 (Register 5-5).
operation between the LSb (D0) and all other data
output bits.
MCP37D11-80 Data Acquisition Device
DCLK
DCLK DCLK
OVR OVR
OVR
WCK
WCK WCK
Q11 Q11 Q0
Q11
Q10 Q10 Q0
Q10
Q2 Q2 Q0
Q2
Q1 Q1 Q0
Q1
EN_OUT_RANDOM Enable
Q0
Q0 Q0
(a) Data Randomizer (b) Data Decoder
FIGURE 4-26: Logic Diagram for Digital Output Randomizer and Decoder.
4.12.11 OUTPUT DISABLE
The digital output can be disabled by setting
OUTPUT_MODE<1:0> = 00 in Address 0x62
(Register 5-20). All digital outputs are disabled,
including OVR, WCK, DCLK, etc.
4.12.12 OUTPUT TEST PATTERNS

To facilitate testing of the I/O interface, the device can
produce various predefined or user-defined patterns on
the digital outputs. See TEST_PATTERNS<2:0> in
Address 0x62 (Register 5-20) for the predefined test
patterns. For the user-defined patterns, Addresses
0x74 – 0x77 (Registers 5-29 – 5-32) can be
programmed using the SPI interface. When an output
test mode is enabled, the ADC’s analog section can still
be operational, but does not drive the digital outputs. The
outputs are driven only with the selected test pattern.

4.12.12.1 Pseudo-Random Number (PN) 4.13 System Calibration
Sequence Output
The built-in system calibration algorithm includes:
When TEST_PATTERNS<2:0> = 111, the device • Harmonic Distortion Correction (HDC)
outputs a pseudo-random number (PN) sequence
• DAC Noise Cancellation (DNC)
which is defined by the polynomial of degree 16, as
shown in Equation 4-11. Figure 4-27 shows the block • Dynamic Element Matching (DEM)
diagram of a 16-bit Linear Feedback Shift Register HDC and DNC correct the nonlinearity in the residue
(LFSR) for the PN sequence. amplifier and DAC, respectively. The system
EQUATION 4-11: POLYNOMIAL FOR PN calibration is performed by:
• Power-up calibration, which takes place during
4 13 15 16 the Power-on Reset sequence (requires 227 clock
P x= 1 + x + x + x + x cycles)
• Background calibration, which takes place during
The output PN[15:4] is directly applied to the output normal operation (per 230 clock cycles).
pins Qn[11:0]. In addition to the output at the Qn[11:0]
Background calibration time is invisible to the user,
pins, the two MSbs, PN[15] and PN[14], are copied to
and primarily affects the ADC's ability to track
the OVR and WCK pins, respectively. variations in ambient temperature.
The calibration status is monitored by the CAL pin or
PN[3] PN[12] PN[14] PN[15] the ADC_CAL_STAT bit in Address 0xC0 (Register 5-
Z-4 Z-9 Z-2 Z-1 80). See Address 0x07 (Register 5-5) and 0x1E
(Register 5-6) for time delay control of the auto-
calibration. Table 4-25 shows the calibration time for
various ADC core sample rates.
XOR
TABLE 4-25: CALIBRATION TIME VS. ADC
CORE SAMPLE RATE
FIGURE 4-27: Block Diagram of 16-Bit LFSR fS (Msps) 90 80 70 60 50
for Pseudo-Random Number (PN) Sequence for Power-Up 1.5 1.7 1.9 2.2 2.7
Output Test Pattern. Calibration Time1(sec)
Refresh Time (sec) of Back- 11.9 13.4 15.3 17.9 21.5
ground Calibration2
Note 1: It takes 227 clock cycles.
2: It takes place every 230 clock cycles by itself during
normal operation.
4.13.1 RESET COMMAND

Although the background calibration will track changes
in temperature or supply voltage, changes in clock
frequency or register configuration should be followed
by a recalibration of the ADC. This can be
accomplished via either the Hard or Soft Reset
command. The recalibration time is the same as the
power-up calibration time (227 clock cycles). Resetting
the device is highly recommended when exiting from
Shutdown or Standby mode after an extended amount
of time. During the reset, the device has the following
state:
• No ADC output
• No change in power-on condition of internal
reference
• Most of the internal clocks are not distributed
• Contents of internal user registers:
- Not affected by Soft Reset
- Reset to default values by Hardware Reset
• Current consumption of the digital section is
negligible, but no change in the analog section.

4.13.1.1 Hardware Reset This will perform a fast recalibration of the ADC. The
contents of the internal registers are not affected by the
A hard reset is triggered by toggling the RESET pin. On
Soft Reset.
the rising edge, all internal calibration registers and
user registers are initialized to their default states and In Standby mode, most of the internal circuitry is
recalibration of the ADC begins. The recalibration time disabled except for the reference, clock and SPI
is the same as the power-up calibration time. See interface. If the device has been in standby for an
Figure 2-6 for the timing details of the hardware extended period of time, the current calibration value
RESET pin. may not be accurate. Therefore, when exiting from
Standby mode, executing the device Soft Reset at the
4.13.1.2 Soft Reset same time is highly recommended.
The user can issue a Soft Reset command for a fast
recalibration of the ADC by setting the SOFT_RESET 4.15 AutoSync Mode: Synchronizing
bit to ‘0’ in Address 0x00 (Register 5-1). During Soft Multiple ADCs at the Same Clock
Reset, all internal calibration registers are initialized to using Master and Slave
their initial default states. User registers are unaffected. Configuration
When exiting the Soft Reset (changing from ‘0’ to ‘1’),
an automatic device calibration takes place. AutoSync allows multiple devices to sample analog
inputs synchronously at the same clock edge. Output
4.14 Power Dissipation and Power data is also presented synchronously if they are using
Savings the same digital signal post-processing options.
Figure 4-28 shows the system configuration using the
The power dissipation of the ADC core is proportional AutoSync feature. Three examples with timing
to the sample rate (fS). The digital power dissipation of diagram are shown in Figure 2-7 – Figure 2-9.
the CMOS outputs are determined primarily by the
Once the devices are synchronized, each device
strength of the digital drivers and the load condition on
performs internal calibration (TPCAL) before sending out
each output pin. The maximum digital load current
valid data output. Any ADC data output before the
(ILOAD) can be calculated as:
calibration is complete should be ignored.
EQUATION 4-12: CMOS OUTPUT LOAD Note that the calibration time varies slightly from device
to device, and the internal calibration status can be
CURRENT
monitored using the CAL pin or ADC_CAL_STAT bit in
I LOAD = DV DD1.8  f DCLK  N  CLOAD the Register Address 0xC0.
The valid synchronized output is available when all
Where:
devices complete their own internal calibration. For this
N = Number of bits reason, the user has two options for the synchronized
CLOAD = Capacitive load of output pin output: (a) monitor the calibration status of individual
devices and wait until all devices complete calibrations
or (b) use an external AND gate as shown in Figure 4-
The capacitive load presented at the output pins 27. Master and all Slave devices are synchronized when
needs to be minimized to minimize digital power the AND gate output toggles to “High”.
consumption. The output load current of the LVDS
The AutoSync feature can be used with the following
output is constant, since it is set by
steps:
LVDS_IMODE<2:0> in Address 0x63 (Register 5-21).
• Master device is selected by setting SLAVE pin to
4.14.1 POWER-SAVING MODES “GND”: SYNC pin becomes output pin.
This device has two power-saving modes: • Slave device is selected by setting SLAVE pin to
“High” (or tie to DVDD18): SYNC pin becomes
• Shutdown
input pin.
• Standby
• Feed the Master’s SYNC pin output to Slave’s
They are set by the SHUTDOWN and STANDBY bits in SYNC pin.
Address 0x00 (Register 5-1). • Use AutoSync mode using (a) Power-On Reset
In Shutdown mode, most of the internal circuitry, (Figure 2-7), (b) RESET Pin (Figure 2-8), or (c)
including the reference and clock, are turned off with SOFT RESET bit (Figure 2-9).
the exception of the SPI interface. During Shutdown,
the device consumes 23 mA (typical), primarily due to
digital leakage. When exiting from Shutdown, issuing a
Soft Reset at the same time is highly recommended.

DVDD18
Pull-up
DVDD18
(> 360)
SYNC Pin Output
SLAVE SYNC SYNC SLAVE
CAL CAL
MCP37D11-80 MCP37D11-80
Master Slave 1
DVDD18
SYNC SLAVE
CAL
MCP37D11-80
Slave 2
DVDD18
“High” when
SYNC SLAVE all devices
complete
CAL
calibration
MCP37D11-80
Slave N
AND Gate
Note: For optimum operation, it is highly recommended to use the same digital supply voltage (DVDD18,
DVDD12) (i.e., tie all DVDD12 together and tie all DVDD18 together) for Master and Slave devices.
FIGURE 4-28: Synchronizing Multiple ADCs Using AutoSync Feature.

5.0 SERIAL PERIPHERAL TABLE 5-1: SPI PIN FUNCTIONS
INTERFACE (SPI) Pin
Descriptions
The user can configure the ADC for specific functions Name
or optimized performance by setting the device’s Chip Select pin. SPI mode is initiated at
internal registers through the serial peripheral interface the falling edge. It needs to maintain
(SPI). The SPI communication uses three pins: CS, CS active-low for the entire period of the
SCLK and SDIO. Table 5-1 summarizes the SPI pin SPI communication. The device exits the
functions. The SCLK is used as a serial timing clock SPI communication at the rising edge.
and can be used up to 50 MHz. SDIO (Serial Data
Serial clock input pin.
Input/Output) is a dual-purpose pin that allows data to
be sent or read from the internal registers. The Chip • Writing to the device: Data is latched
Select pin (CS) enables SPI communication when SCLK at the rising edge of SCLK
active-low. The falling edge of CS followed by a rising • Reading from the device: Data is
edge of SCLK determines the start of the SPI latched at the falling edge of SCLK
communication. When CS is tied to high, SPI Serial data input/output pin. This pin is
communication is disabled and the SPI pins are placed initially an input pin (SDI) during the first
in high-impedance mode. The internal registers are 16-bit instruction header. After the
accessible by their address. instruction header, its I/O status can be
Figures 5-1 and 5-2 show the SPI data communication SDIO changed depending on the R/W bit:
protocols for this device with MSb-first and LSb-first • if R/W = 0: Data input pin (SDI) for
options, respectively. It consists of: writing
• 16-bit wide instruction header + Data byte 1 + • if R/W = 1: Data output pin (SDO) for
Data byte 2 + . . . + Data Byte N reading
Table 5-2 summarizes the bit functions. The R/W bit of
the instruction header indicates whether the command TABLE 5-2: SPI DATA PROTOCOL BIT
is a read (‘1’) or a write (‘0’): FUNCTIONS
• If the R/W bit is ‘1’, the SDIO pin changes Bit Name Descriptions
direction from an input (SDI) to an output (SDO)
R/W 1 = Read Mode
after the 16-bit wide instruction header.
0 = Write Mode
By selecting the R/W bit, the user can write the register
W1, W0 00 = Data for one register (1 byte)
or read back the register contents. The W1 and W2 bits
(Data 01 = Data for two registers (2 bytes)
in the instruction header indicate the number of data
Length) 10 = Data for three registers (3 bytes)
bytes to transmit or receive in the following data frame.
11 = Continuous reading or writing by
Bits A2 – A0 are the SPI device address bits. These clocking SCLK(1)
bits are used when multiple devices are used in the A2 - A0 Device SPI Address for multiple
same SPI bus. A2 is internally hardcoded to ‘0’. Bits A1 devices in SPI bus
and A0 correspond to the logic level of the ADR1 and A2: Internally hardcoded to ‘0’
ADR0 pins, respectively. A1: Logic level of ADR1 pin
A0: Logic level of ADR0 pin
The R9 – R0 bits represent the starting address of the
Configuration register to write or read. The data bytes R9 - R0 Address of starting register
following the instruction header are the register data. D7 - D0 Register data. MSb or LSb first,
All register data is eight bits wide. Data can be sent in depending on the LSb_FIRST bit
MSb-first mode (default) or in LSb-first mode, which is setting in 0x00
determined by the <LSb_ FIRST> bit setting in Address Note 1: The register address counter is incremented
0x00 (Register 5-1). In Write mode, the data is clocked by one per step. The counter does not
in at the rising edge of the SCLK. In the Read mode, the automatically reset to 0x00 after reaching the
data is clocked out at the falling edge of the SCLK. last address (0x15D). Be aware that the user
registers are not sequentially allocated.

CS
SCLK
SDIO
R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0
Address of Register Data 2 Register Data N

Starting Register Register Data of
Device Address
starting register
defined by R9 - R0
16-Bit Instruction Header Register Data
FIGURE 5-1: SPI Serial Data Communication Protocol with MSb-first. See Figures 2-3 and 2-4 for
Timing Specifications.
CS
SCLK
SDIO
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 A0 A1 A2 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D5 D6 D7
Address of Register Data 2 Register Data N

Starting Register
Register Data of
Device Address
starting register
defined by R9 - R0
16-Bit Instruction Header Register Data
FIGURE 5-2: SPI Serial Data Communication Protocol - with LSb-First. See Figures 2-3 and 2-4 for
Timing Specifications.
5.1 Register Initialization

Note 1: All address and bit locations that are not
The internal Configuration registers are initialized to included in the following register map
their default values under two different conditions: table should not be written or modified by
• After 220 clock cycles of delay from the Power-on the user.
Reset (POR). 2: Some registers include factory-controlled
• Resetting the hardware reset pin (RESET). bits (FCB). Do not overwrite these bits.
Figures 2-3 and 2-4 show the timing details.
5.2 Configuration Registers

The internal registers are mapped from Addresses
0x00 – 0x15D. These user registers are not
sequentially located. Some user Configuration
registers include factory-controlled bits. The factory-
controlled bits should not be overwritten by the user.
All user Configuration registers are read/write, except
for the last four registers, which are read-only. Each
register is made of an 8-bit-wide volatile memory, and
their default values are loaded during the power-up
sequence or by using the hardware RESET pin. All
registers are accessible by the SPI command using the
register address. Table 5-3 shows the user-register
memory map, and Registers 5-1 – 5-83 show the
details of the register bit functions.

 2020 Microchip Technology Inc.

TABLE 5-3: REGISTER MAP TABLE
Bits
Default
Addr. Register Name
Value
b7 b6 b5 b4 b3 b2 b1 b0
0x00 SPI Bit Ordering and ADC SHUTDOWN LSb-FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSb-FIRST SHUTDOWN 0x24
Mode Selection
1 = Shutdown 1 = LSb first 0 = Soft Reset 1 = Standby 1 = Standby 0=Soft Reset 1 = LSb first 1 = Shutdown
0 = MSb first 0 = MSb first
0x01 No. of Channel Selection and EN_DATCLK_IND FCB<3> = 0 SEL_NCH<2:0> FCB<2:0> = 111 0x0F
Independency Control of
Output Data and Clock Divider
0x02 Output Data and OUT_DATARATE<3:0> OUT_CLKRATE<3:0> 0x00
Clock Rate Control
0x04 SPI SDO Timing Control SDO_TIME FCB<6:0> = 0011111 0x9F
0x07 Output Randomizer POL_WCK EN_AUTOCAL_ FCB<4:0> = 10001 EN_OUT_ 0x62
and WCK Polarity Control TIMEDLY RANDOM
0x1E Auto-Calibration AUTOCAL_TIMEDLY<7:0> 0x80
Time Delay Control
0x52 DLL Control EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL 0x0A
0x53 Clock Source Selection FCB<6:4>= 010 CLK_SOURCE FCB<3:0>= 0101 0x45
0x54 PLL Reference Divider PLL_REFDIV<7:0> 0x00
0x55 PLL Output and PLL_OUTDIV<3:0> FCB<1:0> = 10 PLL_REFDIV<9:8> 0x48
Reference Divider
0x56 PLL Prescaler (LSb) PLL_PRE (LSB)<7:0> 0x78
0x57 PLL Prescaler (MSb) FCB<3:0> = 0100 PLL_PRE (MSB)<11:8> 0x40
0x58 PLL Charge Pump FCB<2:0> = 000 PLL_BIAS PLL_CHAGPUMP<3:0> 0x12
0x59 PLL Enable Control 1 U FCB<4:3> = 10 EN_PLL_REFDIV FCB<2:1> = 00 EN_PLL FCB<0> = 1 0x41
0x5A PLL Loop Filter Resistor U FCB<1:0> = 01 PLL_RES<4:0> 0x2F
0x5B PLL Loop Filter Cap3 U FCB<1:0> = 01 PLL_CAP3<4:0> 0x27
0x5C PLL Loop Filter Cap1 U FCB<1:0> = 01 PLL_CAP1<4:0> 0x27
0x5D PLL Loop Filter Cap2 U FCB<1:0> = 01 PLL_CAP2<4:0> 0x27
0x5F PLL Enable Control 2 FCB<5:2> = 1111 EN_PLL_OUT EN_PLL_BIAS FCB<1:0> = 01 0xF1
0x62 Output Data Format and U FCB<0> = 0 DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0> 0x10
Output Test Pattern
0x63 LVDS Output Load and Drive FCB<3:0> = 0000 LVDS_LOAD LVDS_IMODE<2:0> 0x01
Current Control
DS20006381A-page 73
0x64 Output Clock Phase EN_PHDLY DCLK_PHDLY_DEC<2:0> FCB<3:0> = 0011 0x03

Control when Decimation
Filter is used
0x65 LVDS Output Polarity Control POL_LVDS<5:0> NO EFFECT<1:0> 0x00
0x66 Digital Offset DIG_OFFSET_GLOBAL<7:0> 0x00
Correction - Lower Byte
Legend: U = Unimplemented bit, read as ‘0’ FCB = Factory-Controlled Bits. Do not program 1 = bit is set 0 = bit is cleared x = bit is unknown
2: Read-only register. Preprogrammed at the factory for internal use.
TABLE 5-3: REGISTER MAP TABLE (CONTINUED)
DS20006381A-paage 74

Bits
Default
Addr. Register Name
Value
b7 b6 b5 b4 b3 b2 b1 b0
0x67 Digital Offset DIG_OFFSET_GLOBAL<15:8> 0x00

Correction - Upper Byte
0x68 WCK and OVR FCB<5:2> = 0010 POL_WCK_OVR EN_WCK_OVR FCB<1:0> = 00 0x24
0x6B PLL Calibration FCB<6:2> = 00001 PLL_CAL_TRIG FCB<1:0> = 00 0x08
0x6D PLL Output and Output Clock U<1:0> EN_PLL_CLK FCB<1> = 0 DCLK_DLY_PLL<2:0> FCB<0> = 0 0x00
Phase
0x74 User-Defined Output PATTERN A<3:0> Do not use (Leave these bits as ‘0000’) 0x00
Pattern A - Lower Nibble
0x75 User-Defined Output PATTERN A<11:4> 0x00
Pattern A - Upper Byte
0x76 User-Defined Output PATTERN B<3:0> Do not use (Leave these bits as ‘0000’) 0x00
Pattern B - Lower Nibble
0x77 User-Defined Output PATTERN B<11:4> 0x00
Pattern B - Upper Byte
0x78 Noise-Shaping Requantizer NSR_RESET NSRA<6:0> 0x00
Channel A Filter
0x79 Dual-Channel DSPP Control EN_DSPP_2 NSRB<6:0> 0x00
0x7A FIRA0 Filter, FDR and NSR FCB<1> = 0 FIR_A<0> EN_FDR FCB<0> = 0 EN_NSRB_11 EN_NSRB_12 EN_NSRA_11 EN_NSRA_12 0x00
Control
0x7B FIR A Filter FIR_A<8:1> 0x00
0x7C FIR B Filter FIR_B<7:0> 0x00
0x7D Auto-Scan Channel Order - CH_ORDER<7:0> 0x78
Lower Byte
0x7E Auto-Scan Channel Order - CH_ORDER<15:8> 0xAC
Middle Byte
0x7F Auto-Scan Channel Order - CH_ORDER<23:16> 0x8E
Upper Byte
0x80 Digital Down-Converter HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1 0x00
Control 1
0x81 Digital Down-Converter FDR_BAND EN_DDC2 GAIN_HBF_DDC SEL_FDR EN_DSPP_8 8CH_CW GAIN_8CH<1:0> 0x00
Control 2
0x82 Numerically Controlled NCO_TUNE<7:0> 0x00
Oscillator (NCO) Tuning -
Lower Byte
Middle Lower Byte
Middle Upper Byte

Bits
Default
Addr. Register Name
Value
b7 b6 b5 b4 b3 b2 b1 b0

Upper Byte
0x86 CH0 NCO Phase Offset in CW CH0_NCO_PHASE<7:0> 0x00
or DDC Mode - Lower Byte
or DDC Mode - Upper Byte
0x8A CH2 NCO Phase Offset in CW CH2_NCO_PHASE<7:0> 0x00
0x8B CH2 NCO Phase Offset in CW CH2_NCO_PHASE<15:8> 0x00
0x8C CH3 NCO Phase Offset in CW CH3_NCO_PHASE<7:0> 0x00
0x8D CH3 NCO Phase Offset in CW CH3_NCO_PHASE<15:8> 0x00
0x8E CH4 NCO Phase Offset in CW CH4_NCO_PHASE<7:0> 0x00
0x8F CH4 NCO Phase Offset in CW CH4_NCO_PHASE<15:8> 0x00
DS20006381A-page 75
0x96 CH0 Digital Gain CH0_DIG_GAIN<7:0> 0x3C

DS20006381A-paage 76

Bits
Default
Addr. Register Name
Value
b7 b6 b5 b4 b3 b2 b1 b0
0x9A CH4 Digital Gain CH4_DIG_GAIN<7:0> 0x3C

0x9B CH5 Digital Gain CH5_DIG_GAIN<7:0> 0x3C
0x9C CH6 Digital Gain CH6_DIG_GAIN<7:0> 0x3C
0x9D CH7 Digital Gain CH7_DIG_GAIN<7:0> 0x3C
0x9E CH0 Digital Offset CH0_DIG_OFFSET<7:0> 0x00
0x9F CH1 Digital Offset CH1_DIG_OFFSET<7:0> 0x00
0xA0 CH2 Digital Offset CH2_DIG_OFFSET<7:0> 0x00
0xA7 Digital Offset Weight Control FCB<5:3> = 010 DIG_OFFSET_WEIGHT<1:0> FCB<2:0> = 111 0x47
0xC0 Calibration Status ADC_CAL_STAT FCB<6:0> = 000-0000 ─
Indication (Read only)
0xD1 PLL Calibration Status FCB<4:3> = xx PLL_CAL_STAT FCB<2:1> = xx PLL_VCOL_STAT PLL_VCOH_STAT FCB<0> = x ─
and PLL Drift Status Indication
(Read only)
0x15C CHIP ID - Lower Byte(2) CHIP_ID<7:0> ─
(Read only)
0x15D CHIP ID - Upper Byte(2) CHIP_ID<15:8> ─
(Read only)
REGISTER 5-1: ADDRESS 0X00 – SPI BIT ORDERING AND ADC MODE SELECTION(1)
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
SHUTDOWN LSb_FIRST SOFT_RESET STANDBY STANDBY SOFT_RESET LSb_FIRST SHUTDOWN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SHUTDOWN: Shutdown mode setting for power-saving(2)

1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
bit 6 LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 5 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 4 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 3 STANDBY: Send the device into a power-saving Standby mode(4)
1 = ADC in Standby mode
0 = Not in Standby mode (Default)
bit 2 SOFT_RESET: Soft Reset control bit(3)
1 = Not in Soft Reset mode (Default)
0 = ADC in Soft Reset
bit 1 LSb_FIRST: Select SPI communication bit order
1 = Start SPI communication with LSb first
0 = Start SPI communication with MSb first (Default)
bit 0 SHUTDOWN: Shutdown mode setting for power-saving(2)
1 = ADC in Shutdown mode
0 = Not in Shutdown mode (Default)
Note 1: Upper and lower nibble are mirrored, which makes the MSb- or LSb-first mode interchangeable. The lower nibble (bit <3:0>)
has a higher priority when the mirrored bits have different values.
2: During Shutdown mode, most of the internal circuits including the reference and clock are turned-off except for the SPI
interface. When exiting from Shutdown (changing from ‘1’ to ‘0’), executing the device Soft Reset simultaneously is highly
recommended for a fast recalibration of the ADC. The internal user registers are not affected.
3: This bit forces the device into Soft Reset mode, which initializes the internal calibration registers to their initial default states.
The user-registers are not affected. When exiting Soft Reset mode (changing from ‘0’ to ‘1’), the device performs an automatic
device calibration including PLL calibration if PLL is enabled. DLL is reset if enabled. During Soft Reset, the device has the
following states:
- no ADC output
- no change in power-on condition of internal reference
- most of the internal clocks are not distributed
- power consumption: (a) digital section - negligible, (b) analog section - no change
4: During Standby mode, most of the internal circuits are turned off except for the reference, clock and SPI interface. When exiting
from Standby mode (changing from ‘1’ to ‘0’) after an extended amount of time, executing Soft Reset simultaneously is highly
recommended. The internal user registers are not affected.

REGISTER 5-2: ADDRESS 0X01 – NUMBER OF CHANNELS, INDEPENDENCY CONTROL OF OUTPUT
DATA AND CLOCK DIVIDER

EN_DATCLK_IND FCB<3> SEL_NCH<2:0> FCB<2:0>
bit 7 bit 0
Legend:
bit 7 EN_DATCLK_IND: Enable data and clock divider independently(1)

1 = Enabled
0 = Disabled (Default)
bit 6 FCB<3>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
bit 5-3 SEL_NCH<2:0>: Select the total number of input channels to be used(2)
111 = 7 inputs
110 = 6 inputs
101 = 5 inputs
100 = 4 inputs
011 = 3 inputs
010 = 2 inputs
001 = 1 input (Default)
000 = 8 inputs
bit 2-0 FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1: EN_DATCLK_IND = 1 enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).
2: See Addresses 0x7D – 0x7F (Registers 5-38 – 5-40) for selecting the input channel order.

REGISTER 5-3: ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)

OUT_DATARATE<3:0> OUT_CLKRATE<3:0>
bit 7 bit 0
Legend:
bit 7-4 OUT_DATARATE<3:0>: Output data rate control bits

1111 = Output data is all 0’s
1100 = Internal test only(2)
1001 = Full speed divided by 512
0000 = Full-speed rate (Default)
bit 3-0 OUT_CLKRATE<3:0>: Output clock rate control bits(3,4)
1111 = Full-speed rate
1110 = No clock output
0000 = No clock output (Default)
Note 1: This register should be used to realign the output data and clock when the decimation or digital down-conversion (DDC) option
is used.
2: 1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed with differ-
ent settings, the outputs will be in an undefined state.
3: Bits <3:0> become active if EN_DATCLK_IND = 1 in Address 0x01 (Register 5-2).
4: When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.

REGISTER 5-4: ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL

SDO_TIME FCB<6:0>
bit 7 bit 0
Legend:
bit 7 SDO_TIME: SPI SDO output timing control bit

1 = SDO output at the falling edge of clock (Default)
0 = SDO output at the rising edge of clock
REGISTER 5-5: ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL

POL_WCK EN_AUTOCAL_- FCB<4:0> EN_OUT_RANDOM
TIMEDLY
bit 7 bit 0
Legend:
bit 7 POL_WCK: WCK polarity control bit(1)

1 = Inverted
0 = Not inverted (Default)
bit 6 EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit(2)
1 = Enabled (Default)
0 = Disabled
bit 0 EN_OUT_RANDOM: Output randomizer control bit
1 = Enabled: ADC data output is randomized
Note 1: See Address 0x68 (Register 5-26) for WCK/OVR pair control.
2: This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).

REGISTER 5-6: ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)

AUTOCAL_TIMEDLY<7:0>
bit 7 bit 0
Legend:
bit 7-0 AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits

1111-1111 = Maximum value
•••
1000-0000 = (Default)
•••
0000-0000 = Minimum value
Note 1: EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay
before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.
REGISTER 5-7: ADDRESS 0X52 – DLL CONTROL

EN_DUTY DCLK_PHDLY_DLL<2:0> EN_DLL_DCLK EN_DLL EN_CLK RESET_DLL
bit 7 bit 0
Legend:
bit 7 EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock
1 = Correction is ON
0 = Correction is OFF (Default)
bit 6-4 DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL(1)
111 = +315° phase-shifted from default
011 = +135 phase-shifted from default
000 = (Default)
bit 3 EN_DLL_DCLK: Enable DLL digital clock output
0 = Disabled: DLL digital clock is turned off. ADC output is not available when DLL is used.
bit 2 EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock.
1 = Enabled
0 = Disabled. DLL block is disabled (Default)
bit 1 EN_CLK: Enable clock input buffer
1 = Enabled (Default).
0 = Disabled. No clock is available to the internal circuits, ADC output is not available.
bit 0 RESET_DLL: DLL circuit reset control(2)
1 = DLL is active
0 = DLL circuit is held in reset (Default)
Note 1: These bits have an effect only if EN_PHDLY = 1 and decimation is not used.
2: DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.

REGISTER 5-8: ADDRESS 0X53 – CLOCK SOURCE SELECTION

FCB<6:4> CLK_SOURCE FCB<3:0>
bit 7 bit 0
Legend:
bit 4 CLK_SOURCE: Select internal timing source
1 = PLL output is selected as timing source
0 = External clock input is selected as timing source (Default)
REGISTER 5-9: ADDRESS 0X54 – PLL REFERENCE DIVIDER

PLL_REFDIV<7:0>
bit 7 bit 0
Legend:
bit 7-0 PLL_REFDIV<7:0>: PLL Reference clock divider control bits(1)

1111-1111 = PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)
•••
0000-0010 = Do not use (No effect)
0000-0000 = PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)
Note 1: PLL_REFDIV is a 10-bit wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Table 5-4 for PLL_REF-
DIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock input at the CLK
pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not supported. EN_PLL_REFDIV in
Address 0x59 (Register 5-14) must be set.

REGISTER 5-10: ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER

PLL_OUTDIV<3:0> FCB<1:0> PLL_REFDIV<9:8>
bit 7 bit 0
Legend:
bit 7-4 PLL_OUTDIV<3:0>: PLL output divider control bits(1)

1111 = PLL output divided by 15
•••
0100 = PLL output divided by 4 (Default)
0000 = PLL output not divided
bit 1-0 PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>(2)
00 = see Table 5-4. (Default)
Note 1: PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.
2: See Address 0x54 (Register 5-9) and Table 5-4 for PLL_REFDIV<9:0> settings. EN_PLL_REFDIV in Address 0x59
(Register 5-14) must be set.
TABLE 5-4: EXAMPLE – PLL REFERENCE DIVIDER BIT SETTINGS VS. PLL REFERENCE INPUT
FREQUENCY
PLL_REFDIV<9:0> PLL Reference Frequency
11-1111-1111 Reference frequency divided by 1023
─ ─
00-0000-0010 Do not use (not supported)

REGISTER 5-11: ADDRESS 0X56 – PLL PRESCALER (LSB)

PLL_PRE<7:0>
bit 7 bit 0
Legend:
bit 7-0 PLL_PRE<7:0>: PLL prescaler selection(1)

1111-1111 = VCO clock divided by 255 (if PLL_PRE<11:8> = 0000)
•••
0111-1000 = VCO clock divided by 120 (if PLL_PRE<11:8> = 0000) (Default)
•••
0000-0000 = VCO clock not divided (if PLL_PRE<11:8> = 0000)
Note 1: PLL_PRE is a 12-bit-wide setting. The upper four bits (PLL_PRE<11:8>) are defined in Address 0x57. See Table 5-5 for the
PLL_PRE<11:0> settings. The PLL Prescaler is used to divide down the VCO output clock in the PLL phase-frequency detector
loop circuit.
REGISTER 5-12: ADDRESS 0X57 – PLL PRESCALER (MSB)

FCB<3:0> PLL_PRE<11:8>
bit 7 bit 0
Legend:
bit 3-0 PLL_PRE<11:8>: PLL prescaler selection(1)
1111 = 212 - 1 (max), if PLL_PRE<7:0> = 0xFF
•••
0000 = Default)
Note 1: PLL_PRE is a 12-bit-wide setting. See the lower eight bit settings (PLL_PRE<7:0>) in Address 0x56 (Register 5-11). See
Table 5-5 for the PLL_PRE<11:0> settings for PLL feedback frequency.
TABLE 5-5: Example: PLL Prescaler Bit Settings and PLL Feedback Frequency
PLL_PRE<11:0> PLL Feedback Frequency
1111-1111-1111 VCO clock divided by 4095 (212 - 1)

1111-1111-1110 VCO clock divided by 4094 (212 - 2)
─ ─
0000-0000-0011 VCO clock divided by 3

REGISTER 5-13: ADDRESS 0X58 – PLL CHARGE-PUMP

FCB<2:0>: PLL_BIAS PLL_CHAGPUMP<3:0>
bit 7 bit 0
Legend:
bit 4 PLL_BIAS: PLL charge-pump bias source selection bit
1 = Self-biasing coming from AVDD (Default)
0 = Bandgap voltage from the reference generator (1.2V)
bit 3-0 PLL_CHAGPUMP<3:0>: PLL charge pump bias current control bits(1)
1111 = Maximum current
•••
0010 = (Default)
•••
0000 = Minimum current
Note 1: PLL_CHAGPUMP<3:0> should be set based on the phase detector comparison frequency. The bias current amplitude
increases linearly with increasing the bit setting values. The increase is from approximately 25 µA to 375 µA, 25 µA per step.
See Section 4.7.2.1, "PLL Output Frequency and Output Control Parameters" for more details of the PLL block.
REGISTER 5-14: ADDRESS 0X59 – PLL ENABLE CONTROL 1
U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

— FCB<4:3> EN_PLL_REFDIV FCB<2:1> EN_PLL FCB<0>
bit 7 bit 0
Legend:
bit 7 Unimplemented: Not used.

bit 4 EN_PLL_REFDIV: Enable PLL Reference Divider (PLL_REFDIV<9:0>).
1 = Enabled
0 = Reference divider is bypassed (Default)
bit 1 EN_PLL: Enable PLL circuit.
1 = Enabled

REGISTER 5-15: ADDRESS 0X5A – PLL LOOP FILTER RESISTOR

— FCB<1:0> PLL_RES<4:0>
bit 7 bit 0
Legend:

bit 4-0 PLL_RES<4:0>: Resistor value selection bits for PLL loop filter(1)
11111 = Maximum value
•••
01111= (Default)
•••
00000 = Minimum value
Note 1: PLL_RES<4:0> should be set based on the phase detector comparison frequency. The resistor value increases linearly with the
bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.7, "ADC Clock Selection".
REGISTER 5-16: ADDRESS 0X5B – PLL LOOP FILTER CAP3

— FCB<1:0> PLL_CAP3<4:0>
bit 7 bit 0
Legend:

bit 4-0 PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter(1)
•••
00111= (Default)
•••
Note 1: This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0>. The capacitor value increases linearly with the
bit settings, from minimum to maximum values. This setting should be set based on the phase detector comparison frequency.

REGISTER 5-17: ADDRESS 0X5C – PLL LOOP FILTER CAP1

— FCB<1:0> PLL_CAP1<4:0>
bit 7 bit 0
Legend:

•••
00111= (Default)
•••
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with the shunt resistor which is defined by
the PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting
should be set based on the phase detector comparison frequency.
REGISTER 5-18: ADDRESS 0X5D – PLL LOOP FILTER CAP2

— FCB<1:0> PLL_CAP2<4:0>
bit 7 bit 0
Legend:

•••
00111= (Default)
•••
Note 1: This capacitor is located between the charge pump output and ground, and in parallel with CAP1 which is defined by the PLL_-
CAP1<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting should
be set based on the phase detector comparison frequency.

REGISTER 5-19: ADDRESS 0X5F – PLL ENABLE CONTROL 2(1)

FCB<5:2> EN_PLL_OUT EN_PLL_BIAS FCB<1:0>
bit 7 bit 0
Legend:
bit 7-4 FCB<5:2>: Factory-Controlled Bits. This is not for the user. Do not change the default settings.
bit 3 EN_PLL_OUT: Enable PLL output.
1 = Enabled
bit 2 EN_PLL_BIAS: Enable PLL bias
1 = Enabled
Note 1: To enable PLL output, EN_PLL_OUT, EN_PLL_BIAS and EN_PLL in Address 0x59 (Register 5-14) must be set.

REGISTER 5-20: ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN

— FCB DATA_FORMAT OUTPUT_MODE<1:0> TEST_PATTERNS<2:0>
bit 7 bit 0
Legend:

bit 6 FCB: Factory-controlled bit. This is not for the user. Do not change default setting.
bit 5 DATA_FORMAT: Output data format selection
1 = Offset binary (unsigned)
0 = Two’s complement (Default)
bit 4-3 OUTPUT_MODE<1:0>: Output mode selection(1)
11 = Do not use. Output is undefined
10 = Select DDR LVDS output mode with even bit first(2)(Default)
01 = Select CMOS output mode
00 = Output disabled
bit 2-0 TEST_PATTERNS<2:0>: Test output data pattern selection(3)
111 = Output data is pseudo-random number (PN) sequence(4)
110 = Sync Pattern for LVDS output
Output: '11111111 0000'
101 = Alternating Sequence for LVDS mode
Output: ‘01010101 1010’
100 = Alternating Sequence for CMOS mode
Output: ‘11111111 1111’ alternating with ‘00000000 0000’
011 = Alternating Sequence for CMOS
Output: ‘01010101 0101’ alternating with ‘10101010 1010’
010 = Ramp Pattern: Output (Q0) is incremented by1 LSB per 64 clock cycles(5)
001 = Double Custom Patterns
Output: Alternating custom pattern A (see Addresses 0X74 - 0X75 – Registers 5-29 –5-30)
and custom pattern B (see Address 0X76 - 0X77 – Registers 5-31 – 5-32)(6)
000 = Normal Operation. Output: ADC data (Default)
Note 1: See Figures 2-1 –2-2 for the timing diagrams.
2: Rising edge: Q10, Q8, Q6, Q4, Q2, Q0.
Falling edge: Q11, Q9, Q7, Q5, Q3, Q1.
3: See Section 4.12.12 “Output Test Patterns” for more details.
(a) In LVDS mode: only the active pins (per register settings) are active. Inactive output pins are High Z state.
(b) In CMOS mode: all data output pins (Q11-Q0), output test pins (TP), OVR and WCK pins are active,
even if they are disabled by register settings.
Since the output test pins (TP) can toggle during this test, the output test pins can draw extra current if
they are connected to the supply pin or ground. To avoid the extra current draws, always leave the TP
pins floating (not connected).
4: Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR). See
Section 4.12.12.1, "Pseudo-Random Number (PN) Sequence Output" for more details.
5: OVR and WCK bits are incremented by 1 per 219 and 218 clock cycles, respectively.
6: Pattern A<11:0> and B<11:0> are applied to Q<11:0>. Q11 = OVR, Q10 = WCK.

REGISTER 5-21: ADDRESS 0X63 – LVDS OUTPUT LOAD AND DRIVER CURRENT CONTROL
FCB<3:0> LVDS_LOAD LVDS_IMODE<2:0>
bit 7 bit 0
Legend:
bit 7-4 FCB<3:0>: Factory-controlled bits. This is not for the user. Do not change default setting.
bit 3 LVDS_LOAD: Internal LVDS load termination
1 = Enable internal load termination
0 = Disable internal load termination (Default)
bit 2-0 LVDS_IMODE<2:0>: LVDS driver current control bits
111 = 7.2 mA
011 = 5.4 mA
001 = 3.5 mA (Default)
000 = 1.8 mA
Do not use the following settings (1):
110, 101, 100, 010
Note 1: Do not use these settings. These settings can result in unknown output currents.

REGISTER 5-22: ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS USED

EN_PHDLY DCLK_PHDLY_DEC<2:0> FCB<3:0>
bit 7 bit 0
Legend:
bit 7 EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.
1 = Enabled
bit 6-4 DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used(2)
111 = +315° phase-shifted from default(2)
000 = Default(3)
Note 1: These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.
2: Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0, only 4-
phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C (Registers 5-35 – 5-37).
See Addresses 0x6D and 0x52 (Registers 5-28 and 5-7) for DCLK phase shift for other modes.
3: The phase delay for all other settings is referenced to this default phase.
REGISTER 5-23: ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL

POL_LVDS<5:0> NO EFFECT<1:0>
bit 7 bit 0
Legend:
bit 7-2 POL_LVDS<5:0>: Control polarity of LVDS data pairs (Q5+/Q5- – Q0+/Q0-)
111111 = Invert all LVDS pairs
111110 = Invert all LVDS pairs except the LSb pair
•••
100000 = Invert MSb LVDS pair
•••
000001 = Invert LSb LVDS pair
000000 = No inversion of LVDS bit pairs (Default)
bit 1-0 NO EFFECT<1:0>: No effect bits.

REGISTER 5-24: ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)

DIG_OFFSET_GLOBAL<7:0>
bit 7 bit 0
Legend:
bit 7-0 DIG_OFFSET_GLOBAL<7:0>: Lower byte of DIG_OFFSET_GLOBAL<15:0> for all channels(-)

0000-0000 = Default
-Offset is added to the ADC output. Setting is two’s complement using two combined registers (16-bits wide).
Setting range: (-215 to 215 - 1) x 0.125 LSb(s)
REGISTER 5-25: ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)

DIG_OFFSET_GLOBAL<15:8>
bit 7 bit 0
Legend:
bit 7-0 DIG_OFFSET_GLOBAL<15:8>: Upper byte of DIG_OFFSET_GLOBAL<15:0> for all channels(1)

0000-0000 = Default
Note 1: See Note - in Address 0x66 (Register 5-24)
REGISTER 5-26: ADDRESS 0X68 – WCK AND OVR BIT CONTROL

FCB<5:2> POL_WCK_OVR EN_WCK_OVR FCB<1:0>
bit 7 bit 0
Legend:
bit 7-4 FCB<5:2>: Factory-controlled bits. This is not for the user. Do not change default settings.
bit 3 POL_WCK_OVR: Polarity control for WCK and OVR bit pair in LVDS mode
1 = Inverted
0 = Not inverted (Default)
bit 2 EN_WCK_OVR: Enable WCK and OVR output bit pair
0 = Disabled
bit 1-0 FCB<1:0>: Factory-controlled bits. This is not for the user. Do not change default settings.

REGISTER 5-27: ADDRESS 0X6B – PLL CALIBRATION

FCB<6:2> PLL_CAL_TRIG FCB<1:0>
bit 7 bit 0
Legend:
bit 2 PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition(1)
Toggle from “1” to “0”, or “0” to “1” = Start PLL calibration
bit 1-0 FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not program.
Note 1: See PLL_CAL_STAT in Address 0xD1 (Register 5-81) for calibration status indication.
REGISTER 5-28: ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
─ EN_PLL_CLK FCB<1> DCLK_DLY_PLL<2:0> FCB<0>
bit 7 bit 0
Legend:
bit 7-6 Unimplemented: Not used

bit 5 EN_PLL_CLK: Enable PLL output clock
1 = PLL output clock is enabled to the ADC core
0 = PLL clock output is disabled (Default)
bit 4 FCB<1>: Factory-Controlled Bit. This is not for the user. Do not change default settings.
bit 3-1 DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output(2)
111 = Delay of 15 cycles
110 = Delay of 14 cycles
•••
001 = Delay of one cycle
000 = No delay (Default)
Note 1: This register has effect only when the PLL clock is selected by the CLK_SOURCE bit in Address 0x53
(Register 5-8) and PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14).
2: This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is
used as the clock source and the decimation is not used.

REGISTER 5-29: ADDRESS 0X74 – USER-DEFINED OUTPUT PATTERN A (LOWER NIBBLE)

PATTERN_A<3:0> Do not use (Leave these bits as ‘0000’)
bit 7 bit 0
Legend:
bit 7-4 PATTERN_A<3:0>: Lower nibble of PATTERN_A<11:0>(1)

bit 3-0 Do not use: Leave these bits to default settings (‘0000’)(2)
Note 1: See PATTERN_A<11:4> in Address 0x75 (Register 5-30) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2: The output from these bit settings is on “Unused Output Pattern Test Pins”, which are recommended to be not connected to the
host device. Therefore, the effect of these bit settings is not monitored. Leave these bits as default settings (‘0000’) all the time.
REGISTER 5-30: ADDRESS 0X75 – USER-DEFINED OUTPUT PATTERN A (UPPER BYTE)

PATTERN_A<11:4>
bit 7 bit 0
Legend:
bit 7-0 PATTERN_A<11:4>: Upper byte of PATTERN_A<11:0>(1)

Note 1: See PATTERN_A<3:0> in Address 0x74 (Register 5-29) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-31: ADDRESS 0X76 – USER-DEFINED OUTPUT PATTERN B (LOWER NIBBLE)

PATTERN_B<3:0> Do not use (Leave these bits as ‘0000’)
bit 7 bit 0
Legend:
bit 7-4 PATTERN_B<3:0>: Lower nibble of PATTERN_B<11:0>(1)

bit 3-0 Do not use: Leave these bits to default settings (‘0000’)(2)
Note 1: See PATTERN_B<11:4> in Address 0x77 (Register 5-32) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2: The output from these bit settings is on “Unused Output Pattern Test Pins”, which are recommended to be not connected to the
host device. Therefore, the effect of these bit settings is not monitored. Leave these bits as default settings (‘0000’) all the time.

REGISTER 5-32: ADDRESS 0X77 – USER-DEFINED OUTPUT PATTERN B (UPPER BYTE)
PATTERN_B<11:4>
bit 7 bit 0
Legend:
bit 7-0 PATTERN_B<11:4>: Upper byte of PATTERN_B<11:0>(1)

Note 1: See PATTERN_B<3:0> in Address 0x76 (Register 5-31) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-33: ADDRESS 0X78 – NOISE-SHAPING REQUANTIZER RESET CONTROL AND CHANNEL A
FILTER (NSRA)(1)
NSR_RESET NSRA<6:0>
bit 7 bit 0
Legend:
bit 7 NSR_RESET: Toggle of this bit causes a reset of the NSRA and NSRB state.
- Toggle from ‘1’ to ‘0’ or from ‘0’ to ‘1’ = Reset of NSRA and NSRB(2)
- Otherwise = No effect (Default)
bit 6-0 NSRA<6:0>: NSRA filter settings. See Tables 4-13 to 4-14 for the NSR filter settings(3)
000-0000 = (Default)
Note 1: This register is used for single- and dual-channel modes only.
2: The NSR filter will be also automatically reset if the filter setting is changed.
3: In dual-channel mode, NSRA<6:0> is used for channel A.
REGISTER 5-34: ADDRESS 0X79 – DUAL-CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL

AND NOISE-SHAPING REQUANTIZER CHANNEL B FILTER (NSRB)(1)
EN_DSPP_2 NSRB<6:0>
bit 7 bit 0
Legend:
bit 7 EN_DSPP_2: Enable digital post-processing functions for dual-channel operations

1 = Enabled
bit 6-0 NSRB<6:0>: NSRB filter settings. See Tables 4-13 to 4-14 for the NSR filter settings(2)
000-0000 = (Default)
Note 1: This register is used for single- and dual-channel modes only.
2: In dual-channel mode, NSRB<6:0> is used for channel B.

REGISTER 5-35: ADDRESS 0X7A – FIR_A0 FILTER, FDR AND NSR CONTROL(1)

FCB<1> FIR_A<0> EN_FDR FCB<0> EN_NSRB_11 EN_NSRB_12 EN_NSRA_11 EN_NSRA_12
bit 7 bit 0
Legend:
bit 6 FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A) in single-channel mode(2)
1 = Enabled
bit 5 EN_FDR: Enable fractional delay recovery (FDR) option
1 = Enabled (with delay of 59 clock cycles).
bit 3 EN_NSRB_11: Enable 11-bit noise-shaping requantizer for Channel B
1 = Enabled
bit 2 EN_NSRB_12: Enable 12-bit noise-shaping requantizer for Channel B
1 = Enabled
bit 1 EN_NSRA_11: Enable 11-bit noise-shaping requantizer for Channel A
1 = Enabled
bit 0 EN_NSRA_12: Enable 12-bit noise-shaping requantizer for Channel A
1 = Enabled
Note 1: This register is used only for single- and dual-channel modes.
2: This is the LSb of the FIR A filter settings. For the first 2x decimation, set FIR_A<0> = 1 for single-channel operation, and
FIR_A<0> = 0 for dual-channel operation. See Address 0x7B (Register 5-36) for FIR_A<8:1> settings.

REGISTER 5-36: ADDRESS 0X7B – FIR A FILTER(1,5)

FIR_A<8:1>
bit 7 bit 0
Legend:
bit 7-0 FIR_A<8:1>: Decimation Filter FIR A settings for Channel A (or I)(2)
Single-Channel Mode:(3)
FIR_A<8:0> =
1-1111-1111 = Stage 1 - 9 filters (decimation rate: 512)
0-1111-1111 = Stage 1 - 8 filters
0-0111-1111 = Stage 1 - 7 filters
0-0011-1111 = Stage 1 - 6 filters
0-0001-1111 = Stage 1 - 5 filters
0-0000-1111 = Stage 1 - 4 filters
0-0000-0111 = Stage 1 - 3 filters (decimation rate = 8)
0-0000-0011 = Stage 1 - 2 filters (decimation rate = 4)
0-0000-0001 = Stage 1 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Dual-Channel Mode:(4)
FIR_A<8:0> =
1-1111-1110 = Stage 2 - 9 filters (decimation rate: 256)
0-1111-1110 = Stage 2 - 8 filters
0-0111-1110 = Stage 2 - 7 filters
0-0011-1110 = Stage 2 - 6 filters
0-0001-1110 = Stage 2 - 5 filters
0-0000-1110 = Stage 2 - 4 filters
0-0000-0110 = Stage 2 - 3 filters
0-0000-0010 = Stage 2 filter (decimation rate = 2)
0-0000-0000 = Disabled all FIR A filters. (Default)
Note 1: This register is used only for single and dual-channel modes. The register values are thermometer encoded.
2: FIR_A<0> is placed in Address 0x7A (Register 5-35).
3: In single-channel mode, the 1st stage filter is selected by FIR_A<0> = 1 in Address 0x7A (Register 5-35).
4: In dual-channel mode, the 1st stage filter is disabled by setting FIR_A<0> = 0 in Address 0x7A.
5: SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation rate for the single-channel mode is 512, and 256 for the dual-channel mode.

REGISTER 5-37: ADDRESS 0X7C – FIR B FILTER(1,2)

FIR_B<7:0>
bit 7 bit 0
Legend:
bit 7-0 FIR_B<7:0>:Decimation Filter FIR B settings for Channel B (or Q)(3)
1111-1111 = Stage 2 - 9 filters (decimation rate = 256)
0111-1111 = Stage 2 - 8 filters
0011-1111 = Stage 2 - 7 filters
0001-1111 = Stage 2 - 6 filters
0000-1111 = Stage 2 - 5 filters
0000-0111 = Stage 2 - 4 filters
0000-0011 = Stage 2 - 3 filters
0000-0001 = Stage 2 filter (decimation rate = 2)
0000-0000 = Disabled all FIR B Filters. (Default)
Note 1: This register is used for the dual-channel mode only. The register values are thermometer encoded.
2: EN_DSPP_2 bit in Address 0x79 (Register 5-34) must be set when using decimation in dual-channel mode.
3: SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation factor for the dual-channel mode is 256.
REGISTER 5-38: ADDRESS 0X7D – AUTO-SCAN CHANNEL ORDER (LOWER BYTE)

CH_ORDER<7:0>
bit 7 bit 0
Legend:
bit 7-0 CH_ORDER<7:0>: Lower byte of CH_ORDER<31:0>(1)

0111-1000 = Default
Note 1: See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-39: ADDRESS 0X7E – AUTO-SCAN CHANNEL ORDER (MIDDLE BYTE)

CH_ORDER<15:8>
bit 7 bit 0
Legend:
bit 7-0 CH_ORDER<15:8>: Middle byte of CH_ORDER<31:0>(1)

1010-1100 = Default
to be selected.

REGISTER 5-40: ADDRESS 0X7F – AUTO-SCAN CHANNEL ORDER (UPPER BYTE)

CH_ORDER<23:16>
bit 7 bit 0
Legend:
bit 7-0 CH_ORDER<23:16>: Upper byte of CH_ORDER<31:0>(1)

1000-1110 = Default
to be selected.
REGISTER 5-41: ADDRESS 0X80 – DIGITAL DOWN-CONVETER CONTROL 1(1)

HBFILTER_B HBFILTER_A EN_NCO EN_AMPDITH EN_PHSDITH EN_LFSR EN_DDC_FS/8 EN_DDC1
bit 7 bit 0
Legend:
bit 7 HBFILTER_B: Select half-bandwidth filter at DDC output of channel B in dual-channel mode(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 6 HBFILTER_A: Select half-bandwidth filter at DDC output of channel A(2)
1 = Select High-Pass filter at DDC output
0 = Select Low-Pass filter at DDC output (Default)
bit 5 EN_NCO: Enable NCO of DDC1
1 = Enabled
bit 4 EN_AMPDITH: Enable amplitude dithering for NCO(3, 4)
1 = Enabled
bit 3 EN_PHSDITH: Enable phase dithering for NCO(3, 4)
1 = Enabled
bit 2 EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO
1 = Enabled
bit 1 EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around fS/8/DER(5)
1 = Enabled
bit 0 EN_DDC1: Enable digital down converter 1 (DDC1)
1 = Enabled(6)
Note 1: This register is used for single-, dual- and octal-channel modes when CW feature is enabled (8CH_CW = 1).
2: This filter includes a decimation of 2.
-Single-channel mode: HBFILTER_A is used.
-Dual-channel mode: Both HBFILTER_A and HBFILTER_B are used.
3: This requires the LFSR to be enabled: EN_LFSR=1
4: EN_AMPDITH = 1 and EN_PHSDITH = 1 are recommended for the best performance.
5: DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data.
6: DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together.

REGISTER 5-42: ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2

FDR_BAND EN_DDC2 GAIN_HBF_DDC SEL_FDR EN_DSPP_8 8CH_CW GAIN_8CH<1:0>
bit 7 bit 0
Legend:
bit 7 FDR_BAND: Select 1st or 2nd Nyquist band

1 = 2nd Nyquist band
0 = 1st Nyquist band (Default)
bit 6 EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC.
1 = Enabled
bit 5 GAIN_HBF_DDC: Gain selection for the output of the digital half-band filter (HBF) in DDC(1)
1 = x2
0 = x1 (Default)
bit 4 SEL_FDR: Select fractional delay recovery (FDR)
1 = FDR for 8-channel
0 = FDR for dual-channel (Default)
bit 3 EN_DSPP_8: Enable digital signal post-processing (DSPP) features for 8-channel operation(2)
1 = Enabled
bit 2 8CH_CW: Enable CW mode in octal-channel mode(2, 3)
1 = Enabled
bit 1-0 GAIN_8CH<1:0>: Select gain factor for CW signal in octal-channel modes.
11 = x8, 10 = x4, 01 = x2, 00 = x1 (Default)
Note 1: See Section 4.8.3, "Decimation Filters".
2: By enabling this bit, the phase offset corrections in Addresses 0x086 – 0x095 (Registers 5-47 – 5-62) are also enabled.
EN_DSPP_8 is a global setting bit to enable SEL_FDR and LVDS_8CH bits (Address 0x62 - Register 5-20).
3: When CW mode is enabled, the ADC output is the result of the summation (addition) of all eight channels’ data after each
channel’s digital phase offset, digital gain, and digital offset are controlled using the Addresses 0x86 - 0xA7 (Registers 5-47 to
5-79). The result is similar to the beamforming in the phased-array sensors.

REGISTER 5-43: ADDRESS 0X82 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (LOWER BYTE)

NCO_TUNE<7:0>
bit 7 bit 0
Legend:
bit 7-0 NCO_TUNE <7:0>: Lower byte of NCO_TUNE<31:0>(1)

0000-0000 = DC (0 Hz) when NCO_TUNE<31:0> = 0x00000000 (Default)
Note 1: See Note 1 and Note 2 in Address 0x85 (Register 5-46).
REGISTER 5-44: ADDRESS 0X83 – NUMERICALLY CONTROLLED OSCILLATOR TUNING

(MIDDLE-LOWER BYTE)

NCO_TUNE<15:8>
bit 7 bit 0
Legend:
bit 7-0 NCO_TUNE<15:8>: Middle lower byte of NCO_TUNE<31:0>(1)

0000-0000 = Default
REGISTER 5-45: ADDRESS 0X84 – NUMERICALLY CONTROLLED OSCILLATOR TUNING

(MIDDLE-UPPER BYTE)

NCO_TUNE<23:16>
bit 7 bit 0
Legend:
bit 7-0 NCO_TUNE<23:16>: Middle upper byte of NCO_TUNE<31:0>(1)

0000-0000 = Default

REGISTER 5-46: ADDRESS 0X85 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (UPPER BYTE)

NCO_TUNE<31:24>
bit 7 bit 0
Legend:
bit 7-0 NCO_TUNE<31:24>: Upper byte of NCO_TUNE<31:0>(1,2)

1111-1111 = fS if NCO_TUNE<31:0> = 0xFFFF FFFF
•••
0000-0000 = Default
Note 1: This Register is used only when DDC is enabled: EN_DDC1 = 1 in Address 0x80 (Register 5-41). See Section 4.8.4.3,
"Numerically Controlled Oscillator (NCO)" for the details of NCO.
2: NCO frequency = (NCO_TUNE<31:0>/232) x fS, where fS is the sampling clock frequency.
REGISTER 5-47: ADDRESS 0X86 – CH0 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)

CH0_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
bit 7-0 CH0_NCO_PHASE<7:0>: Lower byte of CH0_NCO_PHASE<15:0>(1,2,3)

1111-1111 = 1.4° when CH0_NCO_PHASE<15:0> = 0x00FF
•••
0000-0000 = 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: This register is not used in the MCP37211. In the MCP37D11, this register has an effect when the following modes are used:
- CW with DDC mode in octal-channel mode
- Single and dual-channel mode with DDC.
2: CH0 is the 1st channel selected by CH_ORDER<23:0>.
3: CH(n)_NCO_PHASE<15:0> = 216 x Phase Offset Value/360.

REGISTER 5-48: ADDRESS 0X87: CH0 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
CH0_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
bit 7-0 CH0_NCO_PHASE<15:8>: Upper byte of CH0_NCO_PHASE<15:0>(1)

1111-1111 = 359.995° when CH0_NCO_PHASE<15:0> = 0xFFFF
•••
Note 1: See Note 1 - Note 3 in Register 5-47.

CH1_NCO_PHASE<7:0>
bit 7 bit 0
Legend:
bit 7-0 CH1_NCO_PHASE<7:0>: Lower byte of CH1_NCO_PHASE<15:0>(1)

•••
Note 1: See Note 1 - Note 3 in Register 5-47. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-50: ADDRESS 0X89 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)

CH1_NCO_PHASE<15:8>
bit 7 bit 0
Legend:
bit 7-0 CH1_NCO_PHASE <15:8>: Upper byte of CH1_NCO_PHASE<15:0>(1)

•••
Note 1: See Note 1 - Note 3 in Register 5-47. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.

REGISTER 5-51: ADDRESS 0X8A – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)

CH2_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••
Note 1: See Note 1 - Note 3 in Register 5-47. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-52: ADDRESS 0X8B – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)

CH2_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••
Note 1: See Note 1 - Note 3 in Register 5-47. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-53: ADDRESS 0X8C – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)

CH3_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••
Note 1: See Note 1 - Note 3 in Register 5-47. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.

REGISTER 5-54: ADDRESS 0X8D – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)

CH3_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••
REGISTER 5-55: ADDRESS 0X8E – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)

CH4_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••
REGISTER 5-56: ADDRESS 0X8F – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)

CH4_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••


CH5_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••

CH5_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••

CH6_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••


CH6_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••

CH7_NCO_PHASE<7:0>
bit 7 bit 0
Legend:

•••

CH7_NCO_PHASE<15:8>
bit 7 bit 0
Legend:

•••

REGISTER 5-63: ADDRESS 0X96 – CH0 DIGITAL GAIN

CH0_DIG_GAIN<7:0>
bit 7 bit 0
Legend:
bit 7-0 CH0_DIG_GAIN<7:0>: Digital gain setting for channel 0(1,2)

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH0 is the 1st channel selected by CH_ORDER<23:0>.
2: Max = 0x7F(3.96875), Min = 0x80 (-4), Step size = 0x01 (0.03125). Bits from 0x81-0xFF are two’s complementary of 0x00-
0x80. Negative gain setting inverts output. See Addresses 0x7D - 0x7F (Registers 5-38 – 5-40) for channel selection.


CH1_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH1 is the 2nd channel selected by CH_ORDER<23:0>.
2: See Note 2 in Register 5-63.


CH2_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.


CH3_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH3 is the 4th channel selected by CH_ORDER<23:0> bits.

REGISTER 5-67: ADDRESS 0X9A – CH4 DIGITAL GAIN

CH4_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0
Note 1: CH4 is the 5th channel selected by CH_ORDER<23:0>.

REGISTER 5-68: ADDRESS 0X9B – CH5 DIGITAL GAIN

CH5_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0

REGISTER 5-69: ADDRESS 0X9C – CH6 DIGITAL GAIN

CH6_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0

REGISTER 5-70: ADDRESS 0X9D – CH7 DIGITAL GAIN

CH7_DIG_GAIN<7:0>
bit 7 bit 0
Legend:

1111-1111 = -0.03125
1111-1110 = -0.0625
1111-1101 = -0.09375
1111-1100 = -0.125
•••
1000-0011 = -3.90625
1000-0010 = -3.9375
1000-0001 = -3.96875
1000-0000 = -4
0111-1111 = 3.96875 (MAX)
0111-1110 = 3.9375
0111-1101 = 3.90625
0111-1100 = 3.875
•••
0011-1100 = 1.875 (Default)
•••
0000-0011 = 0.09375
0000-0010 = 0.0625
0000-0001 = 0.03125
0000-0000 = 0.0

REGISTER 5-71: ADDRESS 0X9E – CH0 DIGITAL OFFSET

CH0_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
bit 7-0 CH0_DIG_OFFSET <7:0>: Digital offset setting bits for channel 0(1)
1111-1111 = 0xFF x DIG_OFFSET_WEIGHT<1:0>
•••
0000-0001 = 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000 = 0 (Default)
Note 1: See Table 4-21 for the corresponding channel. Offset value is two’s complement. This value is multiplied by DIG_OFFSET_-
WEIGHT<1:0> in Address 0xA7 (Register 5-79).
REGISTER 5-72: ADDRESS 0X9F – CH1 DIGITAL OFFSET

CH1_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)
Note 1: See Note 1 in Register 5-71.
REGISTER 5-73: ADDRESS 0XA0 – CH2 DIGITAL OFFSET

CH2_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)


CH3_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)

CH4_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)

CH5_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)


CH6_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)

CH7_DIG_OFFSET<7:0>
bit 7 bit 0
Legend:
•••
0000-0000 = 0 (Default)
REGISTER 5-79: ADDRESS 0XA7 – DIGITAL OFFSET WEIGHT CONTROL

FCB<5:3> DIG_OFFSET_WEIGHT<1:0> FCB<2:0>
bit 7 bit 0
Legend:
bit 4-3 DIG_OFFSET_WEIGHT<1:0>: Control the weight of the digital offset settings(1)
11 = 2 LSb x Digital Gain
10 = LSb x Digital Gain
01 = LSb/2 x Digital Gain
00 = LSb/4 x Digital Gain, (Default)
Note 1: This bit setting is used for the digital offset setting registers in Addresses 0x9E - 0xA7 (Registers 5-71 – 5-79).

REGISTER 5-80: ADDRESS 0XC0 – CALIBRATION STATUS INDICATION
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ADC_CAL_STAT FCB<6:0>
bit 7 bit 0
Legend:
bit 7 ADC_CAL_STAT: Power-up auto-calibration status indication flag bit

1 = Device power-up calibration is completed
0 = Device power-up calibration is not completed
bit 6-0 FCB<6:0>: Factory-Controlled Bits. These bits are read only, and have no meaning for the user.
REGISTER 5-81: ADDRESS 0XD1 – PLL CALIBRATION STATUS AND PLL DRIFT STATUS INDICATION
R-x R-x R-x R-x R-x R-x R-x R-x
FCB<4:3> PLL_CAL_STAT FCB<2:1> PLL_VCOL_STAT PLL_VCOH_STAT FCB<0>
bit 7 bit 0
Legend:
bit 5 PLL_CAL_STAT: PLL auto-calibration status indication flag bit(1)
1= Complete: PLL auto-calibration is completed
0= Incomplete: PLL auto-calibration is not completed
bit 2 PLL_VCOL_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with low VCO frequency
0 = PLL operates as normal
bit 1 PLL_VCOH_STAT: PLL drift status indication bit
1 = PLL drifts out of lock with high VCO frequency
0 = PLL operates as normal
bit 0 FCB<0>: Factory-Controlled Bit. This bit is readable, but has no meaning for the user.
Note 1: See PLL_CAL_TRIG bit setting in Address 0x6B (Register 5-27).

REGISTER 5-82: ADDRESS 0X15C – CHIP ID (LOWER BYTE)

CHIP_ID<7:0>
bit 7 bit 0
Legend:
bit 7-0 CHIP_ID<7:0>: Device identification number. Lower byte of the CHIP ID<15:0>(1)
Note 1: Read-only register. Preprogrammed at the factory for internal use.
Example: MCP37D11-80: ‘0000 1010 0010 0000’
MCP37D31-80: ‘0000 1010 0110 0000’
MCP37D21-80: ‘0000 1010 0100 0000’
REGISTER 5-83: ADDRESS 0X15D – CHIP ID (UPPER BYTE)

CHIP_ID<15:8>
bit 7 bit 0
Legend:
bit 7-0 CHIP_ID<15:8>: Device identification number. Lower byte of the CHIP ID<15:0>(1)

6.0 DEVELOPMENT SUPPORT Graphical User Interface (GUI) software for ADC
configuration and evaluation. Figure 6-1 and Figure 6-
Microchip offers a high-speed ADC evaluation platform 2 show this evaluation tool. This evaluation platform
which can be used to evaluate Microchip’s high-speed allows users to quickly evaluate the ADC’s
ADC products. The platform consists of an MCP37D11- performance for their specific application requirements.
80 evaluation board (EV06P5A), and FPGA-based More information is available at http://
data capture card board (ADM00506), and PC-based www.microchip.com.
80 MHz Clock Signal Source
EV06P5A ADM00506
(MCP37D11-80 EV Board) (High-Speed Pipelined ADC Data Capture Card)
FIGURE 6-1: MCP37D11-80 Evaluation Kit.
FIGURE 6-2: PC-Based Graphical User Interface Software.

NOTES:

7.0 TERMINOLOGY Pipeline Delay (LATENCY)
Analog Input Bandwidth (Full-Power LATENCY is the number of clock cycles between the
Bandwidth) initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is
The analog input frequency at which the spectral power available after the pipeline delay plus the output delay
of the fundamental frequency (as determined by FFT after that sample is taken. New data is available at
analysis) is reduced by 3 dB. every clock cycle, but the data lags the conversion by
the pipeline delay plus the output delay. Latency is
Aperture Delay or Sampling Delay increased if digital signal post-processing is used.
This is the time delay between the rising edge of the
input sampling clock and the actual time at which the
Clock Pulse Width and Duty Cycle
sampling occurs. The clock duty cycle is the ratio of the time the clock
signal remains at a logic high (clock pulse width) to one
Aperture Uncertainty clock period. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock
The sample-to-sample variation in aperture delay. results in a 50% duty cycle.
Aperture Delay Jitter Differential Nonlinearity

The variation in the aperture delay time from (DNL, No Missing Codes)
conversion to conversion. This random variation will
An ideal ADC exhibits code transitions that are exactly
result in noise when sampling an AC input. The
1 LSb apart. DNL is the deviation from this ideal value.
signal-to-noise ratio due to the jitter alone will be:
No missing codes to 12-bit resolution indicates that all
4096 codes must be present over all the operating
EQUATION 7-1: conditions.
SNRJITTER = – 20 log  2   fIN  t JITTER  Integral Nonlinearity (INL)
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
Calibration Algorithms scale through positive full scale.
This device utilizes two patented analog and digital
calibration algorithms, Harmonic Distortion Correction Signal-to-Noise Ratio (SNR)
(HDC) and DAC Noise Cancellation (DNC), to improve
the ADC performance. The algorithms compensate SNR is the ratio of the power of the fundamental (PS) to
various sources of linear impairments such as the noise floor power (PN), below the Nyquist frequency
capacitance mismatch, charge injection error and finite and excluding the power at DC and the first nine
gain of operational amplifiers. These algorithms harmonics.
execute in both power-up sequence (foreground) and
background mode: EQUATION 7-2:
• Power-Up Calibration: The calibration is  PS 
SNR = 10 log  -------
conducted within the first 227 clock cycles after  PN
power-up. The user needs to wait this Power-Up
Calibration period after the device is powered-up SNR is either given in units of dBc (dB to carrier) when
for an accurate ADC performance. the absolute power of the fundamental is used as the
• Background Calibration: This calibration is reference, or dBFS (dB to full-scale) when the power of
conducted in the background while the ADC the fundamental is extrapolated to the converter
performs conversions. The update rate is about full-scale range.
every 230 clock cycles.
Channel Crosstalk
This is a measure of the internal coupling of a signal
from an adjacent channel into the channel of interest in
the multi-channel mode. It is measured by applying a
full-scale input signal in the adjacent channel.
Crosstalk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest)
to the power of the signal applied at the adjacent
channel input. It is typically expressed in dBc.

Signal-to-Noise and Distortion (SINAD) Maximum Conversion Rate
SINAD is the ratio of the power of the fundamental (PS) The maximum clock rate at which parametric testing is
to the power of all the other spectral components performed.
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC: Minimum Conversion Rate
EQUATION 7-3: The minimum clock rate at which parametric testing is
performed.
 PS 
SINAD = 10 log  ----------------------
 P D + PN Spurious-Free Dynamic Range (SFDR)
SNR THD
– -----------
10
– ------------
10
SFDR is the ratio of the power of the fundamental to the
= – 10 log 10 – 10 highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale) when the Total Harmonic Distortion (THD)
power of the fundamental is extrapolated to the THD is the ratio of the power of the fundamental (PS) to
converter full-scale range. the summed power of the first 13 harmonics (PD).
Effective Number of Bits (ENOB) EQUATION 7-5:

The effective number of bits for a sine wave input at a  PS 
given input frequency can be calculated directly from its THD = 10 log  --------
 PD
measured SINAD using the following formula:
THD is typically given in units of dBc (dB to carrier).
EQUATION 7-4: THD is also shown by:
SINAD – 1.76
ENOB = ----------------------------------
6.02 EQUATION 7-6:
2 2 2 2
V2 + V3 + V4 +  + Vn
Gain Error THD = – 20 log ------------------------------------------------------------------
2
Gain error is the deviation of the ADC’s actual input V1
full-scale range from its ideal value. The gain error is Where:
given as a percentage of the ideal input full-scale
range. V1 = RMS amplitude of the
fundamental frequency
Gain error is usually expressed in LSb or as a
V1 through Vn = Amplitudes of the second
percentage of full-scale range (%FSR).
through nth harmonics
Gain-Error Drift
Gain-error drift is the variation in gain-error due to a Two-Tone Intermodulation Distortion
change in ambient temperature, typically expressed in (Two-Tone IMD, IMD3)
ppm/°C. Two-tone IMD is the ratio of the power of the
fundamental (at frequencies fIN1 and fIN2) to the power
Offset Error of the worst spectral component at either frequency
The major carry transition should occur for an analog 2fIN1 – fIN2 or 2fIN2 – fIN1. Two-tone IMD is a function of
value of 50% LSb below AIN+ = AIN−. Offset error is the input amplitudes and frequencies (fIN1 and fIN2). It
defined as the deviation of the actual transition from is either given in units of dBc (dB to carrier) when the
that point. absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
Temperature Drift the fundamental is extrapolated to the ADC full-scale
range.
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value across the TMIN to TMAX range.

Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The Common-mode signal can
be an AC or DC signal or a combination of the two.
CMRR is measured using the ratio of the differential
signal gain to the Common-mode signal gain and
expressed in dB with the following equation:
EQUATION 7-7:
 A DIFF
CMRR = 20 log  ------------------
 ACM 
Where:
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common-mode Voltage

NOTES:

8.0 PACKAGING INFORMATION
8.1 Package Marking Information
128-Ball TFBGA Example:
Microchip
MCP37D11
80/TE
e31
^^
YYWWNNN
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e31 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3
1)
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A B
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
0.15 C TOP VIEW
A
C 0.10 C
SEATING
PLANE A2
A1 0.10 C
SIDE VIEW
D1
eD
L
K
J
H
eE
G
F E1
E
D
NOTE 1 C
B
A
1 2 3 4 5 6 7 8 9 10 11
A1 BALL PAD CORNER DETAIL A

BOTTOM VIEW
Microchip Technology Drawing C04-212-TE Rev C Sheet 1 of 2

System In Package
121X Øb
0.15 C A B
0.08 C
DETAIL A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 121
Pitch eE 0.65 BSC
Pitch eD 0.65 BSC
Overall Height A - - 1.08
Standoff A1 0.21 0.32 -
Cap Thickness A2 0.40 0.45 0.50
Overall Width E 8.00 BSC
Overall Pitch E1 6.50 BSC
Overall Length D 8.00 BSC
Overall Pitch D1 6.50 BSC
Terminal Diameter b 0.35 0.40 0.45
Notes:
1. Terminal A1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-212-TE Rev C Sheet 2 of 2

System In Package
E
C2
121X ØB
E
C1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.65 BSC
Contact Pad Spacing C1 6.50
Contact Pad Spacing C2 6.50
Contact Pad Diameter (X121) B 0.35
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2212-TE Rev C

NOTES:

APPENDIX A: REVISION HISTORY
Revision A (June 2020)

• Original release of this document.

PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) -XXX X /XX Examples:

a) MCP37D11-80E/TE: 80 Msps, Tube or Tray,
Device Tape and Reel Sample Temperature Package Extended temperature,
Option Rate Range 121LD TFBGA package
b) MCP37D11T-80E/TE: 80 Msps,
Tape and Reel,
Device: MCP37D11-80: 12-Bit, 80 Msps High-Precision Pipelined ADC Extended temperature,
with Configurable 8-Channel Input MUX, and, 121LD TFBGA package
with built-in Digital Signal Post Processing
features that include Digital Down-Converter,
Decimation Filter, Noise-Shaping Requantizer,
Fractional Delay Recovery, Phase/Gain/Offset
Adjustment per Channel, and CW
Beamforming.
Tape and Blank = Standard packaging (tube or tray)

Reel Option: T = Tape and Reel(1)
Sample Rate: 80 = 80 Msps
Temperature E = -40C to +125C (Extended)

Range:
Package: TE = Ball Plastic Thin Profile Fine Pitch Ball Grid Array -
8x8x1.08 mm Body (TFBGA), 121-Lead
Note 1: Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not printed
on the device package. Check with your Microchip Sales Office for
package availability with the Tape and Reel option.

NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
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02/28/20

MCP37D11 80 Data Sheet DS20006381A

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MCP37D11 80 Data Sheet DS20006381A

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MCP37D11-80

80 Msps, 12-Bit High-Precision Pipelined ADC

Features • Digital Signal Post-Processing (DSPP) Options:

MCP37Dx1-80 Family Comparison(1):

 2020 Microchip Technology Inc. DS20006381A-page 1

AVDD12 AVDD18 GND DVDD12 DVDD18

Digital Signal Post-Processing:

- Digital Down-Converter (DDC)

VBG REF1+ REF1- REF0+ REF0- SDIO SCLK CS SYNC SLAVE

DS20006381A-page 2  2020 Microchip Technology Inc.

 2020 Microchip Technology Inc. DS20006381A-page 3

DS20006381A-page 4  2020 Microchip Technology Inc.

1.0 PACKAGE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

K TP TP TP DCLK- CAL GND SLAVE ADR0 ADR1 GND GND

L TP TP TP DCLK+ RESET SYNC GND CLK+ CLK- GND AVDD18

 2020 Microchip Technology Inc. DS20006381A-page 5

TABLE 1-1: PIN FUNCTION TABLE FOR TFBGA-121 PACKAGE

DS20006381A-page 6  2020 Microchip Technology Inc.

 2020 Microchip Technology Inc. DS20006381A-page 7

DS20006381A-page 8  2020 Microchip Technology Inc.

 2020 Microchip Technology Inc. DS20006381A-page 9

DS20006381A-page 10  2020 Microchip Technology Inc.

2.1 Absolute Maximum Ratings†

2.2 Electrical Specifications

 2020 Microchip Technology Inc. DS20006381A-page 11

DS20006381A-page 12  2020 Microchip Technology Inc.

 2020 Microchip Technology Inc. DS20006381A-page 13

DS20006381A-page 14  2020 Microchip Technology Inc.

 2020 Microchip Technology Inc. DS20006381A-page 15

TABLE 2-2: TIMING REQUIREMENTS - LVDS AND CMOS OUTPUTS

Parameters Sym. Min. Typ. Max. Units Conditions

DS20006381A-page 16  2020 Microchip Technology Inc.

Q<N:0> S-L-1 S-L S-L+1 S-1 S

OVR S-L-1 S-L S-L+1 S-1 S

FIGURE 2-1: Timing Diagram - CMOS Output.

Digital Clock Output: tCPD

 2020 Microchip Technology Inc. DS20006381A-page 17

FIGURE 2-3: SPI Serial Input Timing Diagram.

SDIO MSb out LSb out

FIGURE 2-4: SPI Serial Output Timing Diagram.

DS20006381A-page 18  2020 Microchip Technology Inc.

Power-on Reset (VPOR)

POR Stabilization Period: Power-Up calibration complete:

FIGURE 2-5: Internal Power-Up Sequence Events.

Stop ADC conversion Start register initialization Recalibration complete:

FIGURE 2-6: RESET Pin Timing Diagram.

A. Master Device (SLAVE Pin = 0)

CAL Pin (Output) TPCAL

Data Output Invalid Data Valid Data

B. Slave Device(s) (SLAVE Pin = 1)

CAL Pin (Output) TPCAL

Data Output Invalid Data Valid Data

FIGURE 2-7: Figure 2-5Sync Timing Diagram with Power-On Reset.

 2020 Microchip Technology Inc. DS20006381A-page 19

A. Master Device (SLAVE Pin = 0)

CAL Pin (Output) TPCAL

Data Output Invalid Data Valid Data

B. Slave Device(s) (SLAVE Pin = 1)

CAL Pin (Output) TPCAL

79 SFDR (dBFS) 100