MAHARISHI UNIVERSITY OF

INFORMATION TECHNOLOGY

DIGITAL NOTES
[Department of Computer Application]

Subject Computer Organization and

Architecture
Name
Subject : BCA-302
Code
Course : BCA
Branch :
Semester : 3RD
Prepared by :

SESSION 2024-25
Addition and Subtraction with Signed Magnitude Data
Addition Algorithm
The addition algorithm specifies that:
• If the signs of P and Q are the same, add both the magnitudes and put the sign
of P to the result, as shown in the table below.
• Compare both the magnitudes and subtract the small number from the greater
number when the signs of P and Q disagree.
• In cases where P > Q, the output signs must be equal to P, or the complement
of P's sign in cases where P < Q.
• Subtract Q from P and change the sign of the output to positive when the two
magnitudes are equal.
Subtraction Algorithm
The subtraction algorithm states that:
• When the signs of P and Q differ, the subtraction method says to add both the
magnitudes and put the sign of P to the result.
• Compare both the magnitudes and subtract the smaller number from the greater
number when the signs of P and Q are the same.
• In cases where P > Q, the output signs must be equal to P, or the complement
of P's sign in cases where P < Q.
• Subtract Q from P and change the sign of the output to positive when the two
magnitudes are equal.
Operations Addition of Magnitudes Subtraction of Magnitudes

P>Q P<Q P=Q

(+P) + (+Q) +(P+Q)

(+P) + (-Q) +(P-Q) -(Q-P) +(P-Q)

(-P) + (+Q) -(P-Q) +(Q-P) +(P-Q)

(-P) + (-Q) -(P+Q)

(+P) - (+Q) +(P-Q) -(Q-P) +(P-Q)

(+P) - (-Q) +(P+Q)

(-P) - (+Q) -(P+Q)

(-P) - (-Q) -(P-Q) +(Q-P) +(P-Q)

Flowchart

Flowchart for addition and subtraction

Hardware Implementation

Hardware for signed-magnitude addition and subtraction

Example 1
Let's add two values, +3 and +2, using the signed magnitude representation.
Solution
We represent the given operands as shown below:
+3 = 0 0112
+2 = 0 0102
From the flowchart, we follow that As xor Bs = 0. This implies that As = Bs
Also, according to the table,
Operations Addition of Magnitudes Subtraction of Magnitudes

(+P) + (+Q) +(P+Q)

So we do the addition of the magnitude of both operands.

Mag(+3) + Mag(+2) = 0112 + 0102 = 1012 = Mag(5)
Now the sign of the result will be that of As
Therefore, +3 + (+2) = 0 1012 = +5
Example 2
Let's subtract two values, +3 and +2, using the signed magnitude representation.
Solution
We represent the given operands as shown below:
+3 = 0 0112
+2 = 0 0102
From the flowchart, we follow that As xor Bs = 0. This implies that As = Bs
Also according to the table,
Operations Addition of Magnitudes Subtraction of Magnitudes

P>Q P<Q P=Q

(+P) - (+Q) +(P-Q) -(Q-P) +(P-Q)

Since the magnitude of P > Q,

We get results by +(P-Q).
Mag(Result) = 011 + (010)’ + 1 = 011 + 101 + 1 = (001)
SignBit(Result) = 0
Therefore, +3 - (+2) = +(+3-2) = +1
Also see, What Is a Motherboard and what is middleware

Multiplication Algorithm in Signed Magnitude

Representation
Last Updated : 21 Aug, 2019
•
••
Multiplication of two fixed point binary number in signed magnitude
representation is done with process of successive shift and add operation.

In the multiplication process we are considering successive bits of the multiplier,

least significant bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied down.
The numbers copied down in successive lines are shifted one position to the left
from the previous number.
Finally numbers are added and their sum form the product.
The sign of the product is determined from the sign of the multiplicand and
multiplier. If they are alike, sign of the product is positive else negative.
Hardware Implementation :
Following components are required for the Hardware Implementation of
multiplication algorithm :

1. Registers:
Two Registers B and Q are used to store multiplicand and multiplier
respectively.
Register A is used to store partial product during multiplication.
Sequence Counter register (SC) is used to store number of bits in the
multiplier.
2. Flip Flop:
To store sign bit of registers we require three flip flops (A sign, B sign and
Q sign).
Flip flop E is used to store carry bit generated during partial product
addition.
3. Complement and Parallel adder:
This hardware unit is used in calculating partial product i.e, perform
addition required.
Flowchart of Multiplication:
1. Initially multiplicand is stored in B register and multiplier is stored in Q
register.
2. Sign of registers B (Bs) and Q (Qs) are compared using XOR functionality
(i.e., if both the signs are alike, output of XOR operation is 0 unless 1) and
output stored in As (sign of A register).
Note: Initially 0 is assigned to register A and E flip flop. Sequence counter is
initialized with value n, n is the number of bits in the Multiplier.
3. Now least significant bit of multiplier is checked. If it is 1 add the content of
register A with Multiplicand (register B) and result is assigned in A register
with carry bit in flip flop E. Content of E A Q is shifted to right by one
position, i.e., content of E is shifted to most significant bit (MSB) of A and
least significant bit of A is shifted to most significant bit of Q.
4. If Qn = 0, only shift right operation on content of E A Q is performed in a
similar fashion.
5. Content of Sequence counter is decremented by 1.
6. Check the content of Sequence counter (SC), if it is 0, end the process and
the final product is present in register A and Q, else repeat the process.
Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication
algorithm.

Ans. Here we have two numbers, 7 and 3. First of all, we need to convert 7 and 3 into
binary numbers like 7 = (0111) and 3 = (0011). Now set 7 (in binary 0111) as multiplicand
(M) and 3 (in binary 0011) as a multiplier (Q). And SC (Sequence Count) represents the
number of bits, and here we have 4 bits, so set the SC = 4. Also, it shows the number
of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

Qn Qn + 1 M = (0111) AC Q Qn + 1 SC
M' + 1 =
(1001) &
Operation

1 0 Initial 0000 0011 0 4

Subtract (M'
1001
+ 1)

1001

Perform
Arithmetic
Right Shift 1100 1001 1 3
operations
(ashr)

Perform
Arithmetic
1 1 Right Shift 1110 0100 1 2
operations
(ashr)
 Addition (A
0 1 0111
+ M)

0101 0100

Perform
Arithmetic
0010 1010 0 1
right shift
operation

Perform
Arithmetic
0 0 0001 0101 0 0
right shift
operation

The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the

binary representation of 21 is 10101. Here, we get the resultant in binary 00010101. Now
we convert it into decimal, as (000010101)10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

Arithmetic operations
Last Updated: 2023-05-24

An arithmetic operation is specified by combining operands with one arithmetic operator.

Arithmetic operations can also be specified by the ADD, SUBTRACT, DIVIDE, and MULTIPLY
built-in functions.

You can use the following operators in arithmetic operations:

Operator Operator name

+ Addition
- Subtraction
* Multiplication
⁄ Division
** Exponentiation
Table 1. Arithmetic operator

The plus sign and the minus sign can appear as prefix operators or as infix operators. All other
arithmetic operators can appear only as infix operators.
Prefix operators can precede and be associated with any of the operands of an infix operation.
For example, in the expression A*-B, the minus sign indicates that the value of A is multiplied
by -1 times the value of B.

More than one prefix operator can precede and be associated with a single variable. More than
one positive prefix operator has no cumulative effect, but two negative prefix operators have
the same effect as a single positive prefix operator.

• Data conversion in arithmetic operations

The two operands of an arithmetic operation can differ in type, base, mode, precision,
and scale. When they differ, conversion takes place.
• Results of arithmetic operations
After any necessary conversion of the operands in an expression has been carried out,
the arithmetic operation is performed and a result is obtained. This result can be the
value of the expression, or it can be an intermediate result upon which further
operations are to be performed, or a condition can be raised.
• Using exponentiation
This topic describes how exponentiation is handled in PL/I.

Decimal arithmetic operations in Computer

Architecture?
Computer ArchitectureComputer ScienceNetwork

Decimal arithmetic operations refer to a digital function that does decimal micro-
operations. This function adds or subtracts decimal numbers by forming 9’s or 10’s
complement of the subtrahend. This decimal arithmetic unit first accepts coded
decimal numbers and then generates output in the binary form.

Algorithms that are used for arithmetic operations with decimal data and binary data
are alike. If the micro-operations symbol is interpreted correctly the same flowchart
can be used for both multiplication and division.

The decimal numbers in BCD are stored in groups of four bits in the computer
registers. When performing decimal micro-operations, every 4-bit group represents
a decimal digit and has to be taken as a group

The table shows symbols for decimal arithmetic micro-operations.

Symbols for Decimal Arithmetic Micro-Operations

 Symbolic
Meaning
Representation

It can add decimal numbers and transfers the output

X←X+Y
to X.

Y′ 9’s complement of Y.

It can add the content of X and 10's complement of Y

X ← X + Y′ + 1
and transfers the output to X.

It can shifts the decimal number one digit towards the

dshr X
right in register X.

It can shifts the decimal number one digit towards left

dshl X
in register X

In this table, we can see a bar over the symbol for the register letter. This refers to
the 9’s complement of decimal number that is stored in the register. When 1 is added
to the 9’s complement the 10’s complement is produced.

Therefore, the symbol X ← X+ Y + 1 for decimal digits denotes, transfer of decimal

sum that was formed by adding the original content X to the 10’s complement of Y.

It may be confusing to use similar symbols for 9’s complement and 1’s complement
in case both types of data are used in the same system.

Therefore, it would be better to implement a different symbol for the 9’s complement.
In case only one type of data is taken into consideration, the symbol would apply to
the type of data used.