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    The Von Neumann Architecture

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    Arun Sharma
    The document describes the Von Neumann architecture, which is a basic design for computers consisting of four main subsystems: the memory, ALU, control unit, and I/O. It stores both the program and data in memory and executes program instructions sequentially. The control unit fetches and decodes instructions from memory and executes them by signaling the other subsystems. This allows computers based on the Von Neumann architecture to operate using a stored program.

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    The Von Neumann Architecture

    Uploaded by

    Arun Sharma
    127 views27 pages
    The document describes the Von Neumann architecture, which is a basic design for computers consisting of four main subsystems: the memory, ALU, control unit, and I/O. It stores both the program and data in memory and executes program instructions sequentially. The control unit fetches and decodes instructions from memory and executes them by signaling the other subsystems. This allows computers based on the Von Neumann architecture to operate using a stored program.

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    The document describes the Von Neumann architecture, which is a basic design for computers consisting of four main subsystems: the memory, ALU, control unit, and I/O. It stores both the program and data in memory and executes program instructions sequentially. The control unit fetches and decodes instructions from memory and executes them by signaling the other subsystems. This allows computers based on the Von Neumann architecture to operate using a stored program.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    127 views27 pages

    The Von Neumann Architecture

    Uploaded by

    Arun Sharma
    The document describes the Von Neumann architecture, which is a basic design for computers consisting of four main subsystems: the memory, ALU, control unit, and I/O. It stores both the program and data in memory and executes program instructions sequentially. The control unit fetches and decodes instructions from memory and executes them by signaling the other subsystems. This allows computers based on the Von Neumann architecture to operate using a stored program.

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    © All Rights Reserved
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    of 27

    The Von Neumann

    Architecture
    Chapter 5.1-5.2

    Von Neumann
    Architecture

    Designing Computers
    All computers more or less based on the same
    basic design, the Von Neumann Architecture!

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    The Von Neumann


    Architecture

    Model for designing and building computers,


    based on the following three characteristics:
    1) The computer consists of four main sub-systems:

    Memory
    ALU (Arithmetic/Logic Unit)
    Control Unit
    Input/Output System (I/O)

    2) Program is stored in memory during execution.


    3) Program instructions are executed sequentially.
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    The Von Neumann


    Architecture Bus
    Processor (CPU)
    Memory

    Control Unit
    ALU

    Input-Output

    Communicate with
    "outside world", e.g.
    Screen
    Execute program
    Keyboard
    Storage devices
    Do arithmetic/logic operations
    ...
    requested by program
    CMPUT101 Introduction (c) Yngvi Bjorns
    4

    Store data and program

    Memory Subsystem
    Memory, also called RAM (Random Access Memory),
    Consists of many memory cells (storage units) of a fixed size.
    Each cell has an address associated with it: 0, 1,
    All accesses to memory are to a specified address.
    A cell is the minimum unit of access (fetch/store a complete cell).
    The time it takes to fetch/store a cell is the same for all cells.

    When the computer is running, both


    Program
    Data (variables)

    are stored in the memory.


    CMPUT101 Introduction

    (c) Yngvi Bjorns

    RAM

    Need to distinguish between


    the address of a memory cell and
    the content of a memory cell

    Memory width (W):


    How many bits is each memory
    cell, typically one byte (=8 bits)

    0000000000000001
    0
    1
    2

    Address width (N):


    How many bits used to represent
    each address, determines the
    maximum memory size = address
    space
    If address width is N-bits, then
    address space is 2N (0,1,...,2N-1)
    CMPUT101 Introduction

    1 bit

    2N
    ...

    2N-1

    (c) Yngvi Bjorns

    Memory Size / Speed


    Typical memory in a personal computer (PC):
    64MB - 256MB

    Memory sizes:

    Kilobyte (KB)
    Megabyte(MB)
    Gigabyte (GB)

    = 210 =
    1,024 bytes
    = 220 =
    1,048,576 bytes
    = 230 = 1,073,741,824 bytes

    ~
    ~
    ~

    1 thousand
    1 million
    1 billion

    Memory Access Time (read from/ write to memory)


    50-75 nanoseconds (1 nsec. = 0.000000001 sec.)

    RAM is
    volatile (can only store when power is on)
    relatively expensive
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    Operations on Memory
    Fetch (address):
    Fetch a copy of the content of memory cell with the specified
    address.
    Non-destructive, copies value in memory cell.

    Store (address, value):


    Store the specified value into the memory cell specified by address.
    Destructive, overwrites the previous value of the memory cell.

    The memory system is interfaced via:

    Memory Address Register (MAR)


    Memory Data Register (MDR)
    Fetch/Store signal

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    Structure of the Memory


    Subsystem
    MAR

    MDR
    F/S

    Memory
    decoder
    circuit

    Fetch/Store
    controller

    Fetch(address)
    Load address into MAR.
    Decode the address in MAR.
    Copy the content of memory cell with
    specified address into MDR.

    Store(address, value)

    ...

    CMPUT101 Introduction

    Load the address into MAR.


    Load the value into MDR.
    Decode the address in MAR
    Copy the content of MDR into memory
    cell with the specified address.

    (c) Yngvi Bjorns

    Input/Output Subsystem
    Handles devices that allow the computer system to:
    Communicate and interact with the outside world
    Screen, keyboard, printer, ...
    Store information (mass-storage)
    Hard-drives, floppies, CD, tapes,

    Mass-Storage Device Access Methods:


    Direct Access Storage Devices (DASDs)
    Hard-drives, floppy-disks, CD-ROMs, ...

    Sequential Access Storage Devices (SASDs)


    Tapes (for example, used as backup devices)
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    10

    I/O Controllers
    Speed of I/O devices is slow compared to RAM
    RAM
    ~ 50 nsec.
    Hard-Drive ~ 10msec. = (10,000,000 nsec)
    Solution:
    I/O Controller, a special purpose processor:
    Has a small memory buffer, and a control logic to control I/O
    device (e.g. move disk arm).
    Sends an interrupt signal to CPU when done read/write.

    Data transferred between RAM and memory buffer.


    Processor free to do something else while I/O controller
    reads/writes data from/to device into I/O buffer.
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    11

    Structure of the I/O


    Subsystem
    Data from/to memory

    Interrupt signal (to processor)

    I/O controller
    I/O Buffer
    Control/Logic

    I/O device
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    12

    The ALU Subsystem


    The ALU (Arithmetic/Logic Unit) performs

    mathematical operations (+, -, x, /, )


    logic operations (=, <, >, and, or, not, ...)

    In today's computers integrated into the CPU


    Consists of:

    Circuits to do the arithmetic/logic operations.


    Registers (fast storage units) to store intermediate
    computational results.
    Bus that connects the two.
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    13

    Structure of the ALU


    Registers:
    Very fast local memory cells, that
    store operands of operations and
    intermediate results.
    CCR (condition code register), a
    special purpose register that stores
    the result of <, = , > operations

    ALU circuitry:

    R0
    R1
    R2

    Rn

    Contains an array of circuits to do


    mathematical/logic operations.

    ALU circuitry

    Bus:
    Data path interconnecting the
    registers to the ALU circuitry.
    CMPUT101 Introduction (c) Yngvi Bjorns

    GT EQ LT
    14

    The Control Unit


    Program is stored in memory
    as machine language instructions, in binary

    The task of the control unit is to execute programs


    by repeatedly:

    Fetch from memory the next instruction to be executed.


    Decode it, that is, determine what is to be done.
    Execute it by issuing the appropriate signals to the
    ALU, memory, and I/O subsystems.
    Continues until the HALT instruction
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    15

    Machine Language
    Instructions

    A machine language instruction consists of:


    Operation code, telling which operation to perform
    Address field(s), telling the memory addresses of the
    values on which the operation works.

    Example: ADD X, Y

    (Add content of memory locations X


    and Y, and store back in memory location Y).
    Assume: opcode for ADD is 9, and addresses X=99, Y=100
    Opcode (8 bits) Address 1 (16 bits)
    00001001 0000000001100011
    CMPUT101 Introduction

    Address 2 (16 bits)


    0000000001100100

    (c) Yngvi Bjorns

    16

    Instruction Set Design


    Two different approaches:
    Reduced Instruction Set Computers (RISC)
    Instruction set as small and simple as possible.
    Minimizes amount of circuitry --> faster computers

    Complex Instruction Set Computers (CISC)


    More instructions, many very complex
    Each instruction can do more work, but require more
    circuitry.

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    17

    Typical Machine
    Instructions

    Notation:

    We use X, Y, Z to denote RAM cells


    Assume only one register R (for simplicity)
    Use English-like descriptions (should be binary)

    Data Transfer Instructions

    LOAD X
    Load content of memory location X to R
    STORE X
    Load content of R to memory location X
    MOVE X, Y Copy content of memory location X to loc. Y
    (not absolutely necessary)

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    18

    Machine Instructions
    (cont.)

    Arithmetic

    ADD X, Y, Z
    CON(Z) = CON(X) + CON(Y)
    ADD X, Y
    CON(Y) = CON(X) + CON(Y)
    ADD X
    R = CON(X) + R
    similar instructions for other operators, e.g. SUBTR,OR, ...

    Compare
    COMPARE X, Y
    Compare the content of memory cell X to the content of memory
    cell Y and set the condition codes (CCR) accordingly.
    E.g. If CON(X) = R then set EQ=1, GT=0, LT=0
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    19

    Machine Instructions
    (cont.)
    Branch
    JUMP X
    JUMPGT X

    Load next instruction from memory loc. X

    Load next instruction from memory loc. X


    only if GT flag in CCR is set, otherwise load
    statement from next sequence loc. as
    usual.
    JUMPEQ, JUMPLT, JUMPGE, JUMPLE,JUMPNEQ

    Control
    HALT

    Stop program execution.

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    20

    Example
    Pseudo-code: Set A to B + C
    Assuming variable:
    A stored in memory cell 100, B stored in memory cell
    150, C stored in memory cell 151
    Machine language (really in binary)

    LOAD
    ADD
    STORE
    or
    (ADD

    150
    151
    100
    150, 151, 100)

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    21

    Structure of the Control


    Unit
    PC (Program Counter):

    stores the address of next instruction to fetch


    IR (Instruction Register):
    stores the instruction fetched from memory
    Instruction Decoder:
    Decodes instruction and activates necessary circuitry
    PC
    +1

    CMPUT101 Introduction

    IR

    Instruction
    Decoder

    (c) Yngvi Bjorns

    22

    von Neumann
    Architecture

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    23

    How does this all work


    together?
    Program Execution:
    PC is set to the address where the first program
    instruction is stored in memory.
    Repeat until HALT instruction or fatal error
    Fetch instruction
    Decode instruction
    Execute instruction

    End of loop
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    24

    Program Execution (cont.)


    Fetch phase

    PC --> MAR
    Fetch signal
    MDR --> IR
    PC + 1 --> PC

    (put address in PC into MAR)


    (signal memory to fetch value into MDR)
    (move value to Instruction Register)
    (Increase address in program counter)

    Decode Phase

    IR -> Instruction decoder (decode instruction in IR)


    Instruction decoder will then generate the signals to
    activate the circuitry to carry out the instruction

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    25

    Program Execution (cont.)


    Execute Phase
    Differs from one instruction to the next.

    Example:
    LOAD X (load value in addr. X into register)
    IR_address -> MAR
    Fetch signal
    MDR --> R

    ADD X
    left as an exercise
    CMPUT101 Introduction

    (c) Yngvi Bjorns

    26

    Instruction Set for Our Von


    Neumann
    Machine
    Opcode
    Operation
    Meaning
    0000
    0001
    0010
    0011
    0100
    0101
    0101

    LOAD X
    STORE X
    CLEAR X
    ADD X
    INCREMENT X
    SUBTRACT X
    DECREMENT X
    COMPARE X

    CON(X) --> R
    R --> CON(X)
    0 --> CON(X)
    R + CON(X) --> R
    CON(X) + 1 --> CON(X)
    R - CON(X) --> R
    CON(X) - 1 --> CON(X)

    JUMP X
    JUMPGT X
    JUMPxx X
    IN X
    OUT X
    HALT

    Get next instruction from memory location X


    Get next instruction from memory loc. X if GT=1
    xx = LT / EQ / NEQ
    Input an integer value and store in X
    Output, in decimal notation, content of mem. loc. X
    Stop program execution

    0111
    1000
    1001
    ...
    1101
    1110
    1111

    If CON(X) > R then GT = 1 else 0


    If CON(X) = R then EQ = 1 else 0
    If CON(X) < R then LT = 1 else 0

    CMPUT101 Introduction

    (c) Yngvi Bjorns

    27

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