Computer Organization

(Instruction set Architecture &

Assembly Language Programming)

KR Chowdhary
Professor & Head
Email: [email protected]
webpage: krchowdhary.com

Department of Computer Science and Engineering

MBM Engineering College, Jodhpur

November 14, 2013

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Instruction set principles

◮ Instruction set architecture: A portion of the computer visible to

machine language programmer / compiler writer.
Execution Environments:
◮ Desktop: performance of programs decided by integer and
floating-point arithmetics, no concern to power consumption, and
program size, Appl. Main use web browsing, limited computations.
Compiler generated code.
◮ Servers: data, file servers, web applications, time sharing
applications for many users,
◮ Real-time and embedded systems : Low cost and power, small code
size, e.g., DSP (digital signal processing) and media processors,
continuous streaming of data, fast execution of code (targeting the
worst case performance), code is hand optimized.

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Classification of Instruction set Architectures

◮ High performance Systems: RISC Architecture.

◮ Architectures:
1. Stack architecture: operand is implicitly on top of stack
2. Accumulator architecture: one operand specified other in
accumulator
3. General purpose register(GPR) architecture: operands explicitly in
register or memory.
4. Memory-Memory Architecture: All operands are in memory.
◮ GPR: Registers are faster, and more efficient to use by the compiler.
◮ In (A ∗ B) − (B ∗ C ) − (A ∗ D), multiplication can be evaluated in any
order by GPR but not by stack m/c (example later on)

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Operand locations for four Instruction set architectures

Register-register/
Stack Accumulator Register-memory Load-storage
b b b b b b

TOS
b b b b b b
Processor

b b b

ALU ALU ALU ALU

b b b b b b b b b b b b
Memory

b b b b b b b b b b b b

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Instruction set principles

\\ compute C = A + B
Stack: Accumulator: Register-memory
push A Load A //accesses memory as part of
push B Add B // instruction
Add store C Load R1, A
Pop C Add R3, R1, B
Store R3, C

Register-register:
//accesses memory through load/store inst.
Load R1, A
Load R2, B
Add R3, R1, R2
Store R3, C

Memory-memory architecture?

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Stack v/s Register Memory addressing
Evaluate: (A*B)-(B*C)-(A*D)
-
Stack Machine:
-
PUSH A *

PUSH B * *
A D
MULT A B B C
PUSH B
Figure 1: Tree for (A ∗ B) − (B ∗ C ) − (A ∗ D). Post-Order:
PUSH C
AB ∗ BC ∗ −AD ∗ −
MULT
SUB
Register-Memory Addressing:
PUSH A
MULT E, A, B; A-F registers
PUSH D
MULT F, B, C
MULT
SUB F, E, F
SUB
MULT E, A, D
POP T
SUB T, F, E; T is memory location
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Issues in Instruction set Design

◮ Variables allocated to registers ⇒ memory traffic reduces, program

speeds up, code density reduces (register named with fewer bits)
◮ What can be the +ve and -ve issues of R-R, R-M, and M-M
instructions?
Issues in Memory Addressing:
◮ How memory addresses are specified and interpreted?
◮ Memory Issue: Big Endian v/s Little Endian. In first, the bits are 0,
1, ..., 6, 7. In second: 7, 6, ..., 1, 0. How does it make difference?
Instruction formats: Most instructions specify a register transfer
operation of the form: an opcode followed with a set of n operands,
e.g., X1 = f (X1 , X2 , . . . , Xn ).
◮ Addressing Modes: How the architecture specify the address of an
object?

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Typical Architecture: Intel 8085 Bus structure

◮ 8-bit CPU
◮ Communicates with other units through 16-bit address bus, 8-bit
data bus, and control bus
◮ Address: A0 − A15 , total addressable memory=216 = 65536 (64k).
Address locations 0 - 65535 (0000H - FFFFH).
◮ Databus D0 − D7 (little E.), multiplexed with lower 8 bits (A0 − A7 )
of address bus (A0 − A15 ).
◮ Control bus: Various signal lines (binary) carrying signals like
Read/write, Enable, Ready, Flag bits, etc.

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Typical Architecture: Intel 8085 Internal architecture

◮ 8-bit microprocessor (word length = 8-bit)

◮ Stores 8-bit data (registers, accumulator, memory locations)
◮ Performs arithmetic, logic, and data movement operations using
8-bits
◮ Tests for conditions (if/then)
◮ Sequence the execution of instructions (jumps, etc)
◮ Stores temporary data in RAM & register during runtime

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Intel 8085 Registers

◮ ACC + 6 general purpose registers (8-bit): A(111), B(000), C(001),

D(010), E(011), H(100), L(101), which can be used to form 3 no.
of 16-bit registers, BC(00), DE(01), HL(10), SP(11): two bits in 1st
byte.
◮ Accumulator + Flag register = PSW (processor status register)
(status: Z, S, P, C, AC)
◮ Flag bits: To indicate the result of condition: C(carry), Z(zero),
S(sign minus), P(sign plus), AC(auxiliary carry)
◮ Flag bits are used as Tests for conditions (if/then)
◮ Program Counter (PC): Contains memory address of next instruction
◮ Stack Pointer(SP): holds the return address for subroutine call, can
save registers(PUSH, POP Instructions)

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Intel 8085 Architecture

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Intel 8085 assembly language programming

;Program to add two numbers:

MVI A, 7BH
MVI B, 67H
ADD B
HLT

;Program to multiply a given no. by number 4:

MVI A, 30H
RRC
RRC
MOV B, A
HLT

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Intel 8085 assembly language programming

;Find greater of two numbers:

MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ eq
JP gt
JM lt
eq: MVI D, 00H
JMP stop
gt: MVI D, 01H
JMP stop
lt: MVI D, 02H
stop: HLT

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Intel 8085 Instruction set

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Intel 8085 addressing modes

◮ Immediate addressing (MVI B, 25H)

◮ Direct addressing (LDA 1020H)
◮ Register addressing (MOV B, C)
◮ Implied addressing (CMA, RAR)
◮ Register Indirect addressing(MOV A, M; ADD M).
◮ Register Indirect addressing(LDAX B, LDAX D, STAX B, STAX D)

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Programming in assembly language

;Code to sum five locations and store the result at subsequent

;location:
LXI H, 1010H ; memory pointer for start of data
MVI C, 05H ; initialize counter value
XRA A ; Exclusive OR A with itself
loop: ADC M ; add memory into Accumulator with carry
INX H ; increment the memory pointer register pair HL
DCR C ; decrement the counter
JNZ loop ; if counter not zero then repeat the loop
MOV M, A ; store the sum at subsequent location.
HLT ; otherwise halt the processor

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Programming in assembly language

;Code to copy paste 1000H to 2000H for 25H locations:

LXI B, 1010H ; source pointer
LXI D, 2000H ; destination pointer
MVI H, 25H ; counter initialize
loop: LDAX B
STAX D
INX B
INX D
DCR H
JNZ loop
HLT

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PDP-11 Mini-Computer, 1970s

◮ Registers: R0:R5, SP=R6, PC=R7,(all 16 bits), Status Flags: I, V,

N, Z, C
◮ Address: 16-bits (64K), (32-k words)
◮ additional instructions, like MUL, DIV, WAIT, RESET, and many
more powerful instructions
◮ later versions supported Virtual memory.
◮ 8085 instruction set is subset of PDP11 (DEC machine)
◮ Addressing modes: register, autoincrement, autodecrement, index,
indirect, immediate, absolute, relative

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PDP-11

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IBM360 Addressing Modes
16 General Purpose Register:R0 − R15 ,Mem adr: 20bits
Register Add R3, R4
Immediate Add R4, #3
Displacement Add R4, 100(R1)
Register Indirect Add R4, (R1)
Indexed Add R3, (R1+R2); R1 base, R2 Index
Direct/Absolute Add R1, (1001); [R1] ← [R1]+m[1001]
Memory Indirect Add R1, @(R3); [R1]←[R1]+M[M[R3]]
Auto Increment Add R1, (R2)+; [R1]←[R1]+M[R2]
[R2]← [R2]+d; d size of elem.
Auto decrement Add R1, -(R2);[R2]← [R2]-d; R[1]←[R1]+M[R2]
◮ Addressing modes reduce the instruction count, add complexity in
building computer, may increase average clock cycles per instruction.
Number of addresses:
◮ CDC 6600: ADD Z, Y, X ; three address

1 Fever operands → lesser functions per instruction → longer

programs → longer execution times.
2 long instructions with multiple operands → more complex decoding
& processing circuits.
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Exercises

1. Assume an instruction set that uses a fixed 16-bit instruction length.

Operand specifiers are 6 bits in length. There are 5 two operand
instructions and 33 zero operand instructions. What is the
maximum number of one-operand instructions that can be encoded
using the fixed 16-bit instruction length?
2. A given processor has 32 registers, uses 16-bit immediate and has
142 instructions. In a given program,
◮ 20 % of the instructions take 1 input register and have 1 output
register.,
◮ 30 % have 2 input registers and 1 output register,
◮ 25 % have 1 input register, 1 output register and take an immediate
input as well, and the remaining 25 % have one immediate input and
1 output register.

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Exercises
2.1 For each of the 4 types of instructions , how many bits are required?
Assume that it requires that all instructions be a multiple of 8 bits in
length.
2.2 How much less memory does the program take up if variable-length
instruction set encoding is used as opposed to fixed-length encoding?
3. Compare the memory efficiency of the following instruction set
architectures:
◮ Accumulator- All operations occur between a single register and a
memory location. There are two accumulators of which one is
selected by the opcode;
◮ Memory-memory: All instruction addresses reference only memory
locations
◮ Stack - All operations occur on top of the stack. The
implementation uses a hardwired stack for only the top two stack
entries, which keeps the processor circuit very small and low cost.
Additional stack positions are kept in memory locations, and
accesses to these stack positions require memory references.
◮ Load-store - All operations occur in registers, and register-to register
instructions have three register names per instruction.

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Exercises

To measure memory efficiency, following are assumptions about all 4

instruction sets:
◮ All instructions are an integral number of 8-bit in length;
◮ The opcode is always 8 bits;
◮ Memory accesses use direct address
◮ The variables A, B, C, and D are initially in memory
a. Invent your own assembly language mnemonics and for each
architecture write the best equivalent assembly language code for
this high level language code:
A = B + C;
B = A + C;
D = A - B;
b. Assume the given code sequence is from a small, embedded
computer application, such as a microwave oven controller that uses
16-bit memory addresses and data operands. If a load-store
architecture is used, assume that it has 16 general-purpose registers.
Answer the following questions:

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Exercises

◮ How many instruction bytes are fetched?

◮ How many bytes of data are transferred from/to memory?
◮ Which architecture is the most efficient as measures in code size?
◮ Which architecture is most efficient as measured by total memory
traffic (code + data)
4. Specify the register contents and the flag status as the following
instructions are executed:
XRA A
MVI B, FFH
INR B
DCR A
ADD B
SUI 86H
ANA C
RST1

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Exercises
5. A system is designed to monitor the temperature of a furnace.
Temperature readings are recorded in 16 bits and stored in memory
locations starting at 7060H. The high-order byte is stored first and
the low-order byte is stored in the next consecutive memory
location.However, the low-order byte of all the temperature readings
is constant. Write 8085 ALP to transfer the high-order readings to
consecutive memory locations starting at 7080H and discard the
low-order bytes.Temperature Readings (H): 6745, 8745, 1F45, 3045,
8045, 7F45.
6. First set of data is stored from memory locations starting from
6155H to 6165H. Second set of data is stored from 6255H to
6265H. Write 8085 ALP to interchange the contents of memory
locations with each other.
(6155H) <————————> (6255H)
(6165H) <————————-> (6265H)
7. Download intel 8085 simulator (gnusim8085), using command:
$ sudo apt-get install gnusim8085 <enter>,
and sun the various simulation programs.
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Exercises

8. List the assembly language program generated by a compiler from

the following Fortran program. Assume integer values of one byte
size.
SUM = 0
SUM = SUM + A + B
DIF = DIF - C
SUM = SUM + DIF
9. List the assembly language program generated by the compiler for
the following Fortran IF statement:
IF(A - B) 10, 20, 30
The program branches to statement 10 if A-B <0; to statement 20
if A-B =0; and to statement 30 if A -B > 0.
10. Write a program to multiply two unsigned numbers.

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Bibliography

John L. Hennessy & David A. Patterson, Computer Architecture - A

qualitative approach, 3rd Edition, Elsevier (indian print).
PDP11 processor handbook, Digital Equipment Corporation, 1979.
http://bitsavers.trailing-edge.com/pdf/intel/MCS80/9800301D
8080 8085 Assembly Language Programming Manual May81.pdf
http://www.iitg.ernet.in/asahu/cs421/Lects/Lec04.pdf

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