The Devices:

MOS Transistor
Dynamics

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Overview - Transistor Dynamics

 Transistor capacitances
 Sub-Micron MOS Transistor
» Threshold Variations
» Velocity Saturation
» Sub-Threshold Conduction and Leakage
 Latchup
 Process Variations
 Future Perspectives
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Dynamic Behavior of MOS Transistor

•MOSFET is a majority carrier device

(unlike pn junction diode)
•Delays depend on the time to (dis)charge G

the capacitances between MOS terminals

•Capacitances originate from three sources: CGS CGD

•basic MOS structure (layout) S D

•charge present in the channel

•depletion regions of the reverse-biased CSB CGB CDB

pn-junctions of drain and source

B
•Capacitances are non-linear and vary with
the applied voltage

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 MOS Structure Capacitances

Gate Capacitance

•Gate isolated from channel by gate oxide

Cox   ox / tox
Gate Oxide
Gate
Polysilicon Field-Oxide
Source Drain
(SiO2)
n+ n+

•tox is very small <10nm p+ stopper

p-substrate

•Results in gate capacitance Cg

Bulk Contact

C g  CoxWL CROSS-SECTION of NMOS Transistor

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 The Gate Capacitance

EE415 VLSI Design

 The Gate Capacitance

Gate Capacitance depends on

•channel charge (non-linear)
•topology

Capacitance due to topology

•Source and drain extend below the gate oxide by xd
(lateral diffusion)
•Effective length of the channel Leff is shorter than the
drawn length by factor of 2xd
•Cause of parasitic overlap capacitance, CgsO, between
gate and source (drain)

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 The Gate Capacitance

Overlap Capacitance Channel Capacitance

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 The Channel Capacitance

Channel Capacitance has three components

•capacitance between gate and source, Cgs
•capacitance between gate and drain, Cgd
•capacitance between gate and bulk region, Cgb

Channel Capacitance values

•non-linear, depends on operating region
•averaged to simplify analysis

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 The Channel Capacitance

Different distributions of gate capacitance for varying

operating conditions

Most important regions in digital design: saturation and cut-off

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 Diffusion Capacitance
Bottom Plate Capacitance
Junction Depth

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 Capacitive Device Model

G
CGS = Cgs+ CgsO
CGS CGD
CGD = Cgd+ CgdO

CGB = Cgb S D

CSB = CSdiff CSB CGB CDB

CDB = CDdiff
B

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 Transistor Capacitance Values
for 0.25
Example: For an NMOS with L = 0.24 m,
W = 0.36 m, LD = LS = 0.625 m CGSO = CGDO = Cox xd W = Co W = 0.11 fF

CGC = Cox WL = 0.52 fF

Capacitance of both source and drain so Cgate_cap = CoxWL + 2CoW = 0.74 fF
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF

so Cdiffusion_cap = 0.90 fF Overlap capacitance

Cox Co Cj mj b Cjsw mjsw bsw

(fF/m2) (fF/m) (fF/m2) (V) (fF/m) (V)

NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9

PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9
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 Review: Sources of
Capacitance
Vout
Vin Vout2
CL

CG4
M2 M4
CGD12 CDB2 Vout
pdrain Vout2
Vin
ndrain
Cw
CDB1
M1 M3
CG3

intrinsic MOS transistor capacitances

extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance
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 Gate-Drain Capacitance: The
Miller Effect
 M1 and M2 are either in cut-off or in saturation.
 The floating gate-drain capacitor is replaced by a
capacitance-to-ground (gate-bulk capacitor).
V CGD1 Vout
Vout V
Vin 2CGB1
V
V
M1 M1
Vin

 A capacitor experiencing identical but opposite voltage

swings at both its terminals can be replaced by a
capacitor to ground whose value is two times the
original value
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 Drain-Bulk Capacitance: Keq’s
(for 2.5 m)
 We can simplify the diffusion capacitance calculations
even further by using a Keq to relate the linearized
capacitor to the value of the junction capacitance under
zero-bias
Ceq = Keq Cj0

high-to-low low-to-high
Keqbp Keqsw Keqbp Keqsw
NMOS 0.57 0.61 0.79 0.81
PMOS 0.79 0.86 0.59 0.7
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 Extrinsic (Fan-Out)
Capacitance
 The extrinsic, or fan-out, capacitance is the total gate
capacitance of the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)

 Simplification of the actual situation

» Assumes all the components of Cgate are between Vout and
GND (or VDD)
» Assumes the channel capacitances of the loading gates
are constant

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Layout of Two Chained Inverters
VDD
PMOS
1.125/0.25

1.2m
=2l
Out
In
Metal1

Polysilicon
0.125 0.5
NMOS
0.375/0.25 GND

W/L AD (m2) PD (m) AS (m2) PS (m)

NMOS 0.375/0.25 0.3 1.875 0.3 1.875
PMOS 1.125/0.25 0.7 2.375 0.7 2.375
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 Components of CL (0.25 m)

Expression Value (fF) Value (fF)

C Term HL LH
CGD1 2 Con Wn 0.23 0.23
CGD2 2 Cop Wp 0.61 0.61
CDB1 KeqbpnADnCj + KeqswnPDnCjsw 0.66 0.90
CDB2 KeqbppADpCj + KeqswpPDpCjsw 1.5 1.15
CG3 (2 Con)Wn + CoxWnLn 0.76 0.76
CG4 (2 Cop)Wp + CoxWpLp 2.28 2.28
Cw from extraction 0.12 0.12
CL  6.1 6.0
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 The Sub-Micron MOS Transistor

•Actual transistor deviates substantially from model

•Channel length becomes comparable to other device
parameters. Ex: depth of drain and source junctions
•Referred to as a short-channel device
•Influenced heavily by secondary effects
•Latchup problems

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 The Sub-Micron MOS Transistor

Secondary Effects:
•Threshold Variations
•Parasitic Resistances
•Velocity Saturation
•Mobility Degradation
•Sub-threshold Conduction

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 Threshold Variations
• Part of the region below gate is depleted by source and drain
fields, which reduce the threshold voltage for short channel.
• Similar effect is caused by increase in VDS, so threshold is
smaller with larger VDS
VT VT

Long-channel threshold Low VDS threshold

L VDS
Threshold as a function of Drain-induced barrier lowering
the length (for low VDS) lowers VT for short channel device
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 Variations in I-V Characteristics

•The velocity of the carriers is proportional to the electric field up to

a point.
•When electric field reaches a critical value, Esat, the velocity
saturates.
•When the channel length decreases, only a small VDS is needed for
saturation
•Causes a linear dependence of the saturation current wrt the gate
voltage (in contrast to squared dependence of long-channel device)
•Current drive cannot be increased by decreasing L

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 Velocity Saturation
u n (m/s)

usat = 105
Constant velocity

Constant mobility (slope = µ)

xc = 1.5 x (V/µm)
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 Velocity Saturation

 We assumed carrier velocity is proportional to E-field

» v = Elat = Vds/L
 At high fields, this ceases to be true
» Carriers scatter off atoms
» Velocity reaches vsat
– Electrons: 6-10 x 106 cm/s
– Holes: 4-8 x 106 cm/s
» Better model
μElat
v  vsat  μEsat
Elat
1
Esat

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 Voltage-Current Relation:
Velocity Saturation
For short channel devices
 Linear: When VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
(V) = 1/(1 + (V/(xcL))) is a measure of the degree of
velocity saturation

 Saturation: When VDS = VDSAT  VGS – VT

IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]

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 Velocity Saturation Effects
10
For short channel devices
and large enough VGS – VT

 VDSAT < VGS – VT so

the device enters
saturation before VDS
reaches VGS – VT and
0 operates more often in
saturation

 IDSAT has a linear dependence wrt VGS so a reduced

amount of current is delivered for a given control voltage
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 Velocity Saturation
1.5 0.5
VGS = 5

Linea r Dependence
1.0 VGS = 4

ID (mA)
I D (mA)

VGS = 3
0.5
VGS = 2
VGS = 1
0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0
VDS (V) VGS (V)
(a) I D as a function of VDS (b) ID as a function of VGS
(for VDS = 5 V).

Linear Dependence on VGS

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Short Channel I-V Plot (NMOS)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
X 10-4
2.5
Early Velocity
VGS = 2.5V
Saturation
2

VGS = 2.0V
1.5

Linear Saturation VGS = 1.5V

1

0.5 VGS = 1.0V

0
0
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0.5 1 1.5 2 2.5
VDS (V)
 Leakage Sources
 Subthreshold conduction
» Transistors can’t abruptly turn ON or OFF D
 Junction leakage D
» Reverse-biased PN junction diode current
S
 Gate leakage
S
» Tunneling through ultrathin gate dielectric

 Subthreshold leakage is the biggest source of DC

power dissipation in modern transistors

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 Sub-Threshold Conduction
The Slope Factor
-2
10

Linear qVGS
CD
10
-4
I D ~ I 0e nkT
, n  1
Cox
-6
10 Quadratic
S is VGS for ID2/ID1 =10
ID (A)

Slope S
-8
10

-10 Exponential
10

-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

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 Gate Leakage
 Carriers tunnel thorough very thin gate oxides
 Exponentially sensitive to tox and VDD

IG
S
» A and B are tech constants
» Greater for electrons
– So nMOS gates leak more
 Negligible for older processes (tox > 20 Å) From [Song01]

 Critically important at 65 nm and below (tox ≈ 10 Å=1nm)

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 Sub-Threshold ID vs VGS
D ID
qVGS
 qV
 DS 
I D  I 0e nkT 1  e kT 
 
VG +  
- VS

VDS from 0 to 0.5V

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VGS
 Sub-Threshold ID vs VDS
qVGS
 qV
 DS 
VD I I D  I 0e nkT 1  e kT 1  l  VDS 
D  
 
VG
VS
VGS from 0 to 0.3V

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 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

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 ID versus VDS
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

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 A unified model
for manual analysis

S D

VT0(V) (V0.5) VDSAT(V) k’(A/V2) l(V-1)

NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
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 A PMOS Transistor
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
-4
x 10 VGS = -1.0V
0

VGS = -1.5V
-0.2

-0.4
VGS = -2.0V
Assume all variables
ID (A)

-0.6 negative!
VGS = -2.5V

-0.8

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
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 Parasitic Resistances
Polysilicon gate
Drain
contact
G increase W LD

VGS,eff

W
S D

RS RD

LS , D
RS , D  RSQ  RC Drain
W
RSQ is the resistance per square
RC is the contact resistance
Silicide the bulk region
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 The Transistor as a Switch
ID
V GS = VD D

VGS  VT Rmid
Ron
S D R0

V DS
VDD/2 VDD

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 The Transistor as a Switch
VGS  VT
7
x105  Resistance inversely
Ron
6 S D proportional to W/L (doubling W
halves Ron)
5

4  For VDD>>VT+VDSAT/2, Ron

3
independent of VDD

2  Once VDD approaches VT, Ron

increases dramatically
1 VDD (V)
0
0.5 1 1.5 2 2.5 (for VGS = VDD,
VDS = VDD VDD/2)
VDD(V) 1 1.5 2 2.5
Ron (for W/L = 1)
NMOS(k) 35 19 15 13 For larger devices
PMOS (k) 115 55 38 31 divide Req by W/L
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 Summary of MOSFET Operating
Regions

 Strong Inversion VGS > VT

» Linear (Resistive) VDS < VDSAT
» Saturated (Constant Current) VDS  VDSAT
 Weak Inversion (Sub-Threshold) VGS  VT
» Exponential in VGS with linear VDS dependence

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 Latchup
VD D
VDD
Rnwell
p-source
+ + + +
p n n+ p p n+
n-well Rnwell

Rpsubs n-source Rpsubs

p-substrate

(a) Origin of latchup (b) Equivalent circuit

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 Fitting level-1 model
to short channel characteristics
Region of
matching
ID
Short-channel
I-V curve
VGS = 5 V

Long-channel
approximation

VDS = 5 V VDS

Select k’ and l such that best matching is obtained @ Vgs= Vds = VDD

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 SPICE MODELS
Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes Velocity

Saturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fitting

to measured devices

Level 4 (BSIM): Emperical - Simple and Popular

Berkeley Short-Channel IGFET Model

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 MAIN MOS SPICE PARAMETERS

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 SPICE Parameters for Parasitics

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 Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
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 Technology Evolution

 Semiconductor Industry Association

forecast
» Intl. Technology Roadmap for
Semiconductors

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 Process Variations

Devices parameters vary between runs and even on

the same die!
Variations in the process parameters , such as impurity concentration den-
sities, oxide thicknesses, and diffusion depths. These are caused by non-
uniform conditions during the deposition and/or the diffusion of the
impurities. Introduces variations in the sheet resistances and transistor
parameters such as the threshold voltage.
Variations in the dimensions of the devices, resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.

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 Impact of Device Variations

2.10
2.10

1.90

Delay (nsec)
Delay (nsec)

1.90

1.70
1.70

1.50 1.50
1.10 1.20 1.30 1.40 1.50 1.60 –0.90 –0.80 –0.70 –0.60 –0.50
Leff (in m) VTp (V)

Delay of Adder circuit as a function of variations in L and VT

EE415 VLSI Design

 So What?

 So what if transistors are not ideal?

» They still behave like switches.
 But these effects matter for…
» Supply voltage choice
» Logical effort
» Quiescent power consumption
» Pass transistors
» Temperature of operation
EE415 VLSI Design
 Parameter Variation
 Transistors have uncertainty in parameters
» Process: Leff, Vt, tox of nMOS and pMOS
» Vary around typical (T) values

fast
 Fast (F) SF
FF

» Leff: ____

pMOS
TT

» Vt: ____
» tox: ____ SS
FS

slow
 Slow (S): opposite
slow fast
 Not all parameters are independent nMOS

for nMOS and pMOS

EE415 VLSI Design
 Parameter Variation
 Transistors have uncertainty in parameters
» Process: Leff, Vt, tox of nMOS and pMOS
» Vary around typical (T) values

fast
 Fast (F) SF
FF

» Leff: short

pMOS
TT

» Vt: low
» tox: thin SS
FS

slow
 Slow (S): opposite
slow fast
 Not all parameters are independent nMOS

for nMOS and pMOS

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 Environmental Variation

 VDD and T also vary in time and space

 Fast:
» VDD: ____
» T: ____
Corner Voltage Temperature
F
T 1.8 70 C
S

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 Environmental Variation

 VDD and T also vary in time and space

 Fast:
» VDD: high
» T: low
Corner Voltage Temperature
F 1.98 0C
T 1.8 70 C
S 1.62 125 C

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 Process Corners

 Process corners describe worst case variations

» If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
» nMOS speed
» pMOS speed
» Voltage
» Temperature

EE415 VLSI Design

 Important Corners

 Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time

Power

Subthrehold
leakage

EE415 VLSI Design

 Important Corners

 Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthrehold F F F S
leakage

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 Future Perspectives

25 nm FINFET MOS transistor

EE415 VLSI Design

 Three-Dimensional
Integrated Circuits
 Multiple Layers of Active Devices
 Driven by
» Limited floorplanning choices
» Desire to integrate disparate technologies (GaAs, SOI, SiGe,
BiCMOS)
» Desire to integrate disparate signals (analog, digital, RF)
» Interconnect bottleneck
3D IC
2D IC
As small as 20µm

>500µm
EE415 VLSI Design
60