MOSFET Capacitances

Transistor Dimensions
Y

(n+) LD Gate LD (n+) W

LM
Gate
Source tox Oxide Drain
(p+) n+ L xj n+ (p+)

Substrate (p-Si)
• LM: mask length of the gate
• L: actual channel length
• LD: gate-drain overlap
• Y: typical diffusion length
• W: length of the source and drain diffusion region
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 Energy Band and Charge Diagrams
p type Si

Ec
Ei
Ef
Ev

27 CMOS Digital Integrated Circuits

Energy Band and Charge Diagrams n type Si

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 Effect of Vg on surface potential and
depletion width

Bulk fermi potential

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 Components of charge (C/cm2) in the MOS capacitor

Depletion Qdep

Qinv

Qacc
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 The total substrate charge, Qsub (C/cm2),
is the sum of Qacc, Qdep, and Qinv

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 MOS C–V CHARACTERISTICS
 The capacitance–voltage (C–V) measurement is a
powerful and commonly used method of
determining
• the gate oxide thickness,
• substrate doping concentration,
• threshold voltage, and
• flat-band voltage.

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 C–V curve measurement
 Apply DC bias voltage, Vg,
and a small sinusoidal
signal (1 kHz–10 MHz) to
the MOS capacitor,
 Measure the capacitive
current with an AC
ammeter.
 The capacitance is
calculated from
• icap/vac = ωC.

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 MOS Capacitance
 The capacitance in the MOS
theory is always the small-
signal capacitance

 Negative sign reflect the fact

that Vg is taken at the top
capacitor plate but Qsub is taken
at the bottom capacitor plate
(the body).

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 Accumulation
 In the accumulation region, the
MOS capacitor is just a simple
capacitor with capacitance Cox

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 Depletion
 The MOS capacitor consists of
two capacitors in series:
• the oxide capacitor, Cox, and
• the depletion-layer capacitor, Cdep.

 Under the AC small-signal

voltage, Wdep expands and
contracts slightly at the AC
frequency. Therefore, the AC
charge appears at the bottom of
the depletion layer.

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 Inversion
 In response to the AC signal, Qinv
increases and decreases at the AC
frequency.
 The inversion layer plays the role
of the bottom electrode of the
capacitor. Therefore, C reverts to
Cox in the inversion region.
That would require a ready source of
 This C–V curve is called the quasi- electrons, which can be provided by the
static C–V because Qinv can N region as shown above. PN junctions
respond to the AC signal as if the are always present in an MOS transistor.
frequency were infinitely low Therefore, the MOS transistor C–V
(static case). characteristics at all frequencies follow
the curve discussed earlier.

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 Inversion if junctions are not present
 The P-type substrate is an inefficient supplier of
electrons.
 The electrons are produced through thermal
generation at a very slow rate (for the same reason
the diode reverse leakage current is small.)
 Qinv cannot respond to the AC signal and remains
constant at its DC value. Instead, the AC signal
causes φs to oscillate around 2φF and causes Wdep
to expand and contract slightly around Wdmax.
 This change of Wdep can respond at very high
frequencies because it only involves the movement
of the abundant majority carriers. Consequently,
the AC charge exists at the bottom of the depletion
region.

38 CMOS Digital Integrated Circuits

  The result is a saturation of C at Vt as illustrated by the
lower curve. This curve is known as the capacitor C–V or
the high-frequency MOS capacitor C–V (HF C–V).

39 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Oxide Capacitances
• Parameters studied so far apply to steady-state (DC) behavior. We
need add parameters modeling transient behavior.
• MOSFET capacitances are distributed and complex. But, for
tractable modeling, we use lumped approximations.
• Two categories of capacitances: 1) oxide-related and 2) junction.
Inter-terminal capacitances result as follows:
Cgb D

Cgd Cdb

MOSFET
G B
(DC Model)

Cgs Csb

S
40 CMOS Digital Integrated Circuits
 MOSFET Capacitances
Overlap Capacitances
• Capacitances Cgb, Cgs, and Cgd
• Have the thin oxide as their dielectric
Overlap Capacitances
• Two special components of Cgs and Cgd caused by the lateral
diffusion under the gate and thin oxide
CGS(overlap) = CoxWLD
CGD(overlap) = CoxWLD
LD: lateral diffusion length
W : the width of channel
Cox = εox/tox: capacitance per unit area
• Theses overlap capacitances are bias independent and are added
components of Cgs and Cgd.

41 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Gate-to-Channel Charge Capacitances
• Remaining oxide capacitances not fixed, but are dependent in the
mode of operation of the transistor; referred to as being bias-
dependent.
• Capacitances between the gate and source, and the gate and drain
are really distributed capacitances between the gate and the
channel apportioned to the source and drain.
Cutoff
• No channel formation => Cgs = Cgd = 0. The gate capacitance to
the substrate
Cgb = Cox W L
Linear
• The channel has formed and the capacitance is from the gate to the
source and drain, not to the substrate. Thus Cgb=0 and
Cgs ≈ Cgd ≈ (Cox W L)/2
42 CMOS Digital Integrated Circuits
 MOSFET Capacitances
Gate-to-Channel Charge Capacitances (Cont.)
Saturation
• In saturation, the channel does not extend to the drain. Thus, Cgd=0 and
Cgs ≈ (Cox W L)*2/3
These capacitances as a function of VGS (and VDS) can be plotted Next
slide. Note that the capacitance seen looking into the gate is Cg:
CoxW( 2L/3+2LD) Cg= Cgb+ Cgs + Cgd CoxW(L+2LD)
• For manual calculations, we approximate Cg as its maximum value.

Capacitance Cut-off Linear Saturation

Cgb(total) CoxWL 0 0
Cgd(total) CoxWLD CoxWL/2+CoxWLD CoxWLD
Cgs(total) CoxWLD CoxWL/2+ CoxWLD 2CoxWL/3+ CoxWLD
• This component of input capacitance is directly proportional to L and
W and inversely proportional to tox.

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 Variation of the distributed (gate-to-
channel) oxide capacitances as functions of
VGS

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 Variation of the distributed (gate-to-
channel) oxide capacitances

CGC as a function of VGS CGC as a function of degree

(with VDS=0) of satuaration

45 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Gate-to-Channel Charge Capacitances (Cont.)

Junction Capacitances
• Capacitances associated with the source and the drain
• Capacitances of the reversed biased substrate-to-source and
substrate-to-drain p-n junctions.

• Lumped, but if the diffusion used as a conductor of any length,

both its capacitance and resistance need to be modeled in a way
that tends more toward a distributed model which is used for
resistive interconnect.

46 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance Geometry
The Geometry Y

xj
G
D
W D- Drain
G - Gate

Junction between p substrate and n+ drain (Bottom)

Area: W(Y+xj) = AD

Junction between p+ channel stop and n+ drain (Sidewalls)

Area: xj(W+2Y) = xj PD
47 CMOS Digital Integrated Circuits
 MOSFET Capacitances
Junction Capacitance Geometry (Continued)
• Since the diffusion also enters into contacts at a minimum here,
actual geometries will be more complex, but the fundamental
principles remain.

• Why separate bottom and sides? The carrier concentration in the

channel stop area is an order of magnitude higher (~10NA) than in
the substrate (NA). This results in a higher capacitance for the
sidewalls.

48 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance Geometry (Continued)
• The bottom and channel edge can be treated together via AD in the
SPICE model but often channel edge either ignored or included in
PD.

• All other areas are treated together via the length of the perimeter
PD in the SPICE model. The capacitance in this case is per meter
since dimension xj is incorporated in the capacitance value.

• Same approach for source.

49 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance/Unit Area
• Two junction capacitances per unit area for each distinct diffusion
region, the bottom capacitance and the sidewall. Equations are the
same, but values different.
• Thus, we use a single value Cj which is the capacitance of a p-n
junction diode.
• Recall that most of the depletion region in a diode lies in the region
with the lower impunity concentration, in this case, the p-type
substrate.
• Finding the depletion region thickness in term of basic physical
parameters and V the applied voltage (note that V is negative since
the junction is reversed biased).
2 S i N A  N D
xd   0  V 
q NAND

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 MOSFET Capacitances
Junction Capacitance/Unit Area (Continued)
• The junction potential in this equation is
kT  N A N D 
0  ln  2

q  ni 
The total depletion region charge can be calculated by using xd:
NAND NAND
Q j  Aq x d  A 2 S i q  0  V 
N A ND N A ND
The capacitance found by differentiating Qj with respect to V to
give: dQ j AC j 0
Cj (V )   1/ 2
dV (1V / 0)
with
S q  NAND  1
C j0  i
 
2  N A  N D  0
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 MOSFET Capacitances
Junction Capacitance - Approximations
Approximation for Manual Calculations
• The voltage dependence of Cj(V) makes manual calculations
difficult.

• An equivalent large-signal capacitance for a voltage change from

V1 to V2 can be defined as

Ceq = Q/V = (Qj(V2) - Qj(V1)) / (V2 - V1)

52 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance - Approximations
Approximation for Manual Calculations

Ceq = Q/V = (Qj (V2) – Qj (V1)) /(V2-V1)

for abrupt
junction

53 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance - Approximations
Approximation for Manual Calculations

• The formula of this equivalent large-signal capacitance may be

written as :
Ceq =ACj0Keq

where Keq (0<Keq<1) is the voltage equivalence factor,

K eq 
2 0
 0 V 2   0 V 1 
V 1 V 2

54 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance - Approximations


55 CMOS Digital Integrated Circuits

 MOSFET Capacitances
Junction Capacitance - Approximations

Approximation for Manual Calculations- side wall

junctions
• The formula of this equivalent large-signal capacitance may be
written as :
Cjsw =Cj0swxj

• The voltage equivalent factor for side wall junctions is given by

K eq, sw 
2  0, sw
V1V 2
 0, sw  V 2   0, sw  V 1 
Equivalent large-signal junction capacitance Ceq(SW) for a sidewall
of length (perimeter) P can be calculated as

56 CMOS Digital Integrated Circuits

 Summary
• Full scaling (constant field scaling) better than constant voltage
scaling if the power supply value can be changed.
• Scaling is subject to small geometry effects that create new
limitations and requires new modeling approaches.
• The short-channel effect, narrow-channel effect, mobility
degradation, and subthreshold conduction all bring new
complications to the modeling of the MOSFET.
• Geometric and capacitance relationships developed permit us to
calculate:
the two overlap capacitances due to lateral diffusion,
the three transistor-mode dependent oxide capacitances
the voltage-dependent bottom and sidewall junction
capacitances for the sources and drain, and
fixed capacitance source and drain capacitances values for a
voltage transition in manual calculations.

57 CMOS Digital Integrated Circuits

 Oxide Capacitance
Find capacitances in terms of Cox for NMOS with VT =1V.
Assume area as unity
VGS VDS CGS CGD Region of
operation
2V 5V
3V 2V

4V 5V
-2V 5.5V

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 Oxide Capacitance
Find capacitances in terms of Cox for NMOS with VT =1V.
Assume area as unity
VGS VDS CGS CGD Region of
operation
2V 5V (2/3)Cox 0 Saturation
3V 2V (2/3)Cox 0 Edge of
saturation
4V 5V (2/3)Cox 0 Saturation
-2V 5.5V 0 0 Cutoff

59 CMOS Digital Integrated Circuits

 Oxide Capacitance
Find capacitances in terms of Cox for PMOS with VT = -1V.
Assume area as unity
VGS VDS CGS CGD Region of
operation
-2V -5V
-3V -2V

-4V -5V
-2V 5.5V

60 CMOS Digital Integrated Circuits

 Oxide Capacitance
Find capacitances in terms of Cox for PMOS with VT = -1V.
Assume area as unity
VGS VDS CGS CGD Region of
operation
-2V -5V (2/3)Cox 0 Saturation
-3V -2V (2/3)Cox 0 Edge of
Saturation
-4V -5V (2/3)Cox 0 Saturation
-2V 5.5V 0 0 cutoff

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