GLA UNIVERSITY Mathura, Uttar Pradesh, India
GLA UNIVERSITY Mathura, Uttar Pradesh, India
GLA UNIVERSITY Mathura, Uttar Pradesh, India
Interrupt driven I/ O
I/O device interrupts the processor and initiate
data transfer
Direct memory access
Data transfer is achieved by bypassing the
microprocessor
3
Dealing with I/O Devices
They are assigned a 16-bit address within the address range of the 8085.
The exchange of data with these devices follows the transfer of data with memory. The user uses
the same instructions used for memory.
This is called memory-mapped I/O.
I/O devices are assigned a “port number” within the 8-bit address range of 00H to FFH.
The user in this case would access these devices using the IN and OUT instructions only.
This is called I/O-mapped I/O or Peripheral-mapped I/O.
4
Memory mapping I/O mapping
16 bit memory address are provided for I/O 8-bit I/O port address is provided for I/O
devices devices
The I/O ports or peripherals can be treated like Only IN and OUT instructions can be used for
memory locations and so all instructions data transfer between I/O device and processor
related to memory can be used for data
transmission between I/O device and processor
Data can be moved from any register to ports Data transfer takes place only between
and vice versa accumulator and ports
When memory mapping is used for I/O Full memory space can be used for addressing
devices, full memory address space cannot be memory.
used for addressing memory.
Suitable for systems which require large
Useful only for small systems where memory capacity
memory requirement is less
5
DMA Controller 8237/57
CPU having the control over the bus:
When DMA operates:
8237 Modes
The 8257 processor works on two modes:
1) Master mode;
2) Slave mode;
An active-low input which enables the I/O Read or I/O Write input when the 8237 is
being read or programmed in the "slave" mode.
In the "master" mode. CS is automatically disabled to prevent the chip from selecting
itself while performing the DMA function.
9
DMA Controller 8237
The Intel 8237 is a 4-channel Direct Memory Access (DMA) controller. It is specifically
designed to simplify the transfer of data at high speeds for the Intel® microcomputer
systems. Its primary function is to generate, upon a peripheral request, a sequential
memory address which will allow the peripheral to read or write data directly to or from
memory. Acquisition of the system bus in accomplished via the CPU's hold function.
The 8257 has priority logic that resolves the peripherals requests and issues a
composite hold request to the CPU. It maintains the OMA cycle count for each channel
and outputs a control signal Jo notify the peripheral that the programmed number of
OMA cycles is complete. Other output control signals simplify sectored data transfers.
The 8237 represents a significant savings in component count for DMA-based
microcomputer systems and greatly simplifies the transfer of data at high speed
between peripherals and memories.
Functional Block Diagram of 8237:
The functional blocks of 8237 are data bus buffer, read/write logic, control
logic, priority resolver and four numbers of DMA channels.
Each channel has two programmable 16-bit registers named as address
register and count register.
1
Block diagram
The 8257 is a programmable. Direct Memory Access (DMA) device which, when coupled with a single Intel®
8212 I/O port device, provides a complete four-channels DMA controller for use in Intel® microcomputer
systems. After being initialized by software, the 8237 could transfer a block of data, containing up to 16.384
bytes, between memory and a peripheral device directly, without further intervention required of the CPU.
Upon receiving a DMA transfer request from an enabled peripheral, the 8257:
1
Programmable DMA controller. (a) Block diagram and (b) pin-out.
13
8237 – Block Diagram
1. DMA Channels
3. Read/Write Logic
4. Control Logic
1. DMA Channels
# Four separate DMA channels (CH-0 to CH-3)
D0 – D 7
3.
#A –A
Read/Write Logic
0 3
# IOR, IOW
# RESET
#CLK
# CS
4. Control Logic
# ADSTB (Address Strobe):
# TC (Terminal Count)
2
DRQ0−DRQ3
DACKo − DACK3
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of
the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA
address register or terminal count register. In the master mode, it is used to load
the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA
channels.
Ao - A3
These are the four least significant address lines. In the slave
mode, they act as an input, which selects one of the registers to
be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
CS
A4 - A7
These are the higher nibble of the lower byte address generated
by DMA in the master mode.
READY
HRQ
This signal is used to receive the hold request signal from the output device.
In the slave mode, it is connected with a DRQ input line 8257. In Master
mode, it is connected with HOLD input of the CPU.
HLDA
MEMR
It is the low memory read signal, which is used to read the data from the
addressed memory locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data
to the addressed memory location during DMA write operation.
ADST
AEN
TC
Vcc
31