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ORCIDAtsushi Kurokawa
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2020 – today
- 2023
[j35]Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa:
A parabolic spiral coil transmitter with uniform magnetic field for smart devices. IEICE Electron. Express 20(1): 20220492 (2023)- [j34]Taisei Arima, Shigeru Hidaka, Ryosuke Watanabe, Tomoya Akasaka, Atsushi Kurokawa, Toshiki Kanamoto:
A thermally optimizing method of thin film resistor trimming with machine learning. IEICE Electron. Express 20(5): 20230014 (2023) - [j33]Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa:
Bayesian neural network based inductance calculations of wireless power transfer systems. IEICE Electron. Express 20(5): 20230030 (2023) - [j32]Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa:
Electronic component placement optimization for heat measures of smartglasses. IEICE Electron. Express 20(6): 20230011 (2023) - 2022
- [j31]Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa:
Receiver coil built into belt for heat dissipation of watch-type smart devices. IEICE Electron. Express 19(3): 20210497 (2022) - [j30]Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa:
A bernoulli spiral coil transmitter for charging various small electronic devices. IEICE Electron. Express 19(23): 20220419 (2022) - [c31]Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa:
Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems. GCCE 2022: 222-223 - [c30]Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa:
A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers. GCCE 2022: 224-225 - [c29]Ryosuke Watanabe, Shigeru Hidaka, Tomoya Akasaka, Shota Kajiya, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto:
Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules. MWSCAS 2022: 1-4 - 2021
- [j29]Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa:
Effective methods to promote heat dissipation of wrist wearables. IEICE Electron. Express 18(5): 20210017 (2021) - [c28]Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara:
An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. GCCE 2021: 909-910 - 2020
- [j28]Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto
, Ryosuke Watanabe, Atsushi Kurokawa:
Thermal placement on PCB of components including 3D ICs. IEICE Electron. Express 17(3): 20190737 (2020) - [j27]Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai:
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. IEICE Electron. Express 17(14): 20200198 (2020) - [j26]Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa:
Thermal Model and Countermeasures for Future Smart Glasses. Sensors 20(5): 1446 (2020) - [c27]Koutaro Hachiya, Atsushi Kurokawa:
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation. DATE 2020: 290-293
2010 – 2019
- 2019
- [c26]Koutaro Hachiya, Atsushi Kurokawa:
Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC. 3DIC 2019: 1-6 - [c25]Motoki Ishizaki, Atsushi Kurokawa:
Advantages and Characteristics of a WPT System with a Resonant Wired-2-Coil Repeater. APWCS 2019: 1-5 - [c24]Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai:
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC 2019: 134-143 - [c23]Motoki Ishizaki, Atsushi Kurokawa:
Repeater Coil Connections for WPT System with Wired Three Coils. GCCE 2019: 612-613 - [c22]Kodai Matsuhashi, Atsushi Kurokawa:
Thermal Countermeasures of Glass Wearable Devices. ICCE-TW 2019: 1-2 - [c21]Motoki Ishizaki, Atsushi Kurokawa:
Power Transfer System Combining Wireless Resonators and Wired Three-Coil Repeater. ISCAS 2019: 1-4 - [c20]Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai:
A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. MWSCAS 2019: 1085-1088 - 2017
- [c19]Kaoru Furumi, Masashi Imai, Atsushi Kurokawa:
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. ISQED 2017: 283-288 - 2015
- [j25]Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa:
Structure optimization for timing in nano scale FinFET. IEICE Electron. Express 12(9): 20150297 (2015) - [j24]Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
Signal Propagation Delay Model in Vertically Stacked Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2614-2624 (2015) - [c18]Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa:
Clock skew reduction for stacked chips using multiple source buffers. ISCIT 2015: 327-330 - [c17]Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. ISQED 2015: 519-523 - 2014
- [j23]Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue:
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1059-1074 (2014) - [c16]Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa:
Modeling of substrate contacts in TSV-based 3D ICs. 3DIC 2014: 1-4 - [c15]Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa:
Impact of on-chip interconnects on vertical signal propagation in 3D ICs. APCCAS 2014: 607-610 - [c14]Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa:
Effect of substrate contacts on reducing crosstalk noise between TSVs. APCCAS 2014: 763-766 - 2013
- [c13]Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. ISCAS 2013: 1712-1715 - 2012
- [j22]Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. J. Circuits Syst. Comput. 21(6) (2012) - [c12]Masa-Aki Fukase, Atsushi Kurokawa, Kouhei Ichinohe, Tatsuya Takaki:
Optimum design of the execution stage of embedded processors. ISCIT 2012: 533-537 - 2011
- [j21]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue:
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(5): 1201-1209 (2011) - [c11]Masa-Aki Fukase, Harunobu Uchiumi, Kazuki Narita, Tatsuya Takaki, Naomichi Mimura, Kohei Ichinohe, Tomoaki Sato, Atsushi Kurokawa:
Development of a next generation ubiquitous processor chip. ISPACS 2011: 1-4 - 2010
- [j20]Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto:
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. 93-C(3): 388-392 (2010) - [j19]Kazuyuki Ooya, Yuji Takashima, Atsushi Kurokawa:
Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(9): 1585-1593 (2010) - [j18]Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 250-260 (2010)
2000 – 2009
- 2009
- [j17]Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato:
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 990-997 (2009) - [j16]Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue:
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2531-2539 (2009) - [j15]Yuji Takashima, Kazuyuki Ooya, Atsushi Kurokawa:
Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2962-2970 (2009) - [j14]Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto:
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3016-3023 (2009) - 2008
- [j13]Atsushi Kurokawa, Hiroshi Fujita, Tetsuya Ibe:
Prevention in a Chip of EMI Noise Caused by X'tal Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1077-1083 (2008) - 2007
- [c10]Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue:
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC 2007: 565-570 - 2006
- [j12]Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue:
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 840-846 (2006) - [j11]Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda:
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 847-855 (2006) - [j10]Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue:
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 856-864 (2006) - [j9]Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto:
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3666-3670 (2006) - [c9]Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye:
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD 2006: 47-53 - 2005
- [j8]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao:
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(10): 2562-2569 (2005) - [j7]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3180-3187 (2005) - [j6]Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue:
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3367-3374 (2005) - [j5]Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao:
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3412-3420 (2005) - [j4]Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda:
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3453-3462 (2005) - [j3]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3471-3478 (2005) - [c8]Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki:
Challenge: variability characterization and modeling for 65- to 90-nm processes. CICC 2005: 593-599 - [c7]Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue:
Effective capacitance for gate delay with RC loads. ISCAS (3) 2005: 2795-2798 - [c6]Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED 2005: 153-158 - [c5]Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda:
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED 2005: 586-591 - 2004
- [c4]Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda:
DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC 2004: 517-522 - [c3]Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda:
Efficient capacitance extraction method for interconnects with dummy fills. CICC 2004: 485-488 - 2003
- [j2]Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda:
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 841-845 (2003) - [j1]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2933-2941 (2003) - [c2]Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximate formulae approach for efficient inductance extraction. ASP-DAC 2003: 143-148 - [c1]Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto:
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC 2003: 149-155
Coauthor Index
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