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ORCID53rd DAC 2016: Austin, TX, USA
- Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016. ACM 2016, ISBN 978-1-4503-4236-0
- Li Du, Chun-Chen Liu, Adrian Tang, Yan Zhang, Yilei Li, Kye Cheung, Mau-Chung Frank Chang
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Invited - Airtouch: a novel single layer 3D touch sensing system for human/mobile devices interactions. 1:1-1:6 - Chun-Chen Liu, Yen-Hsiang Wang, Yilei Li, Chien-Heng Wong, Tien Pei Chou, Young-Kai Chen, M.-C. Frank Chang:
Invited - A 2.2 GHz SRAM with high temperature variation immunity for deep learning application under 28nm. 2:1-2:6 - Ting-Chou Lu, Li-Ren Huang, Yu Lee, Kun-Ju Tsai, Yu-Te Liao, Nai-Chen Cheng, Yuan-Hua Chu, Yi-Hsing Tsai, Fang-Chu Chen, Tzi-cker Chiueh:
Invited - Wireless sensor nodes for environmental monitoring in internet of things. 3:1-3:5 - Xinnian Zheng, Lizy K. John, Andreas Gerstlauer:
Accurate phase-level cross-platform power and performance estimation. 4:1-4:6 - Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang:
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. 5:1-5:6 - Yang Song, Kambiz Samadi, Bill Lin:
Single-tier virtual queuing: an efficacious memory controller architecture for MPSoCs with multiple realtime cores. 6:1-6:6 - Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. 7:1-7:6 - Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. 8:1-8:6 - Fa Wang, Xin Li:
Correlated Bayesian Model Fusion: efficient performance modeling of large-scale tunable analog/RF integrated circuits. 9:1-9:6 - Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li:
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. 10:1-10:6 - Honghuang Lin, Peng Li:
Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization. 11:1-11:6 - Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel:
Reliability-aware design to suppress aging. 12:1-12:6 - Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis:
Statistical fault injection for impact-evaluation of timing errors on application performance. 13:1-13:6 - Daniele Jahier Pagliari, Enrico Macii, Massimo Poncino:
Serial T0: approximate bus encoding for energy-efficient transmission of sensor signals. 14:1-14:6 - Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Designing approximate circuits using clock overgating. 15:1-15:6 - Jason Cong, Muhuan Huang, Di Wu, Cody Hao Yu:
Invited - Heterogeneous datacenters: options and opportunities. 16:1-16:6 - Luca P. Carloni:
Invited - The case for embedded scalable platforms. 17:1-17:6 - Wei Wen, Chunpeng Wu, Yandan Wang, Kent W. Nixon, Qing Wu, Mark Barnell, Hai Li, Yiran Chen:
A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip. 18:1-18:6 - Miao Hu, John Paul Strachan, Zhiyong Li, Emmanuelle M. Grafals, Noraica Davila, Catherine Graves, Sity Lam, Ning Ge, Jianhua Joshua Yang, R. Stanley Williams:
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication. 19:1-19:6 - Azalia Mirhoseini, Bita Darvish Rouhani, Ebrahim M. Songhori, Farinaz Koushanfar:
Perform-ML: performance optimized machine learning by platform and content aware customization. 20:1-20:6 - Yong Shim, Abhronil Sengupta, Kaushik Roy:
Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications. 21:1-21:6 - Reza Hajisheykhi, Mohammad Roohitavaf, Ali Ebnenasir, Sandeep S. Kulkarni:
A framework for verification of SystemC TLM programs with model slicing: a case study. 22:1-22:6 - Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang:
Design partitioning for large-scale equivalence checking and functional correction. 23:1-23:6 - Doowon Lee, Tom Kolan, Arkadiy Morgenshtein, Vitali Sokhin, Ronny Morad, Avi Ziv, Valeria Bertacco:
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification. 24:1-24:6 - Mojtaba Ebrahimi, Mohammad Hadi Moshrefpour, Mohammad Saber Golanbari, Mehdi Baradaran Tahoori:
Fault injection acceleration by simultaneous injection of non-interacting faults. 25:1-25:6 - Siam U. Hussain, Farinaz Koushanfar:
Privacy preserving localization for smart automotive systems. 26:1-26:6 - Tiana A. Rakotovao, Julien Mottin, Diego Puschini, Christian Laugier:
Integration of multi-sensor occupancy grids into automotive ECUs. 27:1-27:6 - Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Formal reliability analysis of switched ethernet automotive networks under transient transmission errors. 28:1-28:6 - Carles Hernández, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla:
Random modulo: a new processor cache design for real-time critical systems. 29:1-29:6 - Taeyoung Kim, Zeyu Sun, Chase Cook, Hengyang Zhao, Ruiwen Li, Daniel Wong, Sheldon X.-D. Tan:
Invited - Cross-layer modeling and optimization for electromigration induced reliability. 30:1-30:6 - Deepashree Sengupta, Vivek Mishra, Sachin S. Sapatnekar:
Invited - Optimizing device reliability effects at the intersection of physics, circuits, and architecture. 31:1-31:6 - Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
Invited - Cross-layer approaches for soft error modeling and mitigation. 32:1-32:6 - Geoff V. Merrett:
Invited - Energy harvesting and transient computing: a paradigm shift for embedded systems? 33:1-33:2 - Xia Zhao, Sheng Ma, Yuxi Liu, Lieven Eeckhout, Zhiying Wang:
A low-cost conflict-free NoC for GPGPUs. 34:1-34:6 - Kevin J. M. Martin, Mostafa Rizk, Martha Johanna Sepúlveda, Jean-Philippe Diguet:
Notifying memories: a case-study on data-flow applications with NoC interfaces implementation. 35:1-35:6 - Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan:
Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling. 36:1-36:6 - Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li:
DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. 37:1-37:6 - Kshitij Bhardwaj, Steven M. Nowick:
Achieving lightweight multicast in asynchronous networks-on-chip using local speculation. 38:1-38:6 - Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha:
PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. 39:1-39:6 - Hua-Yu Chang, Iris Hui-Ru Jiang:
Multiple patterning layout decomposition considering complex coloring rules. 40:1-40:6 - Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Redundant via insertion for multiple-patterning directed-self-assembly lithography. 41:1-41:6 - Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak:
Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. 42:1-42:6 - Vivek Mishra, Sachin S. Sapatnekar:
Predicting electromigration mortality under temperature and product lifetime specifications. 43:1-43:6 - Meng Li, Ye Wang, Michael Orshansky:
A Monte Carlo simulation flow for SEU analysis of sequential circuits. 44:1-44:6 - Xin Huang, Valeriy Sukharev, Zhongdong Qi, Taeyoung Kim, Sheldon X.-D. Tan:
Physics-based full-chip TDDB assessment for BEOL interconnects. 45:1-45:6 - Florian Kriebel, Semeen Rehman, Muhammad Shafique, Jörg Henkel:
ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading. 46:1-46:6 - Alok Prakash, Hussam Amrouch, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Improving mobile gaming performance through cooperative CPU-GPU thermal management. 47:1-47:6 - Moslem Didehban, Aviral Shrivastava:
nZDC: a compiler technique for near zero silent data corruption. 48:1-48:6 - Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo:
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. 49:1-49:6 - Chun-Hao Kao, Sheng-Wei Cheng, Pi-Cheng Hsiu:
Similarity-based wakeup management for mobile systems in connected standby. 50:1-50:6 - Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty:
Synergistic timing speculation for multi-threaded programs. 51:1-51:6 - Chung-Wei Lin, Huafeng Yu:
Invited - Cooperation or competition?: coexistence of safety and security in next-generation ethernet-based automotive networks. 52:1-52:6 - Mischa Möstl, Daniel Thiele, Rolf Ernst:
Invited - Towards fail-operational ethernet based in-vehicle networks. 53:1-53:6 - Xin Zhan, Peng Li, Edgar Sánchez-Sinencio:
Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization. 54:1-54:6 - Ji Li, Jeffrey Draper:
Accelerating soft-error-rate (SER) estimation in the presence of single event transients. 55:1-55:6 - Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A fast simulator for the analysis of sub-threshold thermal noise transients. 56:1-56:6 - Zhuo Feng:
Spectral graph sparsification in nearly-linear time leveraging efficient spectral perturbation analysis. 57:1-57:6 - Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. 58:1-58:6 - Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang:
Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning. 59:1-59:6 - Grace Li Zhang, Bing Li, Ulf Schlichtmann:
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. 60:1-60:6 - Kun Young Chung, Andrew B. Kahng, Jiajia Li:
Comprehensive optimization of scan chain timing during late-stage IC implementation. 61:1-61:6 - Phillip Stanley-Marbell, Martin C. Rinard:
Reducing serial I/O power in error-tolerant applications by efficient lossy encoding. 62:1-62:6 - Jisung Park, Jaeyong Jeong, Sungjin Lee, Youngsun Song, Jihong Kim:
Improving performance and lifetime of NAND storage systems using relaxed program sequence. 63:1-63:6 - Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei:
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. 64:1-64:6 - Mengjie Mao, Wujie Wen, Xiaoxiao Liu, Jingtong Hu, Danghui Wang, Yiran Chen, Hai Li:
TEMP: thread batch enabled memory partitioning for GPU. 65:1-65:6 - Sharad Malik, Pramod Subramanyan:
Invited - Specification and modeling for systems-on-chip security verification. 66:1-66:6 - Shreyas Sen:
Invited - Context-aware energy-efficient communication for IoT sensor nodes. 67:1-67:6 - Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. 68:1-68:6 - Victor M. van Santen, Hussam Amrouch, Javier Martín-Martínez, Montserrat Nafría, Jörg Henkel:
Designing guardbands for instantaneous aging effects. 69:1-69:6 - Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen:
NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation. 70:1-70:6 - Cheng Zhuo, Kassan Unda, Yiyu Shi, Wei-Kai Shih:
A novel cross-layer framework for early-stage power delivery and architecture co-exploration. 71:1-71:6 - Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel:
A high-resolution side-channel attack on last-level cache. 72:1-72:6 - Ebrahim M. Songhori, Shaza Zeitouni, Ghada Dessouky, Thomas Schneider, Ahmad-Reza Sadeghi, Farinaz Koushanfar:
GarbledCPU: a MIPS processor for secure computation in hardware. 73:1-73:6 - Yao Wang, Andrew Ferraiuolo, Danfeng Zhang, Andrew C. Myers, G. Edward Suh:
SecDCP: secure dynamic cache partitioning for efficient timing channel protection. 74:1-74:6 - Pengfei Qiu, Yongqiang Lyu, Jiliang Zhang, Xingwei Wang, Di Zhai, Dongsheng Wang, Gang Qu:
Physical unclonable functions-based linear encryption against code reuse attacks. 75:1-75:6 - Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. 76:1-76:6 - Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
Match-making for monolithic 3D IC: finding the right technology node. 77:1-77:6 - Kristof Blutman, Ajay Kapoor, Jacinto Garcia Martinez, Hamed Fatemi, José Pineda de Gyvez:
Lower power by voltage stacking: a fine-grained system design approach. 78:1-78:5 - Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Leveraging FDSOI through body bias domain partitioning and bias search. 79:1-79:6 - I-Peng Wu, Hung-Chih Ou, Yao-Wen Chang:
QB-trees: towards an optimal topological representation and its applications to analog layout designs. 80:1-80:6 - Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo:
Timing-driven cell placement optimization for early slack histogram compression. 81:1-81:6 - Gang Wu, Yue Xu, Dean Wu, Manoj Ragupathy, Yu-Yen Mo, Chris C. N. Chu:
Flip-flop clustering by weighted K-means algorithm. 82:1-82:6 - Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young:
Legalization algorithm for multiple-row height standard cell design. 83:1-83:6 - Kai-Han Tseng, Yao-Wen Chang, Charles C. C. Liu:
Minimum-implant-area-aware detailed placement with spacing constraints. 84:1-84:6 - Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental layer assignment for critical path timing. 85:1-85:6 - Rajesh Jayashankara Shridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy:
Catching the flu: emerging threats from a third party power management unit. 86:1-86:6 - S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
Information dispersion for trojan defense through high-level synthesis. 87:1-87:6 - Theodore Winograd, Hassan Salmani, Hamid Mahmoodi, Kris Gaj, Houman Homayoun:
Hybrid STT-CMOS designs for reverse-engineering prevention. 88:1-88:6 - Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark M. Tehranipoor:
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs. 89:1-89:6 - Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger:
PLL to the rescue: a novel EM fault countermeasure. 90:1-90:6 - Ferdinand Brasser, Kasper Bonne Rasmussen, Ahmad-Reza Sadeghi, Gene Tsudik:
Remote attestation for low-end embedded devices: the prover's perspective. 91:1-91:6 - Tseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, Shuo-Han Chen:
Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory. 92:1-92:6 - Marjan Asadinia, Majid Jalili, Hamid Sarbazi-Azad:
BLESS: a simple and efficient scheme for prolonging PCM lifetime. 93:1-93:6 - Hongwen Dai, Chao Li, Huiyang Zhou, Saurabh Gupta, Christos Kartsaklis, Mike Mantor:
A model-driven approach to warp/thread-block level GPU cache bypassing. 94:1-94:6 - Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler:
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. 95:1-95:6 - Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique, Jörg Henkel:
An area-efficient consolidated configurable error correction for approximate hardware accelerators. 96:1-96:6 - Matthew Vilim, Henry Duwe, Rakesh Kumar:
Approximate bitcoin mining. 97:1-97:6 - Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. 98:1-98:6 - Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel:
Invited - Cross-layer approximate computing: from logic to architectures. 99:1-99:6 - Matthias Jung, Deepak M. Mathew, Christian Weis, Norbert Wehn:
Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM. 100:1-100:4 - Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. 101:1-101:6 - Florin Burcea, Husni M. Habal, Helmut E. Graeb:
Procedural capacitor placement in differential charge-scaling converters by nonlinearity analysis. 102:1-102:6 - Abhilash Karnatakam Nagabhushana, Haibo Wang:
A novel time and voltage based SAR ADC design with self-learning technique. 103:1-103:6 - Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi:
Extended statistical element selection: a calibration method for high resolution in analog/RF designs. 104:1-104:6 - Soheil Hashemi, R. Iris Bahar, Sherief Reda:
A low-power dynamic divider for approximate applications. 105:1-105:6 - Farhana Sharmin Snigdha, Deepashree Sengupta, Jiang Hu, Sachin S. Sapatnekar:
Optimal design of JPEG hardware under the approximate computing paradigm. 106:1-106:6 - Alireza Shafaei, Hassan Afzali-Kusha, Massoud Pedram:
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework. 107:1-107:6 - Advait Madhavan, Timothy Sherwood, Dmitri B. Strukov:
Energy efficient computation with asynchronous races. 108:1-108:6 - Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei:
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. 109:1-109:6 - Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li:
DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. 110:1-110:6 - Hongyan Zhang, Lars Bauer, Jörg Henkel:
Resource budgeting for reliability in reconfigurable architectures. 111:1-111:6 - Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis:
An MPSoC for energy-efficient database query processing. 112:1-112:6 - Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala:
Practical statistical static timing analysis with current source models. 113:1-113:6 - Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya:
Statistical path tracing in timing graphs. 114:1-114:6 - Hiromitsu Awano, Takashi Sato:
Efficient transistor-level timing yield estimation via line sampling. 115:1-115:6 - Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran:
A distributed timing analysis framework for large designs. 116:1-116:6 - Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli:
An MIG-based compiler for programmable logic-in-memory architectures. 117:1-117:6 - Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Islam Khan, Sayeef S. Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan:
Nonvolatile memory design based on ferroelectric FETs. 118:1-118:6 - Hang Zhang, Xuhao Chen, Nong Xiao, Fang Liu:
Architecting energy-efficient STT-RAM based register file on GPGPUs via delta compression. 119:1-119:6 - Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao:
PDS: pseudo-differential sensing scheme for STT-MRAM. 120:1-120:6 - Tigist Abera, N. Asokan, Lucas Davi, Farinaz Koushanfar, Andrew Paverd, Ahmad-Reza Sadeghi, Gene Tsudik:
Invited - Things, trouble, trust: on building trust in IoT systems. 121:1-121:6 - Nancy Cam-Winget, Ahmad-Reza Sadeghi, Yier Jin:
Invited - Can IoT be secured: emerging challenges in connecting the unconnected. 122:1-122:6 - Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li:
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. 123:1-123:6 - Kyounghoon Kim, Jungki Kim, Joonsang Yu, Jungwoo Seo, Jongeun Lee, Kiyoung Choi:
Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks. 124:1-124:6 - Lixue Xia, Tianqi Tang, Wenqin Huangfu, Ming Cheng, Xiling Yin, Boxun Li, Yu Wang, Huazhong Yang:
Switched by input: power efficient structure for RRAM-based convolutional neural network. 125:1-125:6 - Jaeyong Chung, Taehwan Shin:
Simplifying deep neural networks for neuromorphic architectures. 126:1-126:6 - Vincent Camus, Jeremy Schlachter, Christian C. Enz:
A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision. 127:1-127:6 - Yi Wu, Weikang Qian:
An efficient method for multi-level approximate logic synthesis under error rate constraint. 128:1-128:6 - Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler:
Precise error determination of approximated components in sequential circuits with model checking. 129:1-129:6 - Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel:
Area optimization of resilient designs guided by a mixed integer geometric program. 130:1-130:6 - Tianyi Wang, Qiushi Han, Shi Sha, Wujie Wen, Gang Quan, Meikang Qiu:
On harmonic fixed-priority scheduling of periodic real-time tasks with constrained deadlines. 131:1-131:6 - Alejandro Masrur:
A probabilistic scheduling framework for mixed-criticality systems. 132:1-132:6 - Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Distributed scheduling for many-cores using cooperative game theory. 133:1-133:6 - Wen-Hung Huang, Jian-Jia Chen:
Utilization bounds on allocating rate-monotonic scheduled multi-mode tasks on multiprocessor systems. 134:1-134:6 - Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan:
DAG-aware logic synthesis of datapaths. 135:1-135:6 - Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smaïl Niar:
Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators. 136:1-136:6 - Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang:
Improving high-level synthesis with decoupled data structure optimization. 137:1-137:6 - Shane T. Fleming, David B. Thomas:
StitchUp: automatic control flow protection for high level synthesis circuits. 138:1-138:6 - Seyed Ali Rokni, Hassan Ghasemzadeh:
Plug-n-learn: automatic learning of computational algorithms in human-centered internet-of-things applications. 139:1-139:6 - Yu-Wen Jong, Pi-Cheng Hsiu, Sheng-Wei Cheng, Tei-Wei Kuo:
A semantics-aware design for mounting remote sensors on mobile systems. 140:1-140:6 - Piyali Goswami, Sushaanth Srirangapathi, Chetan Matad, Stanley Liu:
Re-target-able software power management framework using SoC data auto-generation. 141:1-141:6 - Dandan Li, Shuzhen Yao, Yuhang Liu, Senzhang Wang, Xian-He Sun:
Efficient design space exploration via statistical sampling and AdaBoost learning. 142:1-142:6 - Mihai Sanduleanu, Ibrahim Abe M. Elfadel:
Invited - Ultra low power integrated transceivers for near-field IoT. 143:1-143:6 - Payam Heydari:
Invited - Integrated millimeter-wave/terahertz sensor systems for near-field IoT. 144:1-144:6 - Wayne P. Burleson, Onur Mutlu, Mohit Tiwari:
Invited - Who is the major threat to tomorrow's security?: you, the hardware designer. 145:1-145:5 - Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
High-level synthesis for micro-electrode-dot-array digital microfluidic biochips. 146:1-146:6 - Tsun-Ming Tseng, Mengchu Li, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Columba: co-layout synthesis for continuous-flow microfluidic biochips. 147:1-147:6 - Juexiao Su, Tianheng Tu, Lei He:
A quantum annealing approach for boolean satisfiability problem. 148:1-148:6 - Mathias Soeken, Anupam Chattopadhyay:
Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis. 149:1-149:6 - Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy:
SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost. 150:1-150:6 - Hadi Asghari Moghaddam, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim:
VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency. 151:1-151:6 - Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu:
Exploration of associative power management with instruction governed operation for ultra-low power design. 152:1-152:6 - Xiang Chen, Jiachen Mao, Jiafei Gao, Kent W. Nixon, Yiran Chen:
MORPh: mobile OLED-friendly recording and playback system for low power video streaming. 153:1-153:6 - Zewei Li, Yongpan Liu, Daming Zhang, Chun Jason Xue, Zhangyuan Wang, Xin Shi, Wenyu Sun, Jiwu Shu, Huazhong Yang:
HW/SW co-design of nonvolatile IO system in energy harvesting sensor nodes for optimal data acquisition. 154:1-154:6 - Amin Rezaei, Danella Zhao, Masoud Daneshtalab, Hongyi Wu:
Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age. 155:1-155:6 - Hehe Li, Yongpan Liu, Chenchen Fu, Chun Jason Xue, Donglai Xiang, Jinshan Yue, Jinyang Li, Daming Zhang, Jingtong Hu, Huazhong Yang:
Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead. 156:1-156:6 - Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Kenneth L. Shepard, Luca P. Carloni:
An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. 157:1-157:6 - Wen-Hung Huang, Jian-Jia Chen, Jan Reineke:
MIRROR: symmetric timing analysis for real-time tasks on multicore platforms with shared resources. 158:1-158:6 - Shin-Haeng Kang, Duseok Kang, Hoeseok Yang, Soonhoi Ha:
Real-time co-scheduling of multiple dataflow graphs on multi-processor systems. 159:1-159:6 - Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin:
Optimal and fast throughput evaluation of CSDF. 160:1-160:6 - Hongwei Wang, Jinglin Shi, Ziyuan Zhu:
An expected hypervolume improvement algorithm for architectural exploration of embedded processors. 161:1-161:6 - James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden:
Standard lattices in hardware. 162:1-162:6 - Dean Sullivan, Orlando Arias, Lucas Davi, Per Larsen, Ahmad-Reza Sadeghi, Yier Jin:
Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity. 163:1-163:6 - Meng Li, Jin Miao, Kai Zhong, David Z. Pan:
Practical public PUF enabled by solving max-flow problem on chip. 164:1-164:6 - Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan Rajendran:
The cat and mouse in split manufacturing. 165:1-165:6 - Shivam Swami, Joydeep Rakshit, Kartik Mohanram:
SECRET: smartly EnCRypted energy efficient non-volatile memories. 166:1-166:6 - Abhishek Basak, Swarup Bhunia, Sandip Ray:
Exploiting design-for-debug for flexible SoC security architecture. 167:1-167:6 - Matthew Poremba, Tao Zhang, Yuan Xie:
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. 168:1-168:6 - Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta:
MTJ variation monitor-assisted adaptive MRAM write. 169:1-169:6 - Xunchao Chen, Navid Khoshavi, Jian Zhou, Dan Huang, Ronald F. DeMara, Jun Wang, Wujie Wen, Yiran Chen:
AOS: adaptive overwrite scheme for energy-efficient MLC STT-RAM cache. 170:1-170:6 - Huizhang Luo, Jingtong Hu, Liang Shi, Chun Jason Xue, Qingfeng Zhuge:
Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM. 171:1-171:6 - Deshan Zhang, Lei Ju, Mengying Zhao, Xiang Gao, Zhiping Jia:
Write-back aware shared last-level cache management for hybrid main memory. 172:1-172:6 - Shuangchen Li, Cong Xu, Qiaosha Zou, Jishen Zhao, Yu Lu, Yuan Xie:
Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. 173:1-173:6 - Alfred L. Crouch, John C. Potter:
Invited - A box of dots: using scan-based path delay test for timing verification. 174:1-174:6
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