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2020 – today
- 2024
[j34]Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino:
Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 344-354 (2024)- [j33]Tsunato Nakai, Ye Wang, Kota Yoshida, Takeshi Fujino:
SEDMA: Self-Distillation with Model Aggregation for Membership Privacy. Proc. Priv. Enhancing Technol. 2024(1): 494-508 (2024) - [j32]Takahito Ino, Kota Yoshida
, Hiroki Matsutani, Takeshi Fujino:
Data Poisoning Attack against Neural Network-Based On-Device Learning Anomaly Detector by Physical Attacks on Sensors. Sensors 24(19): 6416 (2024) - [c44]Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino:
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) 2024: 65-83 - [c43]Kota Yoshida, Takeshi Fujino:
Model Extraction Attack Without Natural Images. ACNS Workshops (2) 2024: 75-83 - [c42]Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Incorporating Cluster Analysis of Feature Vectors for Non-profiled Deep-learning-Based Side-Channel Attacks. ACNS Workshops (1) 2024: 84-101 - 2023
- [j31]Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples. IEEE Access 11: 87200-87209 (2023) - [j30]Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino:
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 281-293 (2023) - [j29]Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Kunihiro Kuroda, Takeshi Fujino:
Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 294-305 (2023) - [j28]Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM. J. Cryptogr. Eng. 13(4): 427-442 (2023) - [j27]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. Sensors 23(10): 4742 (2023) - [c41]Rei Ueda, Tsunato Nakai, Kota Yoshida, Takeshi Fujino:
Evaluation of Membership Inference Attack Against Federated Learning With Differential Privacy on Edge Devices. GCCE 2023: 1-5 - [c40]Masato Okuda, Kota Yoshida, Takeshi Fujino:
Multispectral Pedestrian Detection with Visible and Far-infrared Images Under Drifting Ambient Light and Temperature. SENSORS 2023: 1-4 - 2022
- [j26]Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 300-310 (2022) - [j25]Kota Yoshida, Masaya Hojo, Takeshi Fujino:
Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 326-335 (2022) - [j24]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 336-343 (2022) - [c39]Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino:
Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. ACNS Workshops 2022: 200-217 - [c38]Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino:
Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. AsianHOST 2022: 1-6 - [c37]Seiya Shimada, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication. ATAIT 2022: 75-84 - [c36]Madoka Sakou, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64. ATAIT 2022: 85-94 - 2021
- [j23]Hiroshi Yamada, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino:
Modeling attacks against device authentication using CMOS image sensor PUF. IEICE Electron. Express 18(7): 20210058 (2021) - [j22]Tsunato Nakai, Daisuke Suzuki, Fumio Omatsu, Takeshi Fujino:
Adversarial Black-Box Attacks with Timing Side-Channel Leakage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(1): 143-151 (2021) - [j21]Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino:
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(1): 152-161 (2021) - [j20]Mitsuru Shiozaki, Takeshi Fujino:
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. J. Cryptogr. Eng. 11(3): 201-212 (2021) - [j19]Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino:
Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsystems 87: 103383 (2021) - [j18]Shunsuke Okura, Masanori Aoki, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino, Kenichiro Ishikawa, Isao Takayanagi:
Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. Sensors 21(18): 6079 (2021) - [j17]Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino:
Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 149-175 (2021) - [c35]Kota Yoshida, Takeshi Fujino:
Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment. ACNS Workshops 2021: 78-95 - [c34]Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino:
Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. ACNS Workshops 2021: 151-168 - [c33]Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Takeshi Fujino:
Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES. AsianHOST 2021: 1-6 - [c32]Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino:
Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES Software Implementation with Two Types of Masking Countermeasures including RSM. ASHES@CCS 2021: 29-40 - [c31]Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino:
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. ASHES@CCS 2021: 63-72 - [c30]Kota Yoshida, Kuniyasu Suzaki, Takeshi Fujino:
Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code. HASP@MICRO 2021: 4:1-4:8 - 2020
- [c29]Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino:
Exploring Effect of Residual Electric Charges on Cryptographic Circuits. ASHES@CCS 2020: 57-66 - [c28]Kota Yoshida, Takeshi Fujino:
Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks. AISec@CCS 2020: 117-127 - [c27]Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino:
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS 2020: 1-5 - [c26]Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino:
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS 2020: 1-5 - [i4]Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino:
Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. 2020: 1284 (2020)
2010 – 2019
- 2019
- [c25]Mitsuru Shiozaki, Takeshi Fujino:
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. ASHES@CCS 2019: 13-21 - [c24]Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino:
Deep Learning Side-Channel Attack Against Hardware Implementations of AES. DSD 2019: 261-268 - [c23]Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino:
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. FCCM 2019: 318 - 2018
- [c22]Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino:
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS 2018: 54-59 - 2017
- [j16]Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki:
Tamper-resistant cryptographic hardware. IEICE Electron. Express 14(2): 20162004 (2017) - [j15]Takeshi Kumaki, Takeshi Fujino:
Hierarchical-Masked Image Filtering for Privacy-Protection. IEICE Trans. Inf. Syst. 100-D(10): 2327-2338 (2017) - [c21]Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino:
Malicious CAN-message attack against advanced driving assistant system. HOST 2017: 158 - 2015
- [j14]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing stealthy dopant-level circuits. J. Cryptogr. Eng. 5(2): 85-94 (2015) - [c20]Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino:
Development of LED illumination-based spy photo-prevention system. GCCE 2015: 129-130 - [c19]Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino:
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. ISCAS 2015: 1462-1465 - [c18]Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino:
Proposal of LED-based Peeping Prevention System. MWSCAS 2015: 1-4 - 2014
- [j13]Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino:
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 264-274 (2014) - [j12]Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino:
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 275-283 (2014) - [j11]Takeshi Kumaki, Kei Nakao, Kohei Hozumi, Takeshi Ogura, Takeshi Fujino:
Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. IEICE Trans. Inf. Syst. 97-D(3): 593-596 (2014) - [j10]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4(1): 59-73 (2014) - [j9]Anh-Tuan Hoang, Takeshi Fujino:
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. ACM Trans. Reconfigurable Technol. Syst. 7(2): 10:1-10:19 (2014) - [c17]Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide:
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS 2014: 359-362 - [c16]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing Stealthy Dopant-Level Circuits. CHES 2014: 112-126 - [c15]Yuki Yanagihara, Toshiya Honda, Takeshi Kumaki, Takeshi Fujino:
Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection. ISCAS 2014: 473 - [c14]Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino:
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. ISCAS 2014: 2547-2550 - [i3]Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino:
Diffusion Programmable Device : The device to prevent reverse engineering. IACR Cryptol. ePrint Arch. 2014: 109 (2014) - [i2]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing Stealthy Dopant-Level Circuits. IACR Cryptol. ePrint Arch. 2014: 508 (2014) - 2013
- [c13]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES 2013: 159-178 - [c12]Anh-Tuan Hoang, Takeshi Fujino:
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). FPGA 2013: 266-267 - [c11]Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino:
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. GCCE 2013: 525-527 - [c10]Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino:
Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS 2013: 408-411 - [c9]Kei Nakao, Kohei Hozumi, Takeshi Kumaki, Takeshi Ogura, Takeshi Fujino:
Development of effective information-hiding method for embedded systems. MWSCAS 2013: 1298-1301 - [c8]Toshiya Honda, Yuma Murakami, Yuki Yanagihara, Takeshi Kumaki, Takeshi Fujino:
Hierarchical image-scrambling method with scramble-level controllability for privacy protection. MWSCAS 2013: 1371-1374 - [c7]Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino:
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT 2013: 1-4 - [i1]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013: 579 (2013) - 2012
- [j8]Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino:
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. 95-C(4): 468-477 (2012) - [j7]Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino:
Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(9): 1518-1528 (2012) - [j6]Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino:
Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2182-2190 (2012) - [c6]Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino:
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD 2012: 735-738 - [c5]Anh-Tuan Hoang, Takeshi Fujino:
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA 2012: 1-10 - 2011
- [j5]Masaya Yoshikawa, Takeshi Fujino:
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. 18(4): 218-226 (2011) - [c4]Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino:
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST 2011: 28-33 - [c3]Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino:
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS 2011: 2325-2328 - 2010
- [c2]Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino:
Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE 2010: 21-25
2000 – 2009
- 2008
- [j4]Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino:
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. 91-C(4): 509-516 (2008) - 2007
- [c1]Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino:
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC 2007: 261-264 - 2003
- [j3]Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki:
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2991-3000 (2003) - [j2]Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto:
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits 38(11): 1967-1973 (2003)
1990 – 1999
- 1997
- [j1]Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto:
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32(11): 1721-1727 (1997)
Coauthor Index
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