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    Experiment No. 4: Transistor-Level Circuit Design Using Cadence Design Flow

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    kingster
    This document outlines an experiment on transistor-level circuit design using Cadence. It involves designing various analog and digital circuits through transistor-level schematic capture and simulation, layout, and post-layout simulation. The circuits include a cascode amplifier, differential amplifier, current source, OTA, frequency divider, and non-overlapping clock generator. The goals are to learn transistor-level design methodology and verify designs meet specifications across simulation steps and process variations.

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    Experiment No. 4: Transistor-Level Circuit Design Using Cadence Design Flow

    Uploaded by

    kingster
    82 views7 pages
    This document outlines an experiment on transistor-level circuit design using Cadence. It involves designing various analog and digital circuits through transistor-level schematic capture and simulation, layout, and post-layout simulation. The circuits include a cascode amplifier, differential amplifier, current source, OTA, frequency divider, and non-overlapping clock generator. The goals are to learn transistor-level design methodology and verify designs meet specifications across simulation steps and process variations.

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    2010 VLSI Eng Lab Expt 04A v1

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    This document outlines an experiment on transistor-level circuit design using Cadence. It involves designing various analog and digital circuits through transistor-level schematic capture and simulation, layout, and post-layout simulation. The circuits include a cascode amplifier, differential amplifier, current source, OTA, frequency divider, and non-overlapping clock generator. The goals are to learn transistor-level design methodology and verify designs meet specifications across simulation steps and process variations.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    82 views7 pages

    Experiment No. 4: Transistor-Level Circuit Design Using Cadence Design Flow

    Uploaded by

    kingster
    This document outlines an experiment on transistor-level circuit design using Cadence. It involves designing various analog and digital circuits through transistor-level schematic capture and simulation, layout, and post-layout simulation. The circuits include a cascode amplifier, differential amplifier, current source, OTA, frequency divider, and non-overlapping clock generator. The goals are to learn transistor-level design methodology and verify designs meet specifications across simulation steps and process variations.

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    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4. Experiment No. 4:
    Transistor-level Circuit Design using Cadence Design Flow
    4.1. Objective
    1. To execute a typical transistor-level circuit design methodology (including circuit design, design simulation,
    design layout, post-layout design simulation) using the Cadence design flow for various analog circuits

    4.2. Experimental procedure


    4.2.1 Circuit design (paper-pencil design w/o cadence)
     Expected outputs:
    o Calculations used to meet the target design-specifications
    o Resulting W/L ratios of the transistors used
    o Diagram(s) of the circuit architecture showing all the transistors showing the (W/L) ratios
    o Note: while using paper-pencil level design (to get an estimate of the W/L values prior to any circuit
    simulations), use the 3V ihp process information.

    4.2.2 Schematic capture and simulation


     Use circuit simulations for optimizing a few of the (W/L) values of the transistors in order to meet the design-
    specifications
     Expected outputs:
    o Schematic(s) of the circuit block showing the W and L values for all transistors
    o Schematic diagram(s) of the testbench used with all sources and measurement nodes
    o DC analysis results
    o Transient analysis results
    o AC analysis results
    o The values of design-specifications from circuit simulation(s)

    4.2.3 Circuit layout and layout vs. schematic check


     Do the physical design (layout) of the final version (not the intermediate versions) of the circuit block and
    check against the schematic
     Expected outputs:
    o Layout diagram of the circuit block
    o Design rule check (DRC) report for the layout
    o Layout vs. schematic (LVS) verification report

    4.2.4 Parameter extraction from layout and post-layout simulation


     Extract the circuit parasitics from the layout and perform the post-layout simulations of the circuit
     Expected outputs
    o DC analysis results
    o Transient analysis results
    o AC analysis results
    o The final values of design-specifications from post-layout circuit simulations
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3. Circuits to use for the experiment


    4.3.1 A cascode amplifier design
    1. Design a Common-source NMOS amplifier with a gain of 20 dB.
    First have a resistor load, then a diode connected MOS load and further a current source load.
    2. Increase the input frequency and observe the angle and amplitude of the voltage between the input (gate) VIN
    node and the output (drain) node VOUT.
    Insert a cascode device of appropriate transconductance and observe the amplitude and angle between VIN and
    VOUT again.
    3. Observe what limitations there are on the output voltage swing before and after inserting cascode device.
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3.2 A differential amplifier design


    1. Design a differential amplifier with resistor loading and source of the differential pair grounded.
    Aim at a gain of 40 dB.
    2. Couple the source of the resistor pair and add a resistance to ground.
    3. Replace the resistor with a current source.
    4. Design a differential amplifier with current source biasing with Input common mode range of 1.5V, Output
    common mode range of 1 V, 500V/us slew rate, gain of 40 dB, BW of 40 MHz. Observe the gain and phase
    margins.
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3.3 A current source design


    1. Design a current reference using an ideal resistor as a current source and a MOS as a current sink. Let this be
    of 20 uA.
    Mirror this current on the other branch to generate a current of 1 mA.
    2. Observe the difference in VDS between the reference and the mirrored transistor.
    Now stack two DC biased transistors on top of the mirrored one and observe the current ratio.
    3. Insert an AC current source in the reference and vary it by 5 uA.
    Observe how the mirrored current follows the signal.
    4. Use real resistors from the design kit library (i.e. tech file) to observe process variation of the current.
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3.4 An operational transconductance amplifier design


    1. Design a common-source amplifier using active-device load with a voltage gain (Av) higher than 30.
    2. Convert the design into an operational transconductance amplifier configuration with an output stage added
    next. Aim to get the Gm above 10m ohm-1.
    3. Add a current-source load to get a voltage gain (Av) higher than 100.
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3.5 A digital frequency divider


    1. Design one digital frequency divider block (which can be reset at any time instant) with the following
    specifications
    (i) Input reference frequency of 500 MHz (Square-wave, rise time = fall time = 10ps, no delay).
    (ii) Division ratio ranging from 14 to 18
    (iii) Reset signal of 1ns
    2. Determine the set-up-time and hold-time of the signal at input side
    Determine the propagation delay of the entire block.
    Calculate the maximum operating frequency of the system
    3. Observe the above values for three process-voltage-temperature (PVT) corners.
    (Typical-Typical) / 3V / 27°C
    (Slow-Slow) / 2.7V /°C
    (Fast-Fast) / 3.3V / -40°C
    VLSI Engineering Lab (EC39004): 2010 Spring Semester

    4.3.6 Non-overlapping clock generator


    1. Design a non-overlapping clock generator with following specifications. Delay block in the schematic is a
    chain of even number of inverters.
    (i) clkIN = 100 MHz
    (ii) Load capacitance for clkA and clkB = 100 fF
    (iii) Dead time between the clock transitions (min.) = 15% of Clock-period.
    Dead time between the clock transitions (max.) = 25% of Clock-period.

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