W25X20CLSNIG
W25X20CLSNIG
W25X20CLSNIG
2.5 / 3 / 3.3 V
512K / 1M / 2M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL I/O SPI
Table of Contents
1. GENERAL DESCRIPTION
The W25X05CL (512K-bit), W25X10CL (1M-bit) and W25X20CL (2M-bit) Serial Flash memories
provide a storage solution for systems with limited space, pins and power. The 25X series offers
flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code
download applications as well as storing voice, text and data. The devices operate on a single 2.3V
to 3.6V power supply with current consumption as low as 1mA active and 1A for power-down. All
devices are offered in space-saving packages.
The W25X05CL/10CL/20CL arrays are organized into 256/512/1,024 programmable pages of 256-
bytes each. Up to 256 bytes can be programmed at a time. The W25X05CL/10CL/20CL have
16/32/64 erasable sectors, 2/4/8 erasable 32KB blocks and 1/2/4 erasable 64KB blocks respectively.
The small 4KB sectors allow for greater flexibility in applications that require data and parameter
storage. (See figure 2.)
The W25X05CL/10CL/20CL support the standard Serial Peripheral Interface (SPI), and a high
performance dual output as well as Dual I/O SPI: Serial Clock, Chip Select, Serial Data DIO (I/O0),
DO (I/O1). SPI clock frequencies up to 104MHz are supported allowing equivalent clock rates of
208MHz when using the Fast Read Dual Output instruction. These transfer rates are comparable to
those of 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 16-clocks of instruction-overhead to read a 24-bit address, allowing
true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control
features, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of Serial Flash Memories Software and Hardware Write Protection
W25X05CL: 512K-bit/64K-byte (65,536) Write-Protect all or portion of memory
W25X10CL: 1M-bit/128K-byte (131,072) Enable/Disable protection with /WP pin
W25X20CL: 2M-bit/256K-byte (262,144) Top or bottom array protection
256-bytes per programmable page Flexible Architecture with 4KB sectors
Uniform erasable 4KB, 32KB & 64KB regions. Uniform Sector/Block Erase (4/32/64-kbytes)
SPI with Single / Dual Outputs / I/O Page program up to 256 bytes <1ms
Standard SPI: CLK, /CS, DI, DO, /WP, /Hold More than 100,000 erase/write cycles
Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold More than 20-year data retention
Data Transfer up to 208M-bits / second Low Power, Wide Temperature Range
Clock operation to 104MHz Single 2.3V to 3.6V supply
208MHz equivalent Dual I/O SPI 1mA active current, <1A Power-down(typ.)
Auto-increment Read capability -40 to +85C operating range
Efficient Continuous Read Mode Space Efficient Packaging
Low Instruction overhead 8-pin SOIC / VSOP 150-mil
Continuous Read 8-pin TSSOP 173-mil
As few as 16 clocks to address memory 8-pad WSON 6x5-mm
Allows true XIP (execute in place) operation 8-pad USON 2x3-mm
Contact Winbond for KGD and other options
Figure 1a. W25X05CL/10CL/20CL Pin Assignments, 8-pin SOIC 150-mil, VSOP 150-mil and TSSOP8 173-mil
(Package Code SN, SV and SD)
Figure 1b. W25X05CL/10CL/20CL Pad Assignments, 8-pad WSON 6x8-MM and USON 2x3-MM (Package Code ZP & UX)
5.3 Serial Data Input, Output and IOs (DIO, DO, IO0 and IO1)
The W25X05CL/10CL/20CL support standard SPI and Dual SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output)
to read data or status from the device on the falling edge of CLK.
Dual SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the
device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
6. BLOCK DIAGRAM
7. FUNCTIONAL DESCRIPTION
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept
active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the
device.
Upon power-up or at power-down, the W25X05CL/10CL/20CL will maintain a reset condition while
VCC is below the threshold value of V WI, (See Power-up Timing and Voltage Levels and Figure 26).
While reset, all operations are disabled and no instructions are recognized. During power-up and after
the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a
time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip
Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the
VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If needed, a
pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared
to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (TB, BP1 and BP0) bits. These allow a portion
small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under
hardware control. See Status Register for further information. Additionally, the Power-down instruction
offers an extra level of write protection as all instructions are ignored except for the Release Power-
down instruction.
8.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During
this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
Status
SRP /WP Description
Register
Software /WP pin has no control, The Status register can be written to
0 X Protection after a Write Enable instruction WEL = 1. [Factory Default]
Hardware When /WP pin is low the Status Register locked and cant be
1 0 Protected written to.
Hardware When /WP pin is high the status register is unlocked and can
1 1 Unprotected be written to after a Write Enable instruction WEL = 1.
S7 S6 S5 S4 S3
S3 S2
S2 S1
S1 S0
S0
RESERVED
TOP/BOTTOM PROTECT
(Non-volatile)
(1)
STATUS REGISTER W25X20CL (2M-BIT) MEMORY PROTECTION
TB BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
x 0 0 NONE NONE NONE NONE
0 0 1 3 030000h - 03FFFFh 64KB Upper 1/4
0 1 0 2 and 3 020000h - 03FFFFh 128KB Upper 1/2
1 0 1 0 000000h - 00FFFFh 64KB Lower 1/4
1 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/2
x 1 1 0 thru 3 000000h - 03FFFFh 256KB ALL
(1)
STATUS REGISTER W25X10CL (1M-BIT) MEMORY PROTECTION
TB BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
x 0 0 NONE NONE NONE NONE
0 0 1 1 010000h - 01FFFFh 64KB Upper 1/2
1 0 1 0 000000h - 00FFFFh 64KB Lower 1/2
x 1 x 0 and 1 000000h - 01FFFFh 128KB ALL
8.2 INSTRUCTIONS
The instruction set of the W25X05CL/10CL/20CL consists of twenty basic instructions that are fully
controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DIO input provides the instruction
code. Data on the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (dont care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 25. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a
full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects
the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or
when the Status Register is being written, all instructions except for Read Status Register will be
ignored until the program or erase cycle has completed.
MANUFACTURER ID (M7-M0)
Notes:
1 Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis ( ) indicate data being read from
the device on the DO pin.
2 The Status Register contents will repeat continuously until /CS terminates the instruction.
3 See Manufacturer and Device Identification table for Device ID information.
4 The Device ID will repeat continuously until /CS terminates the instruction.
5 Dual Output and Dual I/O data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
6 Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
/CS
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (06h)
DI
(IO0)
DO High Impedance
(IO1)
Instruction (50h)
Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram
/CS
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (04h)
DI
(IO0)
DO High Impedance
(IO1)
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 7. The instruction is completed by driving /CS high.
Only non-volatile Status Register bits SRP, TB, BP1 and BP0 (bits 7, 5, 3 and 2) can be written to. All
other Status Register bit locations are read-only and will not be affected by the Write Status Register
instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed
Write Status Register cycle will commence for a time duration of t W (See AC Characteristics). While
the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed
to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a
0 when the cycle is finished and ready to accept other instructions again. After the Write Register
cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (TB, BP1 and BP0) to be set for
protecting all, a portion, or none of the memory from erase and program instructions. Protected areas
become read-only (see Status Register Memory Protection table). The Write Status Register
instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction
with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0
state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a
1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is
high the Write Status Register instruction is allowed.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of t SHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Read Data instruction sequence is shown in figure 9. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of
fR (see AC Electrical Characteristics).
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
CLK Mode 0
* = MSB *
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
* = MSB
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
DI
0
(IO0)
Data Out 1 Data Out 2
DO High Impedance
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
(IO1)
* *
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
dummy clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy
clocks is dont care. However, the IO0 pin should be high-impedance prior to the falling edge of the
first data out clock.
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
/CS
* = MSB
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
IO0 switches from
Dummy Clocks Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO0)
DO High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(IO1)
* Data Out 1 * Data Out 2 * Data Out 3 * Data Out 4
If the Continuous Read Mode bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after
/CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.
This reduces the instruction sequence by eight clocks and allows the Read address to be immediately
entered after /CS is asserted low. If the Continuous Read Mode bits M5-4 do not equal to (1,0), the
next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus
returning to normal operation. A Continuous Read Mode Reset instruction can also be used to reset
(M7-0) before issuing normal instructions (See 9.2.12 for detail descriptions).
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
DO
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
(IO1)
* *
* = MSB
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO0)
DO
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(IO1)
* Byte 1 * Byte 2 * Byte 3 * Byte 4
Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4 10)
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0
DO
23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1
(IO1)
* *
= MSB
*
/CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
(IO0)
DO
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
(IO1)
* Byte 1 * Byte 2 * Byte 3 * Byte 4
Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)
IO 0 FFFFh
IO 1 Dont Care
Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O
Since W25X05CL/10CL/20CL does not have a hardware Reset pin, so if the controller resets while
W25X05CL/10CL/20CL are set to Continuous Mode Read, the W25X05CL/10CL/20CL will
not recognize any initial standard SPI instructions from the controller. To address this possibility, it is
recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a
system Reset. Doing so will release the device from the Continuous Read Mode and allow Standard
SPI instructions to be recognized.
To reset Continuous Read Mode during Dual I/O operation, sixteen clocks are needed to shift in
instruction FFFFh.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector
Erase instruction will commence for a time duration of t SE (See AC Characteristics). While the Sector
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Sector Erase
cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector
Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,
BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and
BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block
Erase instruction will commence for a time duration of t BE (See AC Characteristics). While the Block
Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the
cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and
BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction
will commence for a time duration of t CE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed
if any page is protected by the Block Protect (TB, BP1 and BP0) bits (see Status Register Memory
Protection table).
/CS
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (C7h/60h)
DI
(IO0)
DO High Impedance
(IO1)
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-
down instruction will not be executed. After /CS is driven high, the power-down state will entered
within the time duration of tDP (See AC Characteristics). While in the power-down state only the
Release from Power-down / Device ID instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction makes the Power
Down state a useful condition for securing maximum write protection. The device always powers -up in
the normal operation with the standby current of ICC1.
/CS
tDP
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (B9h)
DI
(IO0)
To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code ABh and driving /CS high as shown in figure 20. Release from power-
down will take the time duration of t RES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the t RES1
time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated
by driving the /CS pin low and shifting the instruction code ABh followed by 3-dummy bytes. The
Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 20. The Device ID values for the W25X05CL/10CL/20CL are listed in Manufacturer
and Device Identification table. The Device ID can be read continuously. The instruction is completed
by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction
is the same as previously described, and shown in figure 21, except that after /CS is driven high it
must remain high for a time duration of t RES2 (See AC Characteristics). After this time duration the
device will resume normal operation and other instructions will be accepted.
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write
cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on
the current cycle
/CS
tRES1
Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0
Instruction (ABh)
DI
(IO0)
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 Mode 3
CLK Mode 0 Mode 0
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
90h followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in figure 22. The Device ID values for the W25X05CL/10CL/20CL are listed in Manufacturer
and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be
read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
CLK Mode 0
* = MSB
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 3
CLK Mode 0
DI
0
(IO0)
DO
7 6 5 4 3 2 1 0
(IO1)
Manufacturer ID (EFh) * Device ID
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code 92h followed by
a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input
the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the
Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB)
first as shown in figure 28. The Device ID values for the W25X05CL/10CL/20CL are listed in
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device
ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can
be read continuously, alternating from one to the other. The instruction is completed by driving /CS
high.
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
DO High Impedance
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
(IO1) = MSB
* * * * *
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mode 3
CLK Mode 0
IOs switch from
Input to Output
DI
0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
(IO0)
DO
1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
(IO1)
* MFR ID * Device ID * MFR ID
(repeat)
* Device ID
(repeat)
/CS
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode 0
DO High Impedance
(IO1)
/CS
100
101
102
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Mode 3
CLK Mode 0
DO High Impedance
63 62 61 2 1 0
(IO1)
* = MSB
* 64-bit Unique Serial Number
The instruction is initiated by driving the /CS pin low and shifting the instruction code 9Fh. The
JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type
(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant
bit (MSB) first as shown in figure 25. For memory type and capacity values refer to Manufacturer and
Device Identification table.
9. ELECTRICAL CHARACTERISTICS
0.5 VCC
0.1 VCC
Clock High, Low Time, for Fast Read (0Bh, 3Bh) / tCLH, 4 ns
other instructions except Read Data (03h) tCLL(1)
Additional Byte Program Time (After First Byte) (4) tBP2 2.5 5 s
/CS
tCLH
CLK
tCLQV tCLQV tCLL tSHQZ
tCLQX tCLQX
IO
MSB OUT LSB OUT
output
/CS
tSHSL
tCHSL tSLCH tCHSH tSHCH
CLK
tDVCH tCHDX tCLCH tCHCL
IO
MSB IN LSB IN
input
/CS
/HOLD
tHLQZ tHHQX
IO
output
IO
input
/CS
tWHSL tSHWL
/WP
CLK
IO
input
Write Status Register is allowed Write Status Register is not allowed
E HE
1 4
0.25
D
A
Y
SEATING PLANE e
GAUGE PLANE
b A1
MILLIMETERS INCHES
SYMBOL
Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
b 0.33 0.51 0.013 0.020
c 0.19 0.25 0.008 0.010
E(3) 3.80 4.00 0.150 0.157
D(3) 4.80 5.00 0.188 0.196
e(2) 1.27 BSC 0.050 BSC
HE 5.80 6.20 0.228 0.244
Y(4) - 0.10 - 0.004
L 0.40 1.27 0.016 0.050
0 10 0 10
Notes:
1. Controlling dimensions: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches .
MILLIMETER INCHES
SYMBOL
MIN TYP. MAX MIN TYP. MAX
A 1 0.039
0 10 0 10
MILLIMETER INCHES
SYMBOL
MIN TYP. MAX MIN TYP. MAX
A 1.20 0.047
0 8 0 8
MILLIMETERS INCHES
SYMBOL
MIN TYP. MAX MIN TYP. MAX
A 0.70 0.75 0.80 0.0275 0.0295 0.0314
E (2)
1.27 BSC 0.0500 BSC
MILLIMETERS INCHES
SYMBOL
MIN TYP. MAX MIN TYP. MAX
SOLDER PATTERN
M 3.40 0.1338
N 4.30 0.1692
P 6.00 0.2360
Q 0.50 0.0196
R 0.75 0.0255
Notes:
1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
A
PIN 1
L1
INDENT
A1
D D2
L3
E C E L
y 2
MILLIMETER INCHES
SYMBOL
MIN TYP. MAX MIN TYP. MAX
A 0.50 0.55 0.60 0.020 0.022 0.024
e 0.50 0.020
L1 0.10 0.004
25X = SpiFlash Serial Flash Memory with 4KB sectors, Dual SPI
20C = 2M-bit
10C = 1M-bit
05C = 512K-bit
L = 2.3V to 3.6V
Notes:
1a. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel
(shape T) or Tray (shape S), when placing orders.
1b. The W prefix is not included on the part marking.
2. Only the 2nd letter is used for the part marking, package type ZP is not used for the part marking.
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Further more, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document and
the products and services described herein at any time, without notice.