International Journal on Electrical Engineering and Informatics ‐ Volume 4, Number 3, October 2012

A Quick Guide to Implement Reversible Logic

Shaveta Thakral1, Dipali Bansal2

1 2
Research Scholar, Department of Electronics & Communication (FET)
Manav Rachna International University, Faridabad
1
[email protected],[email protected]
Abstract: Increasing miniaturization and demand of low power electronics is highly motivating research on reversible logic.
Reversible logic has attracted signification attention in fields of computer graphics, optical information processing, quantum
computing, DNA computing, ultra low power CMOS design and communication. A lot of work has been done on synthesis and
optimization of reversible circuits followed by quantitative analysis on various optimization metrics like ancillary inputs, garbage
outputs and quantum cost. It is therefore obvious to present a quick guide on reversible logic implementation to bridge gap between
theory and implementation. Taxonomy diagrams of work done in reversible logic domain are also presented to give a quick review of
all about reversible logic. Quantum realization of popular reversible logic gates along with full adder using RCViewer tool is also
presented which will be stepping stone for a new researcher to synthesize and optimize any complex reversible logic based circuit.

Keywords: Reversible logic, low power electronics, quantum cost, RCViewer

1. Introduction
In 1961 Landauer stated that “amount of energy dissipated for every bit erasure during an irreversible operation is given
by KTln2 joules where K is Boltzman’s constant and T is the operating temperature. In 1973,Bennett proposed the
solution to R. Landauer statement and showed that KTln2 energy dissipation would not occur, if computation is done in
a reversible manner since amount of energy dissipated in a system depends directly on numbers of bits erased during
computation. Classical gates like two input AND, OR, NAND, NOR, XOR and XNOR are irreversible as input states
can’t be uniquely reconstructed from output states. Here two-bit input state is mapped to one-bit output state which
leads to the erasure of one bit and consequently loss of energy. This energy loss can be avoided by mapping n bit input
states to n bit output states so that input states can be uniquely recovered from output states and under such
circumstances, a gate is said to be reversible. Quantum gates or reversible gates differ from Classical gates in a way that
quantum gates work on qubits rather than bits and feedbacks are not permitted.
There are various reversible gates proposed over past decades. Among them major contributions were given by Toffoli,
Feynman, Fredkin .Toffoli gate is a reversible gate which could play a role of a universal gate for reversible circuits.
Fredkin gate is controlled swap gate which is also found to be conservative as well as universal logic gate described
three reversible primitives i.e. NOT, CNOT(controlled NOT) and CCNOT(controlled controlled NOT) that are used to
make a universal circuit . Peres in 1985 proposed Peres gate which was found to be 3*3 reversible logic gate with
lowest quantum cost. Extensive literature survey on gates was done by Garipelly and many other gates are found
popular in literature like TR gate, NG gate, R gate, URG gate, BJN gate, MCL gate, NFT gate, TKS gate, TSG gate,
MTSG gate, SCL gate, MKG gate, BVF gate, BME gate, DPG gate, DKG gate, PTR gate, NCG gate, SBV gate and
HNG Gate.
Parity checking is one of the methods for error detection in digital logic system. In parity preserving reversible circuit,
parity preserving reversible logic gates are used in which parity of input vector must match parity of output vector. A
reversible circuit will be parity preserving if its individual gate is parity preserving. As parity preserving reversible
logic gates used between fault side and output are information lossless. Hence an error at fault side will be
immediately seen at output. Parity preserving reversible gates allows detecting such faults at output which won’t affect
more than a single logical signal. Conservative logic gates exhibit property that there are equal numbers of 1’s in
output as there are in input. Every conservative gate is parity preserving but every parity preserving gate is not
conservative. There are many parity preserving logic gates reported in literature. Among them are Fredkin gate with
quantum cost of 5, double Feynman gate with quantum cost of 2, PPHCG, NFT gate with quantum cost of 7, Islam
gate and modified Islam gate (MIG) with quantum cost of 7, PPPG gate, MNFT gate with quantum cost of 7, five
variables parity preserving gate (F2PG) with quantum cost of 14 and parity conserving multifunctional (PCMF) gate,
universal parity preserving gate (UPPG). It has been found that among existing 24 2*2 reversible logic gates, only 4
are parity preserving and among them only 2 are conservative. Similarly among existing 40320 3*3 reversible logic
gates, only 576 are parity preserving and among them only 36 are conservative. Only Fredkin gate and PCMF are
parity preserving as well as conservative. Others are parity preserving but not conservative. Taxonomy of reversible
logic gates is given in Table 1.
Table 1.Taxonomy of Reversible Logic Gates
2. Optimization Metrics
The optimization metrics of reversible logic circuits are quantum cost, ancillary input, garbage output and delay.
The quantum cost of a reversible gate is total number of 1x1 and 2x2 reversible gates required in the design. The
quantum costs of all reversible 1x1, as well as 2x2 gates, are taken as one. Since every reversible gate consists of
various 1 x 1 or 2 x 2 quantum gates taken from NCV gate library containing combinations of NOT, CNOT and
controlled V and controlled V+ gates, therefore the quantum cost of a reversible gate can be calculated by
counting the numbers of NOT, Controlled-V, Controlled-V+ and CNOT gates. Quantum cost for any reversible
logic circuit should be as low as possible. To achieve reversibility, it is a must to map n bit input states to bit n
output states and sometimes every gate output is neither used as input to some other gates nor acting as a useful
desired output. These undesired or unused outputs that are deliberately obtained to maintain reversibility criterion
of a reversible gate (or circuit) is known as Garbage Outputs. Garbage outputs for any reversible logic circuit
should be as low as possible. To achieve reversibility, it is necessary to map n nit input states to n bit output states.
These constant inputs 0 or 1 which are deliberately applied to maintain reversibility criterion of a reversible gate
(or circuit) are known as Ancillary Inputs. Ancillary inputs for any reversible logic circuit should be as low as
possible. The maximum number of gates in a path from any input line to any output line in any reversible logic
circuit is called as delay. Two assumptions need to be considered for calculation of delay: (i) Each gate performs
computation in one unit time and (ii) all inputs to the circuit are available before the computation begins. The
delay of each 1x1 gate and 2x2 reversible gates is taken as unity. Delay for any reversible logic circuit should be
as low as possible. Taxonomy of optimization metrics of reversible logic circuit is given in Table2.

Table 2. Taxonomy of Reversible Logic Circuit

3. Representation Models
There are various ways to represent a reversible logic based Boolean function. Taxonomy diagram for reversible
logic functions representation models is given in Table 3.

A. Truth table representation

It is simplest form of representing any Boolean function. It is good way of representation for limited number of
variables. Representation via this method becomes cumbersome for large number of variables. An n size Boolean
function is represented using n columns and 2.n rows.

B. Matrix representation
Any reversible Boolean function can be represented in matrix form where a single 1 is occupied in each column
and each row. Therefore it is also called as permutation matrix.

C. Positive Polarity Reed-Muller Expansion

It uses operations AND, XOR and NOT. Reed-muller is equivalent to modulo-2 algebra. It can be positive
polarity based or fixed polarity based. Positive polarity reed muller expansion uses only uncomplemented
variables and expansion can be derived from ESOP where complement of variable A is replaced by A XOR 1.

D. Cycle Expansion
In canonical cycle expansion every permutation of reversible Boolean function can be represented as a
product of disjoint cycles.
E. Binary Decision Diagram
 A binary decision diagram is basically acyclic graph which provides user a simplified if then else (ITE)
structure to determine output based on input. Binary decision diagrams are based on Shannon decomposition.

Table 3. Taxonomy of Reversible Logic Function Representation Models

4. Software Tools
Key thrust area in reversible logic moves all across workflow of reversible logic circuit as a chain of
synthesis, optimization, simulation, verification and testing. Therefore simulators and software tools move
around complete chain. Familiarization with these tools will provide researchers to conclude efficient
quantitative and qualitative analysis on benchmarks. The frequently used tools by researchers are listed by
taxonomy diagram given in Table 4.The tools introduction is given below:

A.. SYREC
It is a hardware description language developed by Robert Wille in 2012. This language is used to
synthesize reversible circuits automatically.

B. RCViewer
It is application software that accepts input files in .tfc format which is basically machine readable
format and viewed circuit after application can be saved in bitmap format. It is called so because it aids
in the visualization of reversible logic based gates, circuits and further cascaded networks. Network may
be formed via NCT (NOT-CNOT-TOFFOLI) gate library or NCTSF (NOT-CNOT-TOFFOLI-SWAP-
FREDKIN) gate library along with support of hadamard, controlled V and controlled V+ gates.

C. QCViewer
It is basically a simulation tool which aid visualization in quantum circuit design. It provides a drag and
drop graphical interface for circuit designing

D. REVKIT
It is an open source toolkit that supports researchers in synthesis, optimization and verification of
reversible circuits. Using REVKIT researcher can apply transformation based synthesis, ESOP based
synthesis, exact synthesis, ESOP based synthesis and applies different optimization techniques as well as
utilize SAT based equivalence checker for verification.

E. RCDEV
It was developed in 2012 which is used to create schematic using standard libraries and it also supports
cascading and aids in verification.

F. RCTEST
It was developed in 2013 which is used in ESOP based synthesis of reversible circuit. It also provides
parity preservation and online testability for fault tolerant reversible circuit.

G. RPGASim
It was developed in 2013 which is acting as simulation tool using RPGA structure.

H. QCADesigner
 It is basically a design, layout and simulation tool for quantum dot cellular automata (QCA) circuit. It
provides power CAD features for designing of complex reversible circuit.

Table 4. Taxonomy of Software Tools in Reversible Logic

4. Synthesis Methods
Researchers have invented many reversible logic based synthesis methods in past few decades each method have
its own advantages as well as disadvantages like number of variables in synthesis of reversible logic based
functions, run time. Choosing best synthesis method is very important as well as tedious task and requires lot of
effort for best design. Taxonomy diagram of reversible logic based synthesis methods is given in Table 4.

A. Transformation based method

A reversible function is transformed into an optimal network of reversible gates by various algorithms. Truth table
based synthesis methods are based on transformations on the truth table. During the reversible logic synthesis
process, a sequence of transformation is applied, and the whole process is implemented by a sequence of Toffoli
gates. Toffoli gates can be applied to a reversible function via three ways: a) To inputs of a reversible function,
leads to synthesis flow from input to output, b) To outputs of a reversible function, leads to synthesis flow from
output to input, c) To both inputs and outputs of a reversible function, leads to synthesis flow in both directions
simultaneously .Application of the algorithm to reversible logic function leads to the generation of a circuit by
applying Toffoli gates to bring reversible function to its identity function. Example of transformation based
algorithm is basic algorithm, bidirectional algorithm and bit string swapping sorting network with BSSSN and
variant of BSSSN.

B. Cycle based method

Here entire permutation is divided into a set of cycles and cycles are synthesized separately. Divide and conquer
approach makes final circuit by cascading individual circuits.

C. Search based method

This method uses positive polarity Reed Muller (PPRM) expansion at each stage and transforms it to identity
function. Given reversible function is then converted using CNOT and CCNOT gates.

D. BDD based method

Wille and Drechsler proposed Binary Decision Diagrams (BDD) based reversible logic synthesis. Limitation of
BDD-based reversible logic synthesis method that it takes a large number of ancilla lines compared to the other
heuristic methods, but quantum cost required is quiet less. Advantage of this method is that it can work for large
number of variables.

E. ESOP based method

Fazel proposed ESOP based synthesis method for designing reversible logic based circuits. If ESOP circuits
provide multiple outputs then sharing of common functions between those outputs proves to be beneficial to
reduce quantum cost and making effective circuit.

F. Programming language based method

 Programming language based synthesis method aids to specify and automatically synthesize reversible
circuits. SyRec is a hardware description language developed by Robert Wille in 2012. This language is used
to synthesize reversible circuits automatically. Other synthesis methods become cumbersome for complex
reversible logic based circuits yet programming language based synthesis methods give good results and
prove to be friendly for specification and synthesis of complex circuits.

Table 5.Taxonomy of Reversible Logic Based Synthesis Methods

5. Quick Guide to RCViewer Tool

RCViewer is simple application software written in C++. It is called so because it aids in the visualization of
reversible logic based gates, circuits and further cascaded networks. Network may be formed via NCT (NOT-
CNOT-TOFFOLI) gate library or NCTSF (NOT-CNOT-TOFFOLI-SWAP-FREDKIN) gate library along with
support of hadamard, controlled V and controlled V+ gates. tn indicates toffoli gate where t indicates toffoli and n
indicates size of toffoli. Similarly fn indicates fredkin gate where f indicates fredkin and n indicates size of
fredkin. RCViewer+ is improved version of RCViewer. It accepts input files in .tfc format which is basically
machine readable format and viewed circuit after application can be saved in bitmap format. .tfc format consists
of prescribed sequence of strings given in Table 5.

Table 6.TFC Format Acceptable

by RCViewer
Ist String IInd String IIIrd String IV String Subsequent
Strings
Shows list of all Shows list of all Shows list of all Shows list of all Gates are listed
variables in input variables output variables input constants as per prescribed
network in network in network in network format in order
of appearance in
actual format
between BEGIN
and END
Starts with Starts with Starts with Starts with BEGIN shows
keyword .v/ keyword .i/ keyword .o/ keyword .c/ beginning of
.variables .inputs .outputs .constants Gate/Network
and END shows
termination of
Gate/Network

Any text written after # sign is considered as comment and need to be ignored. Gate representation in .tfc format
is given in Table 6.
 Table 7. Gate Representation in .TFC Format Acceptable by RCViewer
Gate .TFC Format
NOT Gate TOF(Ф;a) t1a
CNOT Gate TOF(a;b) t2a,b
CCNOT Gate TOF(a,b;c) t3 a,b,c
SWAP Gate FRE(Ф;a,b) f2 a,b
FREDKIN Gate FRE(a;b,c) f3 a,b,c
V Gate V
V+ Gate V+

For any reversible circuit, user can view cost metrics analysis using three alternative options. One method is by
clicking on icon named Q in toolbar. Second method is use of shortcut key i.e. ctrl+Q and third method is go to
view option and select quantum cost. After going for any of these methods, cost statistics can be seen on popup
window showing number of inputs/outputs, number of garbage outputs, number of ancillary/constant inputs,
number of gates and further number of one –qubit gates and two-qubit gates and quantum cost. Quantum
realization of popular reversible logic gates with coding are given below:-

6. Quantum Realization Using RCViewer Tool

It is very important to know that out of four 1*1 one qubit gates; only two are reversible i.e. trivial gate and not
gate. Similarly out of 256 possible 2*2 two qubit gates; only 24 are reversible. There exist 16777216 different
3*3 three qubit gates however number of reversible 3*3 gates is much smaller i.e.40320.RCViewer tool is used in
this paper to verify quantum realization of popular reversible logic gates like BJN, double Feynman, Fredkin,
HNG, Morrison, Peres, RC, RC-I, Toffoli, YAG gate and full adder .Quantum statistics in terms of ancillary
inputs, garbage outputs, gate count and quantum cost is also presented. Table 8 shows BJN gate specification,
expression, quantum cost and popular feature. Figure 1 shows quantum realization of BJN gate with coding.

Table 8. BJT Gate Specifications

Reversible Logic Gate Specification Expression Quantum Feature

Cost

BJN/MTG Gate 3*3 5 Universal Logic Gate,

Used for FAN OUT

Quantum realization of BJN gate using NCV library shows three V gates and two CNOT gates, all are unity cost
gates and leads to gate count 5 as well as quantum cost 5. There is no garbage output as well as no ancillary input.
 Figure.1. Quantum realization of BJN gate with coding

Table 9 shows double Feynman gate specification, expression, quantum cost and popular feature. Figure 2 shows
quantum realization of double Feynman gate with coding.
Table 9. Double Feynman Gate Specifications
Reversible Logic Gate Specification Expression Quantum Feature
Cost

Double Feynman Gate 3*3 2 Parity Preserving

Reversible Logic Gate

Quantum realization of double Feynman gate using NCV library shows two CNOT gates, all are unity cost gates
and leads to gate count 2 as well as quantum cost 2. There is no garbage output as well as no ancillary input.
 Figure. 2. Quantum realization of Double
Feynman gate with coding

Table 10 shows Fredkin gate specification, expression, quantum cost and popular feature. Figure 3 shows
quantum realization of Fredkin gate with coding.

Table 10.Fredkin Gate Specifications

Reversible Logic Gate Specification Expression Quantum Feature

Cost

Fredkin Gate/CSWAP 3*3 5 Universal Reversible Logic

Gate Gate, Parity Preserving
Reversible Logic Gate

Quantum realization of Fredkin gate using NCV library shows five CNOT gates, one V gate and one V + gate leads
to gate count 7 and quantum cost 7 but it can also be viewed as three CNOT gates, one combination of CNOT and
V and one combination of CNOT and V +; all are unity cost gates and leads to gate count 5 as well as quantum
cost 5. There is no garbage output as well as no ancillary input.
 Figure. 3. Quantum realization of Fredkin gate with coding

Table 11 shows HNG gate specification, expression, quantum cost and popular feature. Figure 4 shows quantum
realization of HNG gate with coding.

Table 11. HNG Gate Specifications

Reversible Logic Gate Specification Expression Quantum Feature

Cost

HNG Gate
4*4 6 Reversible Adder

Quantum realization of HNG gate using NCV library shows four V and two CNOT gates, all are unity cost gates
and leads to gate count 6 as well as quantum cost 6. There is no garbage output as well as no ancillary input.

Figure. 4. Quantum realization of HNG gate with coding

Table 12 shows Morrison gate specification, expression, quantum cost and popular feature. Figure 5 shows
quantum realization of Morrison gate with coding.

Table 12. Morrison Gate Specifications

 Reversible Logic Gate Specification Expression Quantum Feature
Cost

Morrison Gate 5*5 7 OR,AND

Quantum realization of Morrison gate using NCV library shows two V, one V+ and four CNOT gates, all are unity
cost gates and leads to gate count 7 as well as quantum cost 7. There is no garbage output as well as no ancillary
input.

Figure 5. Quantum realization of Morrison gate with coding

Table 13 shows Peres gate specification, expression, quantum cost and popular feature. Figure 6 shows quantum
realization of Peres gate with coding.

Table 13. Peres Gate Specifications

Reversible Logic Gate Specification Expression Quantum Feature

Cost

Peres Gate/NTG 3*3 4 Lowest Quantum Cost

Quantum realization of Peres gate using NCV library shows two V, one V+ and one CNOT gates, all are unity
cost gates and leads to gate count 4 as well as quantum cost 4. There is no garbage output as well as no ancillary
input.
 Figure 6. Quantum realization of Peres gate with coding

Table 14 shows RC gate specification, expression, quantum cost and popular feature. Figure 7 shows quantum
realization of RC gate with coding.

Table 14. RC Gate Specifications

Reversible Logic Gate Specification Expression Quantum Feature
Cost

RC Gate 4*4 5 Comparator

Quantum realization of RC gate using NCV library shows two V, one V+ and four CNOT gates, all are unity cost
gates and leads to gate count 7 as well as quantum cost 7. But it can also be viewed as two CNOT gates, one V
gate, one combination of CNOT and V and one combination of CNOT and V +; all are unity cost gates and leads to
gate count 5 as well as quantum cost 5. There is no garbage output as well as no ancillary input.
 Figure 7. Quantum realization of RC gate with coding

Table 15 shows RC-I gate specification, expression, quantum cost and popular feature. Figure 8 shows quantum
realization of RC-I gate with coding.

Table 15. RC-I Gate Specifications

Reversible Logic Gate Specifi Expression Quantu Feature

cation m Cost

RC-I Gate 3*3 4 1 bit comparator

Quantum realization of RC-I gate using NCV library shows two V, one V+ and two CNOT gates, all are unity cost
gates and leads to gate count 5 as well as quantum cost 5. But it can also be viewed as one V, one V+ and one
CNOT gates and one combination of CNOT and V gate. It leads to gate count 4 as well as quantum cost 4 .There
is no garbage output as well as no ancillary input.
 Figure 8:.Quantum realization of RC-I Gate with coding

Table 16 shows Toffoli gate specification, expression, quantum cost and popular feature. Figure 9 shows quantum
realization of Toffoli gate with coding.

Table 16. Toffoli Gate Specifications

Reversible Logic Gate Specifi Expression Quantu Feature

cation m Cost

Toffoli/CCNOT Gate[3] 3*3 5 Universal Reversible Logic Gate

Quantum realization of Toffoli gate using NCV library shows two V, one V+ and two CNOT gates, all are unity
cost gates and leads to gate count 5 as well as quantum cost 5. There is no garbage output as well as no ancillary
input.

Figure 9. Quantum realization of Toffoli gate with

coding

Table 17 shows YAG gate specification, expression, quantum cost and popular feature. Figure 10 shows quantum
realization of YAG gate with coding.

Table 17. YAG Gate Specifications

Reversible Logic Specification Expression Quantum Cost Feature
Gate

YAG/UPG Gate 3*3 4 AND,NAND,OR,NOR

Quantum realization of YAG gate using NCV library shows two V, one V+ and two CNOT gates, all are unity cost
gates and leads to gate count 5 as well as quantum cost 5.But it can also be viewed as two V, one CNOT and one
combination of V+ and CNOT leads to gate count 4 as well as quantum cost 4.There is no garbage output as well
as no ancillary input.

Figure 10. Quantum realization of YAG gate with

coding
Quantum realization of three bit adder using NCT and NCV library is given in Figure 11 and using MCT library
is given in Figure 12.

Figure 11. Quantum realization of three bit adder using NCT Library and NCV Library

Figure 12. Quantum realization of three bit adder using MCT Library

7. Conclusions
This paper aims not only give a quick guide on reversible logic gates with their expressions, special features and
quantum cost but also on their quantum implementation to justify quantum cost which are stepping stones in
design and synthesis of any complex reversible logic based synthesis .It moreover bridge gap between theory and
implementation using RCViewer tool. A new researcher may begin with basics of reversible logic gates and
implement optimum reversible logic circuit based on various optimization metrics like ancillary inputs, garbage
outputs, quantum cost. Paper also focus on different representation models of reversible logic based functions,
different reversible logic based synthesis methods , optimization metrics for comparative analysis of different
models and different software tools used in reversible logic based synthesis and optimization

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