Delay PDF
Delay PDF
Delay PDF
VSS logic 0
Logic level matching
• Levels at output of one gate must be
sufficient to drive next gate.
Transfer characteristics
• Transfer curve shows static input/output
relationship—hold input voltage, measure
output voltage.
Noise Margins
• How much noise can a gate input see
before it does not recognize the input?
VDD
β p/β n > 1
Vin Vout
Vin
0
VDD
Logic Levels
• To maximize noise margins, select logic
levels at
– unity gain point of DC transfer characteristic
Vout
β p/β n > 1
Vin Vout
VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|
Noise margin
• Noise margin = voltage difference between
output of one gate and input of next. Noise
must exceed noise margin to make
second gate produce wrong output.
Delay Definitions
• tpdr:
• tpdf:
• tpd:
• tr:
1.5
1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5
0.0
tf
= 0.69 R CL
For rise time replace by the PMOS resistance.
RC Delay Models
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely
d
proportional to width
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise
and fall resistances equal to a unit inverter
(R).
Example: 3-input NAND
• Sketch a 3-input NAND with transistor
widths chosen to achieve effective rise
and fall resistances equal to a unit inverter
(R).
2 2 2
3
3
3
3-input NAND Caps
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2 2 2
3
3-input NAND Capacitors
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
3C
3
3C
3C
3
3C
3C
3
3C
3C
3-input NAND Capacitors
• Annotate the 3-input NAND gate with gate
and diffusion capacitance.
2 2 2
3 9C
5C
3 3C
5C
3 3C
5C
Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC
ladder
• Elmore delay of RC ladder
t pd ≈ ∑ Ri −to − sourceCi
nodes i
C1 C2 C3 CN
Example: 2-input NAND
• Estimate worst-case rising and falling
delay of 2-input NAND driving h identical
gates.
2 2 Y
A 2
h copies
B 2x
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
B 2x 2C h copies
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
B 2x 2C
h copies
t pdr =
R
Y
(6+4h)C
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
B 2x 2C
R h copies
Y
(6+4h)C t pdr = ( 6 + 4h ) RC
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
B 2x 2C h copies
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
B 2x 2C
h copies
x R/2 Y
t pdf =
R/2 2C (6+4h)C
Example: 2-input NAND
• Estimate rising and falling propagation
delays of a 2-input NAND driving h
identical gates.
2 2 Y
A 2 6C 4hC
h copies
B 2x 2C
R/2
t pdf = ( 2C ) ( R2 ) + ⎡⎣( 6 + 4h ) C ⎤⎦ ( R2 + R2 )
x Y
= ( 7 + 4h ) RC
R/2 2C (6+4h)C
Delay Components
• Delay has two parts
– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
CMOS inverter delay
• An approximate method:
– Assume constant Iavg
– The NMOS and the PMOS I1
are in saturated region and V1=Vcc
provide a constant current.
CloadVCC V2=½Vcc
t PHL =
k n (VCC − VTn )
2
CloadVCC
t PLH =
t1 t2
k p (VCC − VTP ) 2
Iavg = I1
Some Points
• The delay of a gate, be it the rise or the fall
time is inversely proportional to VDD.
• Point to ponder: Effect of sizing on the
inverter gate delay.