Tfs757-764Hg Hipertfs Family

TFS757-764HG
HiperTFS Family
™
Combined Two-Switch Forward and Flyback Power Supply Controllers

with Integrated High Voltage MOSFETs
Key Benefits Applications

• Single chip solution for two-switch forward main and flyback • PC
standby • Printer
• High integration allows smaller form factor and higher power • LCD TV
density designs • Video game consoles
• Incorporates control, gate drivers, and three power • High-power adapters
MOSFETS • Industrial and appliance high-power adapters
• Level shift technology eliminates need for pulse transformer
• Protection features include: UV, OV, OTP, OCP, and SCP Output Power Table
• Transformer reset control Two-Switched Forward Flyback
• Prevents transformer saturation under all conditions 380 V 100 V - 400 V
• Allows >50% duty cycle operation
Product
Continuous Continuous Peak
• Reduces primary side RMS currents and conduction losses 50 °C
(25 °C) (50 °C) (50 °C)
• Standby supply provides built-in overload power compensation TFS757HG 193 W 163 W 228 W 20 W
• Up to 434 W total output power in a highly compact package TFS758HG 236 W 200 W 278 W 20 W
• Up to 550 W peak TFS759HG 280 W 235 W 309 W 20 W
• High efficiency solution easily enables design to meet TFS760HG 305 W 258 W 358 W 20 W
stringent efficiency specifications TFS761HG 326 W 276 W 383 W 20 W
• >90% efficiency at full load TFS762HG 360 W 304 W 407 W 20 W
• No-load regulation and low losses at light-load TFS763HG 388 W 327 W 455 W 20 W
• Simple clip mounting to heat sink without need for insulation pad
TFS764HG 414 W 344 W 530 W 20 W
• Halogen free and RoHS compliant
Table 1. Output Power Table (See Notes on page 13).
Main Output
HiperTFS VDDH HD
HS
L
D
Two-Switch Forward
Transformer Auxiliary/Standby
Output
DC RTN
Input Control,
Gate Drivers, R
FB Level Shift
DSB
EN FB
Flyback
Transformer
FB BP
EN
EN
G S
PI-6200-102910
Figure 1. Simplified Schematic of Two-Switch Forward and Flyback Converter.
www.powerint.com February 2011

TFS757-764HG
Section List
Description................................................................................................................................................................... 3
Product Highlights....................................................................................................................................................... 3
Pin Functional Description.......................................................................................................................................... 5
Pin Configuration....................................................................................................................................................... 5.
Functional Block Diagram......................................................................................................................................6-7.
Functional Description ................................................................................................................................................ 8
Output Power Table................................................................................................................................................ 13
Design, Assembly, and Layout Considerations..................................................................................................... 14
Application Example.................................................................................................................................................. 20
Absolute Maximum Ratings...................................................................................................................................... 23
Parameter Table...................................................................................................................................................... 23
Typical Performance Characteristics..................................................................................................................29-33.
Package Details ......................................................................................................................................................... 34
Part Ordering Information......................................................................................................................................... 35
Part Marking Information ......................................................................................................................................... 35
2
Rev. C 02/11 www.powerint.com
TFS757-764HG
Description • Programmable line overvoltage (OV) detection; latching and

The HiperTFS device family members incorporate both a non-latching
high-power two-switch-forward converter and a mid-power • Accurate hysteretic thermal shutdown (OTP)
flyback (standby) converter into a single, low-profile eSIP™ • Accurate selectable current limit (main and standby)
power package. The single chip solution provides the controllers • Output over-current protection (OCP)
for the two-switch-forward and flyback converters, high- and • Fully integrated soft-start for minimum start-up stress
low-side drivers, all three of the high-voltage power MOSFETs, • Simple fast AC reset
and eliminates the converter’s need for costly external pulse • Reduced EMI
transformers. The device is ideal for high power applications • Synchronized 66 kHz forward and 132 kHz flyback
that require both a main power converter (two-switch forward) converters
up to 414 W, and standby converter (flyback) up to 20 W. • Frequency jitter
HiperTFS includes Power Integrations’ standard set of comprehen- • Eliminates up to 30 discrete components for higher reliability
sive protection features, such as integrated soft-start, fault and and lower cost
over-load protection, and hysteretic thermal shutdown.
Asymmetrical Two-Switch Forward Reduces Losses
HiperTFS utilizes advanced power packaging technology that
• Allows >50% duty cycle operation
simplifies the complexity of two-switch forward layout, mounting
• Reduces primary side RMS currents and conduction losses
and thermal management, while providing very high power
• Minimizes the size and cost of the bulk capacitor
capabilities in a single compact package. The devices operate
• Allows reduced capacitance or longer hold-up time
over a wide input voltage range, and can be used following a
• Allows lower voltage output diodes
power-factor correction stage such as HiperPFS.
• Transformer reset control
• Prevents transformer saturation under all conditions
Two-switch-forward power converters are often selected for
• Extends duty cycle to satisfy AC cycle drop out ride through
applications demanding cost-effective efficiency, fast transient
• Duty cycle soft-start with 115% current limit boost
response, and accurate tolerance to line voltage fluctuation. The
• Satisfies 2 ms ~ 20 ms start-up with large capacitance at
two-switch-forward controller incorporated into HiperTFS
output
devices improves on the classic topology by allowing operation
• Output short circuit protection (SCP) with auto-restart
considerably above 60% duty cycle. This improvement reduces
• Remote ON/OFF function
RMS currents conduction losses, minimizes the size and cost of
• Voltage mode controller with current limit
the bulk capacitor, and minimizes output diode voltage ratings.
The advanced design also includes transformer flux reset 20 W Flyback with Selectable Power Limit
control (saturation protection) and charge-recovery switching of • TinySwitch-III based converter
the high-side MOSFET, which reduces switching losses. This • Selectable power limit (10 W, 12.5 W, 15 W, or 20 W)
combination of innovations yields an extremely efficient power • Built-in overload power compensation
supply with smaller MOSFETs, fewer passives and discrete • Flat overload power vs. input voltage
components, and a lower-cost transformer. • Reduces component stress during overload conditions
• Reduces required design margin for transformer and output
HiperTFS’s flyback standby controller and MOSFET solution is diode
based on the highly popular TinySwitch™ technology used in • Output overvoltage (OV) protection with fast AC reset
billions of power converter ICs due to its simplicity of operation, • Latching, non-latching, or auto-restart
light load efficiency, and rugged, reliable, performance. This • Auto-restart
flyback converter can provide up to 20 W of output power and Advanced Package for High Power Applications
the built in overload power compensation reduces component • 434 W output power capability in a highly compact package
design margin. • Up to 550 W peak
• Simple clip mounting to heat sink
Product Highlights
• Can be directly connected to heat sink without insulation pad
Protected Two-Switch Forward and • Provides thermal impedance equivalent to a TO-220
Flyback Combination Solution • Heat slug connected to ground potential for low EMI
• Incorporates three high-voltage power MOSFETs, main and • Staggered pin arrangement for simple routing of board traces
standby controllers, and gate drivers and high-voltage creepage requirements

• Level shift technology eliminates need for pulse transformer • Single power package for two power converters reduces
• Programmable line undervoltage (UV) detection prevents assembly costs layout size
turn-off glitches
3
www.powerint.com Rev. C 02/11
TFS757-764HG
Typical Two-Switch
Function Forward HiperTFS Advantages of HiperTFS
Nominal Duty Cycle 33% 45% Wider duty cycle reduces RMS switch currents by 17%.
Maximum Duty Cycle <50% 63% Reduces RDS(ON) losses by 31%
Switch Current (RMS) 100% 83%

Output Catch Diode VO + VD/DMAX VO + VD/DMAX Lower losses. Wider DMAX lowers catch diode rating by
(1-(50%/63%)) = 21% reduction in catch diode voltage
rating
Clamp Voltage Reset diodes from zero Reset from zero to With fast/slow diode combination, allows charge
to VIN (VIN + 130) recovery to limit high-side COSS loss
Thermal Shutdown --- 118 °C Shutdown / HiperTFS provides integrated OTP device protection
55 °C hysteresis
Current Sense Resistor 0.5 V drop (0.33 W at Sense resistor not Improved efficiency. MOSFET RDS(ON) sense eliminated
300 W) required need for sense resistor
High-Side Drive Requires gate-drive Built in high-side drive Lower cost; component elimination. Removes
transformer (high cost) high-cost gate-drive transformer (EE10 or toroid)
Component Count Higher Lower Saves up to 50 components, depending on specification.
TinySwitch Overload Power --- Built-in compensation Safer design; easier to design power supply. Flattens
Compensation vs. Input Voltage overload output power over line voltages
Package Creepage TO-220 = 1.17 mm eSIP16/12 = 2.3 mm/ HiperTFS meets functional safety spacing at package
3.3 mm pins
Package Assembly 2 × TO-220 package, 2 1 Package No SIL (insulation) pad required
× SIL (insulation)
Table 2. Summary of Differences Between HiperTFS and Other Typical High Power Supplies.
4
TFS757-764HG
Pin Functional Description BYPASS (BP) Pin

This is the decoupled operating voltage pin for the low-side
MAIN DRAIN (D) Pin controller. At start-up the bypass capacitor is charged from an
Drain of the low-side MOSFET transistor forward converter. internal device current source. During normal operation the
capacitor voltage is maintained by drawing current from the
STANDBY DRAIN (DSB) Pin low-side bias winding on the standby power supply. This pin is
Drain of the MOSFET of standby power supply. also used to implement remote ON/OFF for the main controller.
This is done by driving extra current into the BYPASS pin when
GROUND (G) Pin
we want to turn-on the Main controller. The BYPASS pin also
This pin gives a signal current path to the substrate of the
implements a latch-off function to disable standby and main
low-side controller. This pin is provided to allow a separate
when the BP pin current exceeds latching threshold. Latch is
Kelvin connection to the substrate of the low-side controller to
reset when LINE-SENSE pin falls below UV (off) standby
eliminate inductive voltages that might be developed by high
threshold.
switching currents in the SOURCE pin. The GROUND pin is
not intended to carrier high currents, instead it is intended as a HIGH-SIDE OPERATING VOLTAGE (VDDH) Pin
voltage-reference connection only. This is the high-side bias (VDD) of approximately 11.5 V. This
voltage is maintained with current from a high-side bias winding
SOURCE (S) Pin
on the main transformer and/or from a bootstrap diode from the
SOURCE pin that is common to both the standby and main
low-side standby bias supply.
supplies.
HIGH-SIDE SOURCE (HS) Pin
RESET (R) Pin
SOURCE pin of the high-side MOSFET.
This pin provides information to limit the maximum duty cycle as a
function of the current fed into the RESET pin during the off-time HIGH-SIDE DRAIN (HD) Pin
of the main converter MOSFET. This pin can also be pulled up to DRAIN pin of the high-side MOSFET. This MOSFET is floating
bypass to signal remote ON/OFF of the main converter only. with respect to low-side source and ground.
ENABLE (EN) Pin
This is the ENABLE pin for the standby controller. Prior to the H Package (eSIP-16/12)
start-up a resistor connected from ENABLE to BYPASS, can be
detected to select one of several internal current limits.
LINE-SENSE (L) Pin

This pin provides input bulk voltage line-sense function. This
information is used by the undervoltage and overvoltage
detection circuits for both main and standby. The pin can also Exposed Metal
be pulled up to BYPASS or be pulled down to SOURCE to (On Edge)
Internally 1 3 5 6 7 8 9 10 11 13 14 16
implement a remote ON/OFF of both standby and main Connected
D
DSB
G
S
R
EN
L
FB
BP
VDDH
HS
HD
supplies simultaneously. The LINE-SENSE pin works in
conjunction with the RESET pin to implement a duty-cycle limit
function. Also the LINE-SENSE pin compensates the value of
HD
HD
HS
standby current limit so as to flatten the output overload

S
response as a function of input voltage.
FEEDBACK (FB) Pin

This pin provides feedback for the main two transistor forward Exposed Pad
converter. An increase in current sink from FEEDBACK pin to (Backside) Internally
ground, will lead to a reduction in operating duty cycle. This pin Connected to SOURCE
Pin (see eSIP-16B
also selects the main device current limit at start-up (in a similar Package Drawing)
manner to ENABLE pin).
PI-5290-110510
Figure 2. Pin Configuration.
5
TFS757-764HG
HIGH-SIDE
OPERATING VOLTAGE (VDDH) HIGH-SIDE
DRAIN (HD)
VDDH
UNDERVOLTAGE
+
HSD1 11.1 V
12 V 9.9 V
HSD2
S Q
DISCRIMINATOR R
HIGH-SIDE
SOURCE (HS)
PI-5516-060410
BYPASS (BP) HSD1 HSD2
DRAIN (D)
MAIN REMOTE-ON FAULT PRESENT GATE
HS
PWM INPUT
VILIMIT
REMOTE OFF
SOFT-START
DSS
FEEDBACK (FB)
and MAIN CURRENT 3 V+VT
LIMIT SELECT
POWER ON
ILIMIT
SELECT
-
+
R DMAX
RESET (R) CURRENT LIMIT
DUTY GATE COMPARATOR
REMOTE
OFF CYCLE
LIMIT CLK
L ON
LINE-SENSE (L) CONTROLLED

STOP TURN-ON
VBG
GATE DRIVER
LINE
SENSE
LV
S Q
LEADING
- EDGE
R
BLANKING
+
PWM
COMPARATOR
LV D2MAX CLK2 SAW PWM THERMAL SD SOURCE (S)

INPUT
PI-5263-021511
Figure 3. Functional Block Diagram for Two-Switch Forward Converter.
6
TFS757-764HG
LV (LINE VOLTAGE)
BYPASS (BP) STANDBY DRAIN (DSB)
REGULATOR
5.7 V
115 µA
FAULT BYPASS PIN
6.0 V PRESENT UNDER-VOLTAGE
+
AUTO- ENABLE PULL
RESTART -
UP RESISTOR
COUNTER SELECT AND 5.7 V VI
CURRENT 4.7 V VIN LIMIT
RESET ILIMIT
LIMIT STATE
MACHINE ADJUST
CURRENT LIMIT
COMPARATOR
ENABLE -
+
JITTER
CLOCK
CLK2
ENABLE (EN) 1.0 V + VT
and STANDBY DCMAX THERMAL
CURREN LIMIT SHUTDOWN
D2MAX
SELECT
SAW
1.0 V OSCILLATOR S Q
R Q
MAIN LEADING
REMOTE EDGE
ON/ BLANKING
OVP
LATCH OFF
SOURCE (S)
SAW D2MAX
PI-5264-020510
MAIN CLK2 FAULT THERMAL SD
REMOTE PRESENT
ON
Figure 4. Functional Block Diagram for Flyback/Standby Converter.
7
TFS757-764HG
Functional Description
PI-4530-041107
fOSC +
The HiperTFS contains two switch-mode power supply Switching
controllers and associated low-side MOSFET’s along with Frequency
fOSC -
high-side driver and high-side MOSFET.
• The HiperTFS two-switch forward includes a controller along 4 ms

with low-side power MOSFET, high-side power MOSFET and
high-side driver. This device operates in voltage mode (linear
VDRAIN
duty-cycle control) at fixed frequency (exactly half the operat-
ing frequency of the standby controller). The control converts
a current input (FEEDBACK pin), to a duty-cycle at the open Time
drain MOSFET MAIN DRAIN pin decreasing duty-cycle with
increasing sourced current from the FEEDBACK pin. Figure 5. Switching Frequency Jitter (Idealized VDRAIN Waveforms).
• The HiperTFS flyback includes a controller and power MOSFET Main Start-Up Operation
which is based on TinySwitch-III. This device operates in Once the flyback (standby) converter is up and running, the
multi-level ON/OFF current limit control mode. The open drain main converter can be enabled by two functions. The first
MOSFET (STANDBY DRAIN pin) is turned on when the sourced condition is that the BYPASS pin remote-on current must
current from the ENABLE pin is below the threshold and exceed the remote-on threshold (IBP(ON)), provided by an external
switching is disabled when the ENABLE pin current is above remote ON/OFF circuit. This current threshold has a hysteresis
the threshold. to prevent noise interference. Once the BYPASS remote-on
has been achieved, the HiperTFS also requires that the LINE-
In addition to the basic features, such as the high-voltage SENSE pin current exceeds the UV Main-on (IL(MA-UVON)), which
start-up, the cycle-by-cycle current limiting, loop compensation corresponds to approximately 315 VDC input voltage when
circuitry, auto-restart and thermal shutdown, the HiperTFS main using a 4 MW LINE-SENSE pin resistor. Once this LINE-SENSE
controller incorporates many additional functions that reduce pin threshold has been achieved the HiperTFS will enter a 12 ms
system cost, increase power supply performance and design pre-charge period (tD(CH)) to allow the PFC-boost stage to reach
flexibility. regulation before the main applies a load to the bulk-capacitor.
Also during this pre-charge period the high-side driver is
Main Converter General Introduction charged via the boot-strap diode from the low-side auxiliary
The Main converter for the HiperTFS, is a two-switch forward voltage, and is charged when the main low-side MOSFET turns
converter (although the HiperTFS could be used with other
two-switch topologies). This topology involves a low-side and
high-side power MOSFET, both of which are switched at the VIN
same time. In the case of the HiperTFS, the low-side MOSFET 385 V
is a 725 V MOSFET (with the substrate connected to the
t
SOURCE pin). The high-side MOSFET is a 530 V MOSFET
(with the substrate connected to the HIGH-SIDE DRAIN (HD) Standby
pin). As such the substrate of both low-side and high-side Output
MOSFET’s are tied to quiet circuit nodes (0 V and VIN t
respectively), meaning that both MOSFETs have electrically
quiet substrates – good for EMI. Main
Output
The low-side MOSFET has a very low COSS capacitance and

thus can be hard-switched without performance penalty. Due
to the external clamp configuration it is possible to substantially 12 ms t
soft-switch the high-side MOSFET at high-loads (thus 32 ms
eliminating a large proportion of high-side capacitive switching Main 12 ms 115% ILIM
Primary 100% ILIM
loss) and improving efficiency. The higher breakdown voltage Current
on the low-side MOSFET allows the transformer reset voltage to
exceed the input voltage, and thus allow operation at duty
cycles greater than 50%. Higher duty cycle operation leads to t
lower RMS switch currents and also lower output diode
voltage-rating, both of which contribute to improved efficiency. Remote ON
The HiperTFS also contains a high-side driver to control the t

high-side MOSFET. This internal high-side driver eliminates the PI-5619a-102710
need for a gate-driver transformer, an expensive component
that is required for many other two-switch forward circuits. Figure 6. Supply Start-Up Sequence by Remote ON.
8
TFS757-764HG
on, while the main high-side MOSFET is held off. By the end of The HIGH-SIDE OPERATING VOLTAGE pin has an undervoltage
the pre-charge period, the PFC-boost voltage should be at or lock-out threshold, to prevent gate-drive when the supply voltage
above the nominal boost voltage. The HiperTFS begins drops below a safe threshold. At power-up the high-side driver
switching, going through the soft-start period (tSS). During the remains in the off-state, until the HIGH-SIDE OPERATING
soft-start period the maximum duty cycle starts at 30% and is VOLTAGE pin is charged above 10.5 V, at which point the
ramped during a 12 ms period to the maximum. The ramped high-side driver becomes active. The high-side driver is initially
duty cycle controls the rise slew rate of the output during charged via a boot-strap diode connected via a diode to the
start-up, allowing well controlled start-up and also facilitates a HIGH-SIDE OPERATING VOLTAGE pin from the low-side
smooth transition when the control loop takes over regulation standby auxiliary supply (approximately 12 V). During start-up
towards the end of soft-start. Also during a 32 ms period the high-side MOSFET remains off, but the low-side MOSFET is
(starting at the beginning of soft-start), the main current limit is turned on for a period of 14 ms to allow pre-charge of the
boosted to 115% of the nominal selected Main current. This high-side operating voltage to 12 V. After this period, the high-
allows the main to start-up within the required period for the side operating voltage is supplied by a forward-winding coupled
application (typically < 20 ms for PC main applications), when to the main transformer. This floating winding provides energy
there is a substantial capacitive load on the output. After the every time the main converter switches one cycle. The
soft-start period, the current limit returns to 100% of the operating power for high-side operating voltage can also be
nominal selected current limit. provided from a floating winding on the standby supply.
However this would continue delivering power even when the
Main Converter Control FEEDBACK (FB) Pin Operation main converter is in remote-off, and thus is considered
The FEEDBACK pin is the input for control loop feedback from undesirable from a standby light-load efficiency point of view.
the main control loop. During normal operation the FEEDBACK
pin is used to provide duty cycle control for the main converter. Once the high-side driver is operating it receives level-shifted
The system output voltage is detected and converted into a drive commands from the low-side device. These drive
feedback current. The main converter duty cycle will reduce as commands cause both turn-on and turn-off drive of the
more current is sourced from the FEEDBACK pin, reaching zero high-side main MOSFET simultaneously with that of the
duty cycle at approximately 2.1 mA. The nominal voltage of the low-side main MOSFET.
FEEDBACK pin is maintained at approximately 3.5 V. An
internal pole on the FEEDBACK pin is set to approximately The high-side driver also contains a thermal shutdown on-chip,
12 kHz, in order to facilitate optimal control loop response. but this is set to a temperature above the thermal shutdown
temperature of the low-side device. Thus the low-side will
The maximum duty cycle of the main converter is defined by the always shutdown first.
LINE-SENSE pin and RESET pin behavior and is a dynamically
calculated value according to cycle-by-cycle conditions on the Main Converter Maximum Duty Cycle
LINE-SENSE pin and RESET pin. The LINE-SENSE pin resistor converts the input voltage into an
LINE-SENSE pin current signal. The RESET pin resistor
converts the reset voltage into an RESET pin current signal.
Duty (D)
The LINE-SENSE pin and RESET pin currents allow the
78% HiperTFS to determine a maximum duty cycle envelope on a
IL = 60 µA Typical IL and IR
IR = 170 µA currents at VMIN cycle-by-cycle basis. This feature ensures sufficient time for
63% transformer reset on a cycle-by-cycle basis and also protects
Limited by L & R against single-cycle transformer saturation and at high-input
pin duty limit
voltage by limiting the maximum duty cycle to prevent the
transformer from reaching an unsafe flux density during the
FEEDBACK Pin
Current IFB on-time period. Both of these features allow the optimal
0%
performance to be obtained from the main transformer. The
1 mA 2.1 mA duty cycle limit is trimmed during production.
PI-5885-082610
Figure 7. PWM Duty Cycle vs. Control Current. The LINE-SENSE pin and RESET pin are sampled just before
the turn-on of the next main cycle. This is done to sample at a
Main High-Side Driver point when there is minimal noise in the system. Due to the low
The high-side driver is a device that is electrically floating at the current signal input to the LINE-SENSE pin and RESET pin,
potential of the HIGH-SIDE MOSFET SOURCE (HS) pin. This care should be taken to prevent noise injection on these pins
device provides gate-drive for the high-side Main MOSFET. The (see Applications section layout guidelines for details).
low-side main and high-side main MOSFET’s switch simul-
taneously. The high-side driver has a HIGH-SIDE OPERATING Main On-Chip Current Limit with External Selection
VOLTAGE supply pin. External circuitry provides a current During start-up, the FEEDBACK pin and ENABLE pin are both
source into this HIGH-SIDE OPERATING VOLTAGE pin. The used to select internal current limits for the main and standby
high-side operating voltage has an internal 12 V shunt-regulator. converters respectively. The detection period occurs at the
The device consumes approximately 2 mA when driving the initial start-up of the device, and before the main or standby
high-side MOSFET. MOSFETs start switching. This is done to minimize noise
interference.
9
TFS757-764HG
0.7
PI-5977-061010
IL = 60 µA
Duty Cycle Limit IL = 90 µA

0.6
IL = 100 µA
0.5
IL = 115 µA
0.4
0.5 1.0 1.5 2.0 2.5 3.0
IR/IL
Figure 8. Duty Cycle Limit vs. Ratio of R Pin Current Over L Pin Current.
A resistor RFB is connected from the BYPASS pin to the Main Line Undervoltage Detection (UV)
FEEDBACK pin. This resistor feeds current into the FEEDBACK The LINE-SENSE pin resistor is connected to VIN and generates
pin (who’s voltage is clamped to approximately 1 V during this a current signal proportional to VIN. The LINE-SENSE pin voltage
detection period). The current into the FEEDBACK pin is is held by the device at 2.35 V. The LINE-SENSE pin current
determined by the value of the resistor, and thus the input signal is used to trigger under/overvoltage thresholds for both the
current (and indirectly the resistor value), select an internal standby and main converters. Assuming a LINE-SENSE pin
current limit according to the following table. resistor of 4 MW, the standby will begin operating when the
LINE-SENSE pin current exceeds the (IL(SB-UVON)) threshold,
IFB REN(SELECT) nominally approximately 100 V. However the main is still held in
ILIMIT the off-state, until the LINE-SENSE pin current exceeds the
(Threshold) (1%)
(IL(MA-UVON)) threshold, nominally 315 V for 4 MW. There is
0.0-5.1 mA L1 60% mA Open kW hysteresis for both main and standby undervoltage-off
5.1-11.9 mA L2 80% mA 511.0 kW thresholds, to allow sufficient margin to avoid accidental
triggering, and to provide sufficient margin to meet hold-up time
11.9-23.8 mA L3 100% mA 232.0 kW requirements. Bear in mind that the main converter may start to
loose regulation before it finally shuts down. This is because
Table 3. FEEDBACK Pin Main Current Limit Selection.
the dynamic duty cycle limit may clamp the duty cycle below
that required for regulation at lower input voltages. Once the
UV(ON)STANDBY, I(L) = 25 µA
input voltage falls below the 215 V (IL(MA_UVOFF)) threshold, the
main will shutdown but standby will continue to operate. The
standby will turn off when the input voltage drops below
approximately 40 V (IL(SB-UVON)).
I(L) 4.7 V 6.0 V after
standby
5.7 V acheives
V(BP) regulation
1V
2.7 V
V(FB)
V(EN) 2.2 V
TSELECT - current limit selection occurs here during

device start-up and before power supply switching
PI-5975-102610
Figure 9. Current Limit Selection.
10
TFS757-764HG
Standby Power General Introduction

Supply Start-Up Sequence The standby is a wide range power supply, typically a flyback
VIN converter, operating over a wide input range (85-265 VAC) and
delivering up to 20 W continuous output power. The standby
385 V
power supply provides two functions in most high-power
315 V applications. It provides a direct secondary output but also
provide bias power to other primary-side devices (in particular
typically a PFC boost converter).
100 V
The HiperTFS standby retains most features of the TinySwitch-III,
such as auto-restart, thermal shutdown, multi-level current limit
30 V ON/OFF control, etc. The HiperTFS standby controller has a
few differences versus TinySwitch-III:
Standby 1. There are 4 current limits that are selected via the ENABLE
Output
pin (rather than by using different BYPASS pin capacitors as
in TinySwitch-III). There are 4 user selectable current limits
500, 550, 650, 750 mA design for secondary standby
12 ms 2-20 ms
Main output power of 10, 12.5, 15 and 20 W.
Output
2. Secondary OVP latching shutdown. This is triggered via a
current in excess of the BYPASS pin latching shutdown
threshold (IBP(SD) = 15 mA).
3. Dedicated LINE-SENSE pin for line-voltage detection providing
6.0 V absolute UV and OV ON/OFF thresholds (unlike TinySwitch-III
VBP which detects input voltage only during restart).
5.7 V 4. Current limit is compensated as a function of input voltage
4.7 V to maintain a flat overload characteristic versus input voltage.
PI-5611a-062710
In a high-power system, the standby power supply is the first
power supply to begin operating. The main converter cannot
Figure 10. Main and Standby Start-Up.
begin working until the standby is in operation. Likewise the
main converter will shutdown at a higher-voltage than the standby
Main Reset Overvoltage Detection
and thus the standby is always the last power supply to
There is also an overvoltage threshold for the RESET pin. When
shutdown.
triggered, the RESET overvoltage will shutdown only the Main,
leaving the Standby in operation. Standby On-Chip Current Limit with External Selection
During start-up, the FEEDBACK pin and ENABLE pin are both
used to select internal current limits for the Main and Standby
converters respectively. The detection period occurs at the
VIN initial start-up of the device (just after BYPASS pin voltage of
385 V
To VIN 4.7 V is achieved), and before the main or standby MOSFETs
To Clamp
Reset Circuit start switching. This is done to minimize noise interference.
300 V
RL RR
I EN R EN (Select)
ILIMIT
HiperTFS
240 V R (Threshold) (1%)

L
0.0-8.5 mA L1 500 mA Open kW
40 V
8.5-17.7 mA L2 650 mA 280.0 kW
17.7-33.0 mA L3 750 mA 137.0 KW

Standby
Output
33.0-66.0 mA L4 550 mA 63.4 kW
tHOLDUP Table 4. ENABLE Pin Standby Current Limit Selection.

Main Typically turned off by
≥ 20 ms secondary supervisor
Output
circuit, once regulation
below limit The ENABLE pin works in a similar way to the FEEDBACK pin
t1 t2 t3 t4 selection. The only difference being that the ENABLE pin is not
PI-5612a-060910
clamped to 1 V during selection, instead remaining at 2.35 V
during the detection period. Thus the selection resistor values
Figure 11. L and R Pin Duty Limit Mode.
11
TFS757-764HG
are slightly different for the ENABLE pin versus the FEEDBACK However the standby will be forced to shutdown if this input
pin. The ENABLE pin internal current selection is chosen voltage drops below approximately 40 V (as defined by IL(SB-UVOFF)).
according to the above table.
Main and Standby Oscillator and Switching Frequency
The current limit selection for both FEEDBACK pin and ENABLE The standby converter operates at a frequency of 132 kHz. The
pin takes place when the BYPASS pin first reaches 4.7 V. Once main converter operates at exactly half that frequency at 66 kHz.
the short detection period is complete, the BYPASS pin is The two converters both include a common frequency jitter
ramped on up to 5.7 V, and the FEEDBACK pin is allowed to profile that varies the switching frequency ±4 kHz for the main
float to it’s nominal voltage of 3.5 V. (twice the jitter frequency range ±8 kHz for the standby), during
a 4 ms jitter period. The frequency jitter helps reduce quasi-
Standby Line Compensated Current Limit peak and average EMI emissions.
to Flatten Output Overload
For many power supplies, the power output capability of the It should be noted that the HiperTFS has a collision avoidance
power supply increases dramatically as the input voltage scheme in which the main converter is the master and the
increases. This means that most power supplies are able to standby is the slave, which avoids the main and standby switching
deliver much more power (up to 30-40% more power), into a at exactly simultaneous moments. The most common
fault overload when operating at higher input voltage (versus condition would be close to 50% duty cycle, if the main (master)
operating at lower input voltage). This can cause a problem is about to switch (turn-off), then the standby (slave), waits for
since many specifications require that the output overload short instant (200 ns) before starting it’s next cycle. The
power capability of the device is more tightly managed. standby is used as the slave, since the ON/OFF control of the
HiperTFS standby is less easily disrupted by sudden delays in
In the case of the HiperTFS, the standby current limit is adjusted switching, versus the linear control loop of the main converter.
as a function of line (input voltage), in such a ways as to always
provide substantially the same maximum overload power Standby and Main Thermal Shutdown
capability. The input voltage is detected via the LINE-SENSE The HiperTFS provides a thermal shutdown function, (OTP) that
pin current and the internal standby current limit of the device is protects the HiperTFS. This hysteretic thermal shutdown allows
adjusted accordingly on a cycle-by-cycle basis. This means that the device to automatically recover from any thermal fault event.
the HiperTFS standby will only deliver approximately 5% more The thermal shutdown is triggered at a die-temperature of
overload power at high-line as it did at low-line. This feature approximately 118 °C and has a high hysteresis to ensure the
provides a much safer design. average device temperature is within safe levels. In a well
designed system the HiperTFS thermal shutdown is not
150 triggered during any normal operation and is only present as a
PI-5884-052510
safety feature to protect against abnormal or fault conditions.

Output Overload Power (%)
140
Not Compensated
BYPASS (BP) Pin Operation
130
The BYPASS (BP) pin is the supply pin for the entire HiperTFS
120
device. The BYPASS pin is internally connected to a high-voltage
current source via the STANDBY DRAIN power MOSFET. This
110 high-voltage source will charge the BYPASS pin to 4.7 V during
Compensated initial power up. Once the BYPASS pin reaches 4.7 V, the
100 BYPASS pin will check the main and standby current limit
selection (FEEDBACK pin and ENABLE pin resistors respectively).
90 This selection takes a very short period, thereafter the BYPASS
pin continues being charged until it reaches 5.7 V, at which
80
point the standby power supply is ready to begin operation.
50 100 150 200 250 300 350 400 450
Like the TinySwitch-III the high-voltage current source will
VIN DC (V) continue to charge the BYPASS pin if it droops below 5.7 V.
Figure 12. Shows Output Overload Power for Both Compensated and
However in most typical applications, a resistor (typically 7.5 kW)
Uncompensated Standby Current Limits. is connected from primary bias (12 V) to the BYPASS pin. This
resistor provides the operating current to the BYPASS pin,
Standby Line Undervoltage Detection (UV) preventing the need to draw power from the high-voltage
The LINE-SENSE pin resistor is connected to VIN and generates current source. Like the TinySwitch-III, the BYPASS pin contains
a current signal proportional to VIN. The LINE-SENSE pin a shunt regulator, which will be enabled if the BYPASS pin
voltage is held by the device at 2.35 V. The LINE-SENSE pin voltage is externally driven above 5.7 V. The BYPASS pin shunt
current signal is used to trigger under/overvoltage thresholds for current is used for two functions:
both the standby and main converters. Assuming a LINE-SENSE
pin resistor of 4 MW, the standby will begin operating at 1. First, for a 4 mA threshold (IBP(ON)) for main remote-on. When
approximately 100 V (as defined by IL(SB_UVON)). The standby will the BYPASS pin current exceeds this threshold, the main is
shutdown if regulation is lost when input voltage is below 100 V. enabled.
12
TFS757-764HG
2. Second a 15 mA threshold (IBP(SD))for standby secondary OVP Output Power Table

latch-off. When the BYPASS pin current exceeds this Two-Switched Forward Flyback
threshold, the standby and main converters are latched-off. 380 V 100 V - 400 V
This latch can be reset by pulling the LINE-SENSE pin below Product 2
Continuous1 Continuous1 Peak

the line undervoltage threshold (IL(SB-UVOFF)), or by discharging 50 °C
(25 °C) (50 °C) (50 °C)
the BYPASS pin below 4.7 V. TFS757HG 193 W 163 W 228 W 20 W
TFS758HG 236 W 200 W 278 W 20 W
Note: unlike the TinySwitch-III the HiperTFS BYPASS pin capacitor TFS759HG 280 W 235 W 309 W 20 W
does not provide any programming capability. Instead the TFS760HG 305 W 258 W 358 W 20 W
recommended BYPASS pin capacitor should always be a 1 mF TFS761HG 326 W 276 W 383 W 20 W
(ceramic) capacitor. TFS762HG 360 W 304 W 407 W 20 W
TFS763HG 388 W 327 W 455 W 20 W
Main and Standby Line Overvoltage Detection (OV)
TFS764HG 414 W 344 W 530 W 20 W
The overvoltage threshold is included in the device, and can be
Table 5. Output Power Table.
used to disable the device during overvoltage (with the use of
Notes:
an additional external signal Zener). The overvoltage threshold 1. Maximum practical continuous power in an open frame design with adequate
is set sufficiently high to prevent accidental triggering during heat sinking (assuming heat sink θC-A of <4 °C/W), measured at specified
boost PFC overshoot conditions. When the overvoltage ambient temperature (see Key Applications Considerations for more information).
2. Package: eSIP16/12. (Note: Direct attach to heat sink, does not require
condition is triggered, it will simultaneously shutdown both the insulation SIL pad)
Main and Standby. The overvoltage feature is intended for use
with external components (circuitry), to program the overvoltage
threshold independently of the undervoltage thresholds (see the
Applications section for details).
High-Power eSIP Package

The HiperTFS package is designed to minimize the physical size
of the device, while maintaining a low thermal impedance and
sufficient electrical spacing for the pins. The package has 12
functional pins with 4 pins removed for increased pin-to-pin
spacing between high-voltage pins. The low-side two-switch
forward and flyback MOSFETs have a thermal impedance of
less than 1 °C/W to the exposed pad on the back of the
package. Since this pad is referenced to the SOURCE pin
(Source), it is at electrical ground potential and thus can be
connected to the heat sink without need for electrical insulation.
The high-side MOSFET is over-molded to achieve electrical
isolation and thus also allows direct connection to the heat sink.
13
TFS757-764HG
Design, Assemble and Layout Considerations 80
PI-2576-010600
70
Power Table
60
The data sheet power table (Table 1, page 1) represents the
Amplitude (dBµV)
50
maximum advised continuous power based on the following
conditions; 40
30
1. Typical multi-output PC main with the following outputs +12 V,
20
+5 V, +3.3 V, -12 V, and +5 V standby.
2. A boost regulated DC input for Main 300 VDC to 385 VDC -10
minimum nominal of 375 VDC. 0
3. HiperTFS total efficiency at least 85% at full load. EN55022B (QP)
-10
4. Schottky high-efficiency output diodes. EN55022B (AV)
5. DC input for Standby 130 VDC to 385 VDC. -20
6. Sufficient heat sinking and fan cooling to keep device 0.15 1 10 30
temperature below 100 °C. Frequency (MHz)
7. Transformer designed with nominal duty factor of 45%. Figure 13. Fixed Frequency Operation Without Jitter.
HiperTFS Selection 80
PI-5856-030810
Selecting the optimum HiperTFS depends upon the continuous 70
output power, thermal management, (heat sinking, etc.), and
60
maximum ambient operating temperature. OEM applications
are typically 50 °C max ambient while clone PC supplies are Amplitude (dBµV) 50
usually specified at 25 °C ambient. Higher efficiency can be 40
achieved with the larger devices. The maximum output power
30
can be tailored for any given device by programming primary
ILIMIT(MA). 20
-10
Hold-Up Time
The input capacitor is a critical component in designing for a 0
guaranteed minimum hold-up time. Proper design of the -10
EN55022B (QP)
EN55022B (AV)
transformer’s nominal duty cycle and sufficient primary winding
-20
clamp voltage for rest of Main transformer are also essential.
0.15 1 10 30
PIXLS (PI Expert Design Spreadsheet) can compute these
values or refer to formula in AN-51. Frequency (MHz)
Figure 14. Full Range EMI Scan (132 kHz with Jitter) With Identical Circuitry and Conditions.
Bias Support for High-Side Driver
Bias support for HiperTFS high-side switch is sourced from a
forward phased winding of the Main transformer and should 150 V
+VBUS
provide a minimum of 17 V at 300 VDC input (or minimum input
voltage at which regulation can be maintained) to guarantee the
12 V bias required for the high-side driver is maintained.
HiperTFS VDDH
Primary Bias Support
CONTROL HD
The standby converter provides a minimum 17 V output that
biases the BYPASS pin of HiperTFS. It is also the source for R
remote ON/OFF control and OVP. This output should be
capable of delivering a minimum of 20 mA. The primary bias HS
L DR1
filter capacitor should be at 330 mF to hold up the bias during
the start-up transient. D
FB
Start-Up
There is a duty factor soft-start function at start-up that slews EN
from 30% duty factor to max duty factor in approximately 15 ms.
DSB
The current limit during start-up is actually boosted by 115% for
BP
the first 32 ms to provide the ability to drive heavy capacitive
DR2
loads and meet less than 20 ms output rise time requirement. G S
RTN
PI-5846-111810
Figure 15. Typical Primary Winding Clamp-to-Rail.
14
TFS757-764HG
HiperTFS VDDH
CONTROL HD
HS
L
D
FB
~50 Newtons
EN
DSB
BP
Minimum Clearance
G S is 0.078 inches
To Bulk PI-5883-032410
Capacitor
PI-5882-111710
Figure 16. HiperTFS Layout Considerations. Figure 17. HiperTFS Heat Sink Mounting.
EMI an over-molded, electrically isolated section of the package

The frequency jitter feature modulates the switching frequency backside that provides isolation between the heat sink and the
over a narrow band as a means to reduce conducted EMI internal high-side switch. Thermal heat sink compound, and a
average and quasi-peaks associated with the harmonics of the mounting clip providing a minimum torque of 50 Newtons, are
fundamental switching frequency. This is particularly beneficial required for good thermal performance. The heat sink
for average conduction mode where the sampling bandwidth is temperature behind device should not exceed 95 °C to avoid
narrow. The modulation rate is nominally 250 Hz which is high activating the over-temperature shutdown of HiperTFS. Since
enough to reduce EMI but low enough to have negligible effect some of the HiperTFS pins are bent towards the heat sink, there
on output ripple (rejected by control loop). needs to be a minimum of 0.078 inches clearance between
heat sink and PC board.
Transformer Design
It is recommended that the transformer be designed for a Layout Considerations
maximum flux density of 3000 Gauss during continuous
maximum output power and a maximum peak transient flux Use a single point connection between, SOURCE pin, GROUND
density no greater than 4000 Gauss. The turns ratio should be pin and bypass capacitor. Typically the bypass capacitor is a
chosen for a nominal duty factor of 45% at 385 VDC input to surface mount type and is located directly under the HiperTFS
guarantee transformer reset with typical primary winding package between the GROUND pin and the BYPASS pin.
clamp-to-rail (Figure 15). For nominal duty factor of higher value
it is recommend to refer to AN-51 and use PIXLS spreadsheet The FEEDBACK pin and ENABLE pin along with the LINE-
for optimal transformer design. Typically the transformer should SENSE and RESET pins should be kept away from noisy, high
have foil secondary windings for outputs above 10 amps. The voltage switching areas. If it is unavoidable to have long traces
primary winding should be split primary type to keep leakage connecting to FEEDBACK pins then route these traces close to
inductance low. quiet, low impedance traces, that act as a Faraday shield. The
LINE-SENSE and RESET pins are associated with multiple
Standby Mode Consumption series resistor sections due to the high-voltage sensing. Make
The HiperTFS standby converter is essentially a TinySwitch-III sure the last resistor in series chain is SMD type and place it
controller which uses whole-cycle ON/OFF control. This has the very close to the pin. This will minimize the pick-up of noise.
benefit of operating at a low average frequency at lighter loads
which increases efficiency and reducers no-load consumption. The primary auxiliary bias output rectifier and filter should be
star referenced to bulk capacitor. Any Y capacitors referenced
Heat Sinking to DC primary should also be tied to quiet nodes of bulk
The HiperTFS package is eSIP-16/12. There is a metal exposed capacitor negative or positive terminal.
pad that provides a low thermal path to the heat sink for the
low-side power device and standby power device. There is also
15
TFS757-764HG
VIN
R1 VHIGH_BIAS
R1_MAX = VHIGH_BIAS –VDDH
1 mA
Minimum Supply Current to VHIGH_BIAS_(MIN) = VAUX_(MIN) = 14 V
VDDH = 1 mA
C1 C2
HiperTFS VDDH
CONTROL HD
Main Transformer
R
HS
CR1
L
D
FB
EN
DSB Standby Transformer

VAUX
BP
C3
G S
PI-5881-082610
Figure 18. High-Side Bias.
HiperTFS VDDH
VOUT
VOUT(OV) = (15 mA × R1) + V1 + 1 CONTROL HD
R1 HS
VBIAS L
IC1 D
(CTR = 1) FB
EN
V1
DSB
BP
IOVP ≥ 15 mA
G S
PI-5879-111710
Figure 19. Latching Output OVP.
16
TFS757-764HG
VBIAS VIN
VOUT(OV) = V1 + 1 V
R1 HiperTFS VDDH
VOUT
CONTROL HD
VAUX - VCE_OPTO
HS R1 ≤
IL(MA_OVOFF)
L
12 V - 0.3 V
D R1 ≤
146 µA
FB
EN
V1
DSB
BP
G S
PI-5878-111710
Figure 20. Non-Latching Output OVP.
Standby Out VBIAS
IREMOTE_MIN = 1 mA HiperTFS VDDH
CONTROL HD
REM
HS
ISTANDBY_MIN = 900 µA
L
R3
10 kΩ R2 D
Q1 FB
Remote ON VON
R4 EN
13 V
1 kΩ R1
6V DSB
BP
ION_MIN = 5 mA
G S
VON - 6.7 V VAUX(MIN) - 6 V

R1 = R2 = PI-5877-111710
5 mA 900 µA
Figure 21. Remote ON and Standby Bias.
17
TFS757-764HG
VIN
VBIAS
R2
100 kΩ 3.9 MΩ
HiperTFS VDDH
10 kΩ CONTROL HD
Q1
R
R1
90 kΩ
HS
L
D
VR1 FB
300 kΩ (+12 V)
EN
R1 + R2 = 4 MΩ
DSB
VIN(OV)
IL(OV) = BP
R1 + R2
VR1 - 1.9 V
R1 = G S
IL(OV)
PI-5876-111710
Figure 22. Input OVP (Latching).
VIN
VBIAS
R2
3.9 MΩ
100 kΩ HiperTFS VDDH
10 kΩ
CONTROL HD
R1 R
90 kΩ
HS
VR1 L
20 kΩ (+12 V)
D
FB
R1 + R2 = 4 MΩ EN
DSB
VIN(OV)
IL(OV) =
R1 + R2 BP
VR1 - 1.9 V
R1 = G S
IL(OV)
PI-5875-111710
Figure 23. Non-latching Input OVP.
18
TFS757-764HG
HiperTFS VDDH
CONTROL HD
VBIAS
HS
L
L 6.8 MΩ
D
FB
100 kΩ
AC
Input
EN
N 6.8 MΩ
DSB
1 MΩ Q2
BP
0.1 µF 1 MΩ Q1
G S
PI-5874-111710
Figure 24. Fast AC Reset of BP Latch.
R1 = R2 = 4 MΩ
150 V
R1 R2
HiperTFS VDDH
CONTROL HD
HS
L
D
FB
EN
DSB
BP
G S
PI-5873-020411
Figure 25. L and R Pin Reset and Duty Limit Circuit.
19
TFS757-764HG
L and R Pin Transformer Reset and

Forward Duty Clamp Protection
Duty Regulation (FB)

Factor duty cycle
Hard
limit
60%
Reset duty
clamp
To VIN
To Clamp
Available Reset Circuit
RL RR
duty cycle range
HiperTFS
R
L
This region for
transient response Forward duty
clamp
45%
75 µA 100 µA L Pin Current PI-5880-111710
(300 V) (385 V) (VIN with RL = 4 MΩ)
Figure 26. L and R Pin Duty Limit With RL = 4 MW and RR = 4 MW.
Applications Example The standby section is designed to operate whether the boost
PFC stage is on or off. The standby therefore is designed to
High Efficiency +12 V, 25 A Main Output and +5 V 2.5 A operate from 100 VDC to 385 VDC which covers the normal
Standby Power Supply universal input of 90 VAC to 265 VAC.
The circuit in Figure 26 is an example of a design using HiperTFS
providing a 300 W +12 V output forward derived Main converter The start-up sequence is initiated with HiperTFS charging the
and a 12 W +5 V Standby output from the flyback controller of BYPASS pin capacitor via internal high-voltage current source.
HiperTFS. The very high integration of two full converters within Current limit selection then follows via FEEDBACK pin and
a single package immediately shows the result of very low ENABLE pin resistors. The HiperTFS then senses the input
external parts count for the entire design. Both the main voltage via the LINE-SENSE pin resistor series chain R12, R13,
converter and the flyback section of HiperTFS are designed to R35. When the input voltage reaches 100 V VDC the LINE-
give very high-efficiency. The main converter takes advantage SENSE pin UV standby threshold is reached and the standby
of the ability to operate above 50% duty factor which lowers converter turns on. After several milliseconds the standby
RMS switch currents and allows using lower voltage more output will reach regulation and the primary VON +12 V bias will
efficient Schottky diodes on the output. The flyback section be stable. When the input bulk voltage reaches 315 VDC
uses Power Integrations TinySwitch technology which is often which is the UV threshold for the main converter, the main
used in designs that demand high-efficiency and low no-load converter will initiate a turn on sequence once the remote-on
input power consumption. command from secondary is activated. The remote-on switch
(SW1) on the secondary-side for this particular design allows
The design in Figure 27 is intended to work with a PFC boost the user to manually activate that main converter by turning on
front end that nominally provides a 385 VDC input. The main the remote-on optocoupler. In actual PC designs the remote-
converter will regulate to full load between 300 VDC and 385 on would be controlled by a computer start-up command. This
VDC. This voltage range guarantees greater than 20 ms hold-up optocoupler sources 5 mA into the BYPASS pin of the HiperTFS
time with C1 (270 mF). which is the threshold current to start the turn on sequence for
20
TFS757-764HG
the Main converter. The Main converter will first turn on the saturation of the transformer is completely avoided in all conditions
bottom switch to allow the high-side drive to receive the boot- including brownout and load transients. The LINE- SENSE pin
strap bias. After 14 ms the Main converter will start switching also has a UV low threshold which turns off the Main converter
both switches at 66 kHz and the main output voltage will rise. when the input voltage is below 215 V.
Once the regulator U5 becomes active, current will flow through
the optocoupler U1. The collector of U1 will sink current out of This design in particular is intended to operate with a minimum
the FEEDBACK pin to adjust for appropriate duty cycle to of 30 CFM airflow at full load.
maintain regulation. The normal operating sink current is
between 1 mA and 2 mA. There is a forward phased bias Both the main and standby output have overvoltage protection
winding off the main transformer that provides sustained bias from sense circuit around U4 which will source >15 mA during
for the high-side driver. During normal and brownout operation fault into bypass pin to cause latching shut-off of both converters.
the RESET pin senses the turn off clamp voltage via the resistor The standby uses auto-restart to protect the standby output
chain R6, R18, R19 and the internal controller determines the from overpower and over-current. The main output is current
maximum safe duty factor by comparing the RESET pin current limited by the selected internal primary current limit of the main
with the LINE-SENSE pin current. This features guarantees that switch path.
J3-1 VR1 VR2

380 VDC ZMM5242B-7 ZMM5230B-7
12 V 12 V 4.7 V 5V
F2
4A R1
PC817XI1JD0F
VR3 2.2 Ω
P6KE150A
D2
U4A
C2 C1
R12 3.3 nF 270 µF
R5 D3
1.33 MΩ 4.7 Ω 1N4007 R3 R4
100 Ω 150 Ω
R6 R7
100 Ω 4.7 Ω D4
1N4007
RTN
R8 R14 L1
R13 4.7 Ω 2 kΩ 3.3 µH
T
1 MAIN 13,14
+12 V
1.33 MΩ
U3B
PC817X1J00F R18 D5 D7
1.33 MΩ R15 R10 R11
BAV20 M6060C-E3/45 221 Ω
750 Ω R9 43.2 kΩ
U6 15 kΩ
R16 R17 U1A C4 C5
D13* 7.5 kΩ 820 Ω TFS762HG 13 VDDH 100 nF 47 nF
1N5404 R19 C6 C3 PC817XI1J00F
1.33 M 16 100 nF 100 nF R21
R20 R35 HD 2 kΩ C10 C11
1.33 MΩ
CONTROL D6
4.7 kΩ 7 M6060C-E3/45 3300 µF 3300 µF
Q1 R C8
MMBT4401 U4B R36 100 nF
R23 1.33 MΩ
1 kΩ PC817X1J00F 14 2
L U5
HS LM431
9 C9 R24
R22 R25 1 nF 3.92 kΩ
4.7 kΩ 232 kΩ 1 6 9,10
FB D
D10 R26 RTN
BAS16HT1G 10 47 Ω
C13
J4-1 100 nF L2
D8 TSTANDBY 2.2 µH
VR4 UF4005 2 9,10
MMSZ5243BT1G R29
13 V BP D11 +5 V
470 Ω
11 STPS1045B
R27 3 1 R28 C14
280 kΩ DSB 100 Ω 470 nF
EN
SW1
FB 8 Remote ON/OFF
C18 5 G 6 S R34
1 nF R30
U1B C21 C17 1 kΩ 4.75 kΩ
PC817XI1J00F D9 2.2 nF 2200 µF C15 R32
U2A
EN UF4005 PC817XI1J00F 2200 µF 4.7 kΩ
C19 C12
1 nF 1 µF
U2B R33
PC817XI1J00F 1 kΩ
D12
RGP100
14 - 25 V 3 U7
LM431 U3A
C16 R31 PC817XI1J00F
C20 330 nF
330 µF 4.75 kΩ
J3-3 5 6,7
PI-5969-102810 RTN
*Optional component for accidental reverse connection
Figure 27. Schematic of High-Efficiency +12 V, 25 A Main Output and +5 V, 2.5 A Standby Power Supply.
21
TFS757-764HG
– HV +
Y Capacitor
F1
C21
J3
L1
D8
D7
C13
+ C1
C3
R14
D5
R12
C6 D1
R25
R35 D9 Transformer
R1
C16 R13 C10+
R27
C12
VR3 R36
D6
R15
HF LC
C2
R7 R8
D4 Post-Filter
R11
R15
C4
C2
R9 C11+
R10
R6 D3 R18
R24
R21
C8 J1
C13 C9 –
TP1 T2 R26
12 V
D12
C17
+
VR2 VR1
C20
+
J2
5V
C14
R31
R34
J4 R29 –
C16 R28
C18
R30
R16
VR4 U7 R4
U2
D10
R33 L2
C15
R22 U3
R20
R23
R32 SW1 D2
R3
R17 U4
C7
PI-5872-042710
Figure 28. Layout of High-Efficiency +12 V, 25 A Main Output and +5 V, 2.5 A Standby Power Supply.
22
TFS757-764HG
Absolute Maximum Ratings(1,5)

DRAIN Voltage High-Side MOSFET .......................-0.3 V to 530 V Feedback (FB) Current ..................................................... 100 mA
DRAIN Peak Current High-Side: TFS757.................... 3.1 (5.9)4 A Line Sense (L) Pin Voltage ............................................-0.3 V to 9 V
TFS758....................4.5 (8.4)4 A Line Sense (L) Pin Current ....................................................100 ma
TFS759....................5.0 (9.3)4 A Reset (R) Pin Voltage ................................................. -0.3 V to 9 V
TFS760.................. 5.7 (10.7)4 A Reset (R) Pin Current .......................................................... 100 mA
TFS761...................6.1 (11.4)4 A Bypass Supply (BP) Pin Voltage ............................... -0.3 V to 9 V
TFS762...................6.4 (12.1)4 A Bypass Supply (BP) Pin Current ......................................... 100 mA
TFS763.................. 7.2 (13.4)4 A High Side (VDDH) Supply Pin Voltage ..................-0.3 V to 13.4 V
TFS764.................. 8.3 (15.5)4 A High Side (VDDH) Supply Pin Current ..................................50 mA
DRAIN Voltage Low-Side MOSFET..................... -0.3 V to 725 V Storage Temperature .............................................-65 °C to 150 °C
DRAIN Peak Current Low-Side: TFS757.................... 3.1 (5.9)4 A Operating Junction Temperature(2).......................-40 °C to 150 °C
TFS758....................4.5 (8.4)4 A Lead Temperature(3) ..................................................................260 °C
TFS759....................5.0 (9.3)4 A Notes:
TFS760.................. 5.7 (10.7)4 A 1. All voltages referenced to SOURCE, TJ = 25 °C.
TFS761...................6.1 (11.4)4 A 2. Normally limited by internal circuitry.
TFS762...................6.4 (12.1)4 A 3. 1/16 in. (1.59 mm) from case for 5 seconds.
TFS763.................. 7.2 (13.4)4 A 4. The higher peak DRAIN current is allowed while the DRAIN
TFS764................. 8.3 (15.5)4 A voltage is simultaneously less than 400 V.
DRAIN Voltage Standby MOSFET....................... -0.3 V to 725 V 5. Maximum ratings specified may be applied one at a time,
DRAIN Peak Current Standby MOSFET................. 1.20 (2.25)4 A without causing permanent damage to the product.
Enable (EN) Pin Voltage ............................................. -0.3 V to 9 V Exposure to Absolute Rating conditions for extended periods
Enable (EN) Pin Current ................................................... 100 mA of time may affect product reliability.
Feedback (FB) Pin Voltage ........................................ -0.3 V to 9 V
Thermal Resistance
High-Side MOSFET (qJC) TFS757, TFS758..................... 15 °C/W Low-Side MOSFET (qJC) .................................................1 °C/W
TFS759, TFS760..................... 14 °C/W Notes:
TFS761, TFS762..................... 13 °C/W 1. All voltages referenced to SOURCE, TA = 25 °C.
TFS763, TFS764..................... 12 °C/W

Conditions
Parameter Symbol SOURCE = 0 V; TJ = 0 °C to 100 °C Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
Switching Frequency Average 62 66 70
fS(MA) TJ = 25 °C kHz
- PC Main Peak-to-Peak Jitter 4
Frequency Jitter
fM(MA) 250 Hz
Modulation Rate
Remote-ON Main
BYPASS Pin
IBP(ON) VEN = Open 3.2 3.8 4.4 mA
Remote-ON Current
BYPASS Pin Remote-
IBP(OFF) 1.1 mA
OFF Current Hysteresis
BYPASS Pin Latching
IBP(SD) 13 15.5 17.5 mA
Shutdown Threshold
Main/Standby Remote-
tR(ON) 2.5 ms
ON Delay
tR(OFF) 2.5 ms
OFF Delay
tR(PERIOD) 80 ms
OFF Long Time Period
Soft-Start
High-Side Start-Up
tD(CH) 14 ms
Charge Time
Main Current Limit
ILIM(SS) See Note A 115 %
at Start-Up
Soft-Start Period 12 ms
23
TFS757-764HG
Conditions
FEEDBACK Pin
-1800 mA < IFB < -1500 mA, IL = 60 mA,
PWM Gain DCREG(MA) -70 %/mA
IR = 160 mA
PWM Gain
TCDCREG 0.05 %/°C
Temperature Drift
FEEDBACK Pin Feed-
IFB(ON) -1.1 mA
back Onset current IL = 60 mA, IR = 170 mA
FEEDBACK Pin Current TJ = 25 °C
IFB(OFF) -2.1 mA
at Zero Duty Cycle
FEEDBACK Pin
PFB 12 kHz
Internal Filter Pole
FEEDBACK Pin Voltage VFB IFB (OFF), IFB = IFB(ON) 3.56 V
LINE-SENSE Pin (Line Voltage)
Line Undervoltage IL(SB-UVON) TJ = 25 °C Threshold 25

mA
Threshold – Standby IL(SB-UVOFF) 10
Line Undervoltage IL(MA-UVON) Threshold 76 80 84

TJ = 25 °C mA
Threshold – Main IL(MA-UVOFF) Threshold 47 53 58
Line Overvoltage IL(MA-OVON) Threshold 119 135 146
Threshold – Main TJ = 25 °C mA
and Standby IL(MA-OVOFF) Threshold 135 146 164
LINE-SENSE Pin IL = 79 mA 2.4

VL V
Voltage IL = 149 mA 2.5
LINE-SENSE Pin
IL(SC) VL = VBP 375 mA
Short Circuit
RESET Pin (Duty Limit/Main Only Remote-OFF)
Reset Overvoltage IR(MA-OVON) Threshold 165 205 245

TJ = 25 °C mA
Threshold IR(MA-OVOFF) Threshold 175 215 255
RESET Pin Voltage VR IR = 155 mA 2.5 V

RESET Pin Short
IR(SC) VR = VBP 375 mA
Circuit Current
IL = 100 mA, IR = 110 mA 50.5
Duty Cycle – DCLIMIT(MA)
IL = 115 mA, IR = 140 mA 47.5 %
Programmable Limit
DCMAX(MA) IL = 100 mA, IR = 170 mA 63
Current Limit Programming
FEEDBACK Pin
Start-up
Current Limit ILIM(1)(MA) 0-5 mA
See Note C
Detection Range #1
FEEDBACK Pin
Start-up
See Note C
Detection Range #2
FEEDBACK Pin
Start-up
See Note C
Detection Range #3
24
TFS757-764HG
Conditions
Maximum Current Limit

ILIM(1)(MA) di/dt = 175 mA/ms 1.02
ILIM(2)(MA) TFS757
di/dt = 233 mA/ms 1.36
TJ = 25 °C
ILIM(3)(MA) di/dt = 291 mA/ms 1.58 1.70 1.82
ILIM(2)(MA) TFS758
di/dt = 335 mA/ms 1.95
TJ = 25 °C
ILIM(3)(MA) di/dt = 420 mA/ms 2.28 2.45 2.62
ILIM(2)(MA) TFS759
di/dt = 344 mA/ms 2.16
TJ = 25 °C
ILIM(3)(MA) di/dt = 430 mA/ms 2.55 2.70 2.94
ILIM(2)(MA) TFS760
di/dt = 432 mA/ms 2.48
TJ = 25 °C
ILIM(3)(MA) di/dt = 540 mA/ms 2.88 3.10 3.30
Current Limit ILIM(1)(MA) A
di/dt = 338 mA/ms 1.95
ILIM(2)(MA) TFS761
di/dt = 450 mA/ms 2.65
TJ = 25 °C
ILIM(3)(MA) di/dt = 564 mA/ms 3.07 3.30 3.53
ILIM(2)(MA) TFS762
di/dt = 480 mA/ms 2.80
TJ = 25 °C
ILIM(3)(MA) di/dt = 600 mA/ms 3.25 3.50 3.75
ILIM(2)(MA) TFS763
di/dt = 402 mA/ms 3.10
TJ = 25 °C
ILIM(3)(MA) di/dt = 670 mA/ms 3.60 3.90 4.16
ILIM(2)(MA) TFS764
di/dt = 624 mA/ms 3.60
TJ = 25 °C
ILIM(3)(MA) di/dt = 780 mA/ms 4.18 4.50 4.81
Low-Side Main MOSFET
TFS757 TJ = 25 °C 4.87 5.60
ID = ILIM(3)(MA) TJ = 100 °C 7.69 9.05
TFS758 TJ = 25 °C 3.25 3.73
ID = ILIM(3)(MA) TJ = 100 °C 4.90 5.83
TFS759 TJ = 25 °C 2.35 2.70
ID = ILIM(3)(MA) TJ = 100 °C 3.60 4.21
TFS760 TJ = 25 °C 1.96 2.24
ON-State ID = ILIM(3)(MA) TJ = 100 °C 2.80 3.29
RDS(ON) W
Resistance TFS761 TJ = 25 °C 1.60 1.85
ID = ILIM(3)(MA) TJ = 100 °C 2.30 2.75
TFS762 TJ = 25 °C 1.40 1.60
ID = ILIM(3)(MA) TJ = 100 °C 2.00 2.35
TFS763 TJ = 25 °C 1.20 1.40
ID = ILIM(3)(MA) TJ = 100 °C 1.70 2.05
TFS764 TJ = 25 °C 1.10 1.26
ID = ILIM(3)(MA) TJ = 100 °C 1.53 1.80
TFS757 150
TFS758 150
OFF-State Drain TFS759 VL, VR = 0 V, IBP = 6 mA, 150
IDSS(D) mA
Leakage Current TFS760 VDS = 560 V, TJ = 100 °C 150
TFS761 470
TFS762 470
25
TFS757-764HG
Conditions
Low-Side Main MOSFET (cont.)

OFF-State Drain TFS763 VL, VR = 0 V, IBP = 6 mA, 470
IDSS(D) mA
Leakage Current TFS764 VDS = 560 V, TJ = 100 °C 470
Breakdown VL, VR = 0 V, IBP = 6 mA,
BVDSS(D) 725 V
Voltage TJ = 25 °C
Rise Time tR(D) 100 ns
Fall Time tF(D) 50 ns
High-Side Main MOSFET
TFS757 TJ = 25 °C 1.76
ID = ILIM(3)(MA) TJ = 100 °C 2.12
TFS758 TJ = 25 °C 1.15
ID = ILIM(3)(MA) TJ = 100 °C 1.40
TFS759 TJ = 25 °C 0.88
ID = ILIM(3)(MA) TJ = 100 °C 1.06
TFS760 TJ = 25 °C 0.88
ID = ILIM(3)(MA) TJ = 100 °C 1.06
ON-State Resistance RDS(ON)(HD) W
TFS761 TJ = 25 °C 0.69
ID = ILIM(3)(MA) TJ = 100 °C 0.84
TFS762 TJ = 25 °C 0.58
ID = ILIM(3)(MA) TJ = 100 °C 0.7
TFS763 TJ = 25 °C 0.46
ID = ILIM(3)(MA) TJ = 100 °C 0.56
TFS764 TJ = 25 °C 0.46
ID = ILIM(3)(MA) TJ = 100 °C 0.56
TFS757 55
TFS758 82
TFS759 110
Effective Output TFS760 TJ = 25 °C, VGS = 0 V 110
COSS(EFF)(HD) pF
Capacitance TFS761 VDS = 0 V to 80% VDSS(HD) 140
TFS762 165
TFS763 205
TFS764 205
Breakdown Voltage BVDSS(HD) TJ = 25 °C 530 V
TFS757 60
TFS758 60
TFS759 60
OFF-State Drain TFS760 VD = 424 V, 60
IDSS(HD) mA
Current Leakage TFS761 TJ = 100 °C 65
TFS762 80
TFS763 110
TFS764 110
Turn-on Voltage
tR(HD) 30 ns
Rise Time
Turn-off Voltage
tF(HD) 25 ns
Fall Time
26
TFS757-764HG
Conditions
High-Side Main MOSFET (cont.)
High-Side Bias See Note B
VDDH(SHUNT) 11.4 12.1 12.8 V
Shunt Voltage IDDH = 2 mA
High-Side Undervoltage
VDDH(UVON) See Note B 10.7 11.1 11.5 V
ON-Threshold
High-Side Undervoltage
VDDH(UVOFF) See Note B 9.5 9.9 10.3 V
OFF-Threshold
High-Side Shunt
VDDH(HYST) See Note B 0.7 1.2 1.5 V
Hysteresis Voltage
Standby MOSFET
ON-State TJ = 25 °C 3.7 4.37
RDS(ON)(DS) IDSB = ILIM(3)(DSB) W
Resistance TJ = 100 °C 5.5 6.25
VBP = 6.2 V
IDSS1(DS) VEN = 0 V 200

OFF-State Drain VDS = 560 V
TJ = 100 °C mA
Leakage Current
VBP = 6.2 V VDS = 375 V,
IDSS2(DS) 15
VEN = 0 V TJ = 50 °C
VBP = 6.2 V, VEN = 0 V,
Breakdown Voltage BVDSS(DS) 725 V
TJ = 25 °C
DRAIN Supply Voltage VDSB(START) 50 V
Standby Controller
Output Frequency Average 124 132 140
fS(SB) TJ = 25 °C kHz
in Standard Mode Peak-to-peak Jitter 8
Maximum Duty Cycle DCMAX(DSB) IL = 40 mA 67 70 73 %
ENABLE Pin Upper

Turnoff Threshold IDIS -150 -115 -80 mA
Current
IEN = 25 mA 2.0 2.4 2.8
ENABLE Pin Voltage VEN V
IEN = -25 mA 0.8 1.2 1.6
VBP = 0 V,
ICH1 -5 -3.2 -2
TJ = 25 °C
BYPASS Pin
mA
Charge Current
VBP = 4 V,
ICH2 -4 -1.5 0
TJ = 25 °C
BYPASS Pin Voltage VBP VDS = 50 V 5.50 5.70 5.90 V

BYPASS Pin Voltage
VBP(HYST) 0.80 1.0 1.20 V
Hysteresis
BYPASS Pin Shunt
VBP(SHUNT) IBP = 2 mA 5.8 6.0 6.2 V
Voltage
Standby Circuit Protection
ENABLE Pin Current
ILIM(1)(DSB) Start-up 0-8.5 mA
Limit Selection Range #1
27
TFS757-764HG
Conditions
Standby Circuit Protection (cont.)
ENABLE Pin Current
ILIM(2)(DSB) Start-up 8.5-18 mA
ENABLE Pin Current

ILIM(3)(DSB) Start-up 18-33 mA
ENABLE Pin Current

ILIM(4)(DSB) Start-up 33-60 mA
ILIM(1)(DSB) IL = 20 mA, di/dt = 95 mA/ms, TJ = 25 °C 450 500 550

mA
Standby Current Limit
ILIM (IL = 100 mA) / ILIM (IL = 20 mA)

Δ ILIM 80 %
di/dt = 125 mA/ms
General Circuit Protection
I2f = ILIM(2)(DSB)(TYP)× fS(SB)(OSC)(TYP)
Power Coefficient I2f 0.9 × I2f I2f 1.12 × I2f A2Hz
TJ = 25 °C
0.75 ×
Initial Current Limit IINIT TJ = 25 °C
ILIM(MIN)
Leading Edge
tLEB(D) TJ = 25 °C 170 215 ns
Blanking Time (Main)
Leading Edge Blanking
tLEB(DSB) TJ = 25 °C 170 215 ns
Time (Standby)
Current Limit
tILD(D) TJ = 25 °C 150 ns
Delay (Main)
Current Limit
tILD(DSB) TJ = 25 °C 150 ns
Delay (Standby)
Thermal Shutdown
TSD 118 °C
Temperature
Thermal Shutdown
TSD(HYST) 55 °C
Hysteresis
Auto-Restart ON-Time
tAR TJ = 25 °C 64 ms
at fOSC Standby
Auto-Restart Duty
DCAR TJ = 25 °C 2.2 %
Cycle Standby
Supply Current
EN Current > IDIS
IS1 400 750 1000
(No MOSFETs Switching)
DRAIN Supply Current mA
EN Open (Standby MOSFET
IS2 600 950 1200
Switching at fOSC)
NOTES:
A. The current limit is boosted for the first 34 ms of main supply switching and returns to normal level after this period.
B. VDDH(SHUNT) minus VDDH(UV_ON) is equal to 250 mV minimum.
C. Level 1 RFB = open, Level 2 RFB = 511 kW, Level 3 RFB = 232 kW.
D. Level 1 REN = open, Level 2 REN = 280 kW, Level 3 REN = 137 kW, Level 4 REN = 63.4 kW.
28
TFS757-764HG
Typical Performance Characteristics
STANDBY DRAIN Pin Breakdown Voltage

1.1
MAIN DRAIN Pin Breakdown Voltage
1.1
PI-5998-060210
PI-5999-060210
(Normalized to 25 °C)
1.0 1.0
0.9 0.9
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 29. Main Supply. Breakdown Voltage vs. Temperature.
Figure 30. Standby Supply. Breakdown vs. Temperature.
STANDBY DRAIN Pin Output Frequency

1.2 1.2
MAIN DRAIN Pin Output Frequency
PI-6001-060210
PI-6000-060210
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125

Figure 31. Main Supply. Frequency vs. Temperature. Figure 32. Standby Supply. Frequency vs. Temperature.
1.2 1.2
PI-6002-060210
STANDBY DRAIN Pin Current Limit
PI-6003-060210
MAIN DRAIN Pin Current Limit
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Figure 33. Main Supply. Internal Current Limit vs. Temperature. Figure 34. Standby Supply. External Current Limit vs.
Temperature with RIL = 10.5 kW
29
TFS757-764HG
Typical Performance Characteristics (cont.)

STANDBY DRAIN Pin Undervoltage
1.2 5
PI-5959-060210
PI-5955-051210
Threshold (Normalized to 25 °C)
1.0
4
L Pin Voltage (V)

0.8
3
0.6
2
0.4
0.2 1
0
-50 -25 0 25 50 75 100 125 0
0 20 40 60 80 100 120 140 160
Junction Temperature (°C)
L Pin Current (μA)
Figure 35. Standby Supply. Undervoltage Threshold vs.
Junction Temperature. Figure 36. L Pin Voltage vs. L Pin Current.
5 1
PI-5953-051210
PI-5954-050510
4 FEEDBACK Pin Current (mA) 0

R Pin Voltage (V)
-1
3
-2
2
-3
1 -4
0 -5
0 50 100 150 200 250 0 1 2 3 4 5 6 7
R Pin Current (μA) FEEDBACK Pin Voltage (V)
Figure 37. R Pin Voltage vs. R Pin Current. Figure 38. FEEDBACK Pin Current vs. FEEDBACK Pin Voltage.
500 30
PI-5951-050510
PI-5952-051210
BYPASS Pin Current (mA)
400
ENABLE Pin Current (µA)
300
20
200
100
10
0
-100
-200 0
0 1 2 3 4 5 6 7 0.0 2.0 4.0 6.0 8.0
ENABLE Pin Voltage (V) BYPASS Pin Voltage (V)
Figure 39. ENABLE Pin Current vs. ENABLE Pin Voltage. Figure 40. BYPASS Pin Current vs. BYPASS Pin Voltage.
30
TFS757-764HG
30 100
PI-5949-052510
PI-5950-012711
VDDH Current (mA)
75
Duty Cycle (%)

20
50
10
25
0 0
0 4 8 12 16 -50 -25 0 25 50 75 100 125
VDDH Votage (V) Temperature (°C)
Figure 41. VDDH Current vs. VDDH Voltage. Figure 42. Duty Cycle vs. Temperature (TJ = 100 mA, JR = 110 mA).
100 2.5
PI-5942-060110
PI-5948-052510
DRAIN Current (A) 2

75
Duty Cycle (%)
1.5
50
1
TCASE = 25 °C
TCASE = 100 °C
25 .5
0 0
-50 -25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20
Temperature (°C) STANDBY DRAIN Voltage (V)
Figure 43. Duty Cycle vs. Temperature (IL = 115 mA, IR = 140 mA) Figure 44. Standby Supply. Output Characteristics.
5 1000
PI-5944-060110
PI-5943-091010
DRAIN Capacitance (pF)
4
DRAIN Current (A)
100
3
Scaling Factors:
TFS757 0.4
2 TFS758 0.6
TFS759 0.8
TFS760 1.0 10
TFS761 1.2
1 TFS762 1.4
TFS763 1.6
TCASE = 25 °C TFS764 1.8
TCASE = 100 °C
0 0
0 2 4 6 8 10 12 14 16 18 20 0 100 200 300 400 500 600
DRAIN Voltage (V) STANDBY DRAIN Pin Voltage (V)

Figure 45. Drain Supply. Output Characteristics. Figure 46. Standby Supply. Drain Capacitance vs. Drain Voltage.
31
TFS757-764HG
10000 250
PI-5945-091010
PI-5946-060110
Scaling Factors:
TFS757 0.4
TFS758 0.6
DRAIN Capacitance (pF)
TFS759 0.8 200

TFS760 1.0
132 kHz
1000 TFS761 1.2
Power (mW)
TFS762 1.4 150
TFS763 1.6
TFS764 1.8
100
100
100
10 0
0 100 200 300 400 500 600 0 100 200 300 400 500 600 700
DRAIN Pin Voltage (V) STANDBY DRAIN Pin Voltage (V)
Figure 47. Main Supply. Drain Capacitance vs. Drain Voltage. Figure 48. Standby Supply. Power vs. Drain Voltage.
500 20
PI-5947-091010
PI-5970-091010
Scaling Factors: TJ = 25 °C
TFS757 0.4 TJ = 100 °C 100 °C
400 TFS758 0.6 25 °C
TFS759 0.8 15
DRAIN Current (A)
TFS760 1.0
TFS761 1.2
Power (mW)
300 TFS762 1.4

TFS763 1.6
TFS764 1.8 10
200 Scaling Factors:
TFS757 0.17
TFS758 0.25
66 kHz 5 TFS759/760 0.33
100 TFS761 0.42
TFS762 0.50
TFS763/764 0.63
0 0
0 100 200 300 400 500 600 700 0 1 2 3 4 5 6 7
DRAIN Pin Voltage (V) DRAIN Voltage (V)
Figure 49. Main Supply. Power vs. Drain Voltage. Figure 50. High-Side MOSFET Drain Current vs. Drain Voltage.
1000 1.1
PI-5972-051210
PI-5971-083110
Breakdown Voltage
COSS (pF)
1.0
Scaling Factors:
TFS757 0.17
TFS758 0.25
TFS759/760 0.33
TFS761 0.42
TFS762 0.50
TFS763/764 0.63
100 0.9
0 100 200 300 400 -50 -25 0 25 50 75 100 125 150
Drain Voltage (VHD-VHS) Temperature (°C)
Figure 51. High-Side MOSFET Drain Current vs. Drain Voltage. Figure 52. High-Side MOSFET Breakdown Voltage vs. Temperature.
32
TFS757-764HG
PI-5973-083110
Scaling Factors:
TFS757 0.17
TFS758 0.25
1.5 TFS759/760 0.33
TFS761 0.42
Power (mW)
TFS762 0.50
TFS763/764 0.63
1
66 kHz
0.5
0
0 100 200 300 400
DRAIN Voltage (VD)
Figure 53. High-Side MOSFET Power vs. Drain Voltage.
33
34
eSIP-16B (H Package)
Rev. C 02/11
B B C
0.653 (16.59) 0.081 (2.06) 0.381 (9.68)

A
0.647 (16.43) 0.077 (1.96) Ref.
B
2
2 Detail A
0.325 (8.25) 0.290 (7.37) 0.201 (5.11)
Pin 1 I.D. 0.320 (8.13) Ref. Ref.
TFS757-764HG
0.519 (13.18)
Ref.
0.016 (0.41) 0.207 (5.26)

0.140 (3.56) Ref. 0.187 (4.75)
0.120 (3.05)
3
1 3 5 6 7 8 9 10 11 13 14 16 16 14 13 11 10 9 8 7 6 5 3 1
5 0.016 (0.41) 12×
5 0.011 (0.28) 3 4
0.024 (0.61) 12×
0.038 (0.97) 0.056 (1.42) Ref. 0.020 M 0.51 M C 0.019 (0.48)
0.076 (1.93)
0.010 M 0.25 M C A B
FRONT VIEW 0.118 (3.00) 0.118 (3.00) 0.012 (0.30) Ref.
0.019 (0.48) Ref. SIDE VIEW BACK VIEW

10° Ref. 0.114 0.152
0.060 (1.52) Ref. (2.91)
All Around (3.88)
0.021 (0.53)
0.019 (0.48) 14 11 9 7 5 1
5 0.020 (0.50)
0.048 (1.22)
0.046 (1.17) 0.164
0.628 (15.95) Ref. (4.18)
BOTTOM-END VIEW 0.023 (0.58) 16 13 10 8 3

0.114
0.020 (0.51) Ref.
0.235 (5.96) Ref. 0.027 (0.70) 0.076 0.076 (2.91) 0.076
7 8 0.114 0.114
(1.94) (1.94) (1.94)
0.041 (1.04) Ref. 0.167 (4.24) Ref. (2.91) (2.91)
9
0.010 (0.25) Typ. 10 0.101 (2.57) Ref.
Detail A (N.T.S)
MOUNTING HOLE PATTERN (N.T.S)
0.012 (0.30) Typ. Notes: All dimensions in inches (mm)
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremesof the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and inter-
lead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 (0.18) per side.
3. Dimensions noted are inclusive of plating thickness.
11 4. Does not include inter-lead flash or protrusions.
0.035 (0.89) Ref.
5. Pin #6 is the only straight (unformed) lead.
Pin 1
6. Controlling dimensions in inches (mm).
TOP-END VIEW B-B 7 8. Tied to SOURCE (pin 6).
Location of Exposed Metal Tie-Bars 9. Tied to HS (pin 14).
www.powerint.com
10 11. Tied to HD (pin 16). PI-5300-021411
TFS757-764HG
Part Ordering Information

Part Number Option Quantity
PFS757HG Tube 30
PFS758HG Tube 30
PFS759HG Tube 30
PFS760HG Tube 30
PFS761HG Tube 30
PFS762HG Tube 30
PFS763HG Tube 30
PFS764HG Tube 30
Part Marking Information

• HiperTFS Product Family
• TFS Series Number
• Package Identifier
H Plastic eSIP-16B
• Pin Finish
G Halogen Free and RoHS Compliant
TFS 757 H G
35
Revision Notes Date
B Initial Release. 11/09/10
C Updated Absolute Maximum Ratings section. Updated TFS759 ILIMIT, Figures 3, 25, 41, and Package drawing. 02/11
For the latest updates, visit our website: www.powerint.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY
RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or Power Integrationslly by pending U.S. and foreign patent applications assigned to Power
Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a
license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy

POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, Qspeed,
EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks
are property of their respective companies. ©2011, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters Germany Japan Taiwan

5245 Hellyer Avenue Rueckertstrasse 3 Kosei Dai-3 Bldg. 5F, No. 318, Nei Hu Rd., Sec. 1
San Jose, CA 95138, USA. D-80336, Munich 2-12-11, Shin-Yokomana, Nei Hu Dist.
Main: +1-408-414-9200 Germany Kohoku-ku Taipei, Taiwan 114, R.O.C.
Customer Service: Phone: +49-89-5527-3910 Yokohama-shi Kanagwan Phone: +886-2-2659-4570
Phone: +1-408-414-9665 Fax: +49-89-5527-3920 222-0033 Japan Fax: +886-2-2659-4550
Fax: +1-408-414-9765 e-mail: [email protected] Phone: +81-45-471-1021 e-mail: [email protected]
e-mail: [email protected] Fax: +81-45-471-3717
India e-mail: [email protected] Europe HQ
China (Shanghai) #1, 14th Main Road 1st Floor, St. James’s House
Rm 1601/1610, Tower 1, Vasanthanagar Korea East Street, Farnham
Kerry Everbright City Bangalore-560052 India RM 602, 6FL Surrey GU9 7TJ
No. 218 Tianmu Road West, Phone: +91-80-4113-8020 Korea City Air Terminal B/D, 159-6 United Kingdom
Shanghai, P.R.C. 200070 Fax: +91-80-4113-8023 Samsung-Dong, Kangnam-Gu, Phone: +44 (0) 1252-730-141
Phone: +86-21-6354-6323 e-mail: [email protected] Seoul, 135-728, Korea Fax: +44 (0) 1252-727-689
Fax: +86-21-6354-6325 Phone: +82-2-2016-6610 e-mail: [email protected]
e-mail: [email protected] Italy Fax: +82-2-2016-6630
Via De Amicis 2 e-mail: [email protected] Applications Hotline
China (Shenzhen) 20091 Bresso MI World Wide +1-408-414-9660
Rm A, B & C 4th Floor, Block C, Italy Singapore
Electronics Science and Phone: +39-028-928-6000 51 Newton Road Applications Fax
Technology Bldg., 2070 Fax: +39-028-928-6009 #15-08/10 Goldhill Plaza World Wide +1-408-414-9760
Shennan Zhong Rd, e-mail: [email protected] Singapore, 308900
Shenzhen, Guangdong, Phone: +65-6358-2160
China, 518031 Fax: +65-6358-2015
Phone: +86-755-8379-3243 e-mail: [email protected]
Fax: +86-755-8379-5828
e-mail: [email protected]

Tfs757-764Hg Hipertfs Family

Uploaded by

Copyright:

Available Formats

Tfs757-764Hg Hipertfs Family

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tfs757-764Hg Hipertfs Family

Uploaded by

Copyright:

Available Formats

TFS757-764HG

Combined Two-Switch Forward and Flyback Power Supply Controllers

Key Benefits Applications

Figure 1. Simplified Schematic of Two-Switch Forward and Flyback Converter.

www.powerint.com February 2011

Description • Programmable line overvoltage (OV) detection; latching and

Protected Two-Switch Forward and • Provides thermal impedance equivalent to a TO-220

standby controllers, and gate drivers and high-voltage creepage requirements

Switch Current (RMS) 100% 83%

Pin Functional Description BYPASS (BP) Pin

LINE-SENSE (L) Pin

standby current limit so as to flatten the output overload

response as a function of input voltage.

FEEDBACK (FB) Pin

Figure 2. Pin Configuration.

BYPASS (BP) HSD1 HSD2

LINE-SENSE (L) CONTROLLED

LV D2MAX CLK2 SAW PWM THERMAL SD SOURCE (S)

Figure 3. Functional Block Diagram for Two-Switch Forward Converter.

Figure 4. Functional Block Diagram for Flyback/Standby Converter.

• The HiperTFS two-switch forward includes a controller along 4 ms

The low-side MOSFET has a very low COSS capacitance and

The HiperTFS also contains a high-side driver to control the t

Duty Cycle Limit IL = 90 µA

TSELECT - current limit selection occurs here during

Figure 9. Current Limit Selection.

Standby Power General Introduction

240 V R (Threshold) (1%)

17.7-33.0 mA L3 750 mA 137.0 KW

tHOLDUP Table 4. ENABLE Pin Standby Current Limit Selection.

safety feature to protect against abnormal or fault conditions.

2. Second a 15 mA threshold (IBP(SD))for standby secondary OVP Output Power Table

Continuous1 Continuous1 Peak

High-Power eSIP Package

Design, Assemble and Layout Considerations 80

Figure 15. Typical Primary Winding Clamp-to-Rail.

EMI an over-molded, electrically isolated section of the package

DSB Standby Transformer

Figure 18. High-Side Bias.

Figure 19. Latching Output OVP.

Figure 20. Non-Latching Output OVP.

Standby Out VBIAS

IREMOTE_MIN = 1 mA HiperTFS VDDH

VON - 6.7 V VAUX(MIN) - 6 V

Figure 21. Remote ON and Standby Bias.

Figure 22. Input OVP (Latching).

Figure 23. Non-latching Input OVP.

Figure 24. Fast AC Reset of BP Latch.

Figure 25. L and R Pin Reset and Duty Limit Circuit.

L and R Pin Transformer Reset and

Duty Regulation (FB)

(300 V) (385 V) (VIN with RL = 4 MΩ)

Figure 26. L and R Pin Duty Limit With RL = 4 MW and RR = 4 MW.

J3-1 VR1 VR2

Absolute Maximum Ratings(1,5)

Line Undervoltage IL(SB-UVON) TJ = 25 °C Threshold 25

Line Undervoltage IL(MA-UVON) Threshold 76 80 84

LINE-SENSE Pin IL = 79 mA 2.4

Reset Overvoltage IR(MA-OVON) Threshold 165 205 245