An open-source high-frequency lock-in

amplifier
Cite as: Rev. Sci. Instrum. 90, 094701 (2019); https://doi.org/10.1063/1.5083797
Submitted: 30 November 2018 . Accepted: 19 August 2019 . Published Online: 10 September 2019

G. A. Stimpson , M. S. Skilbeck, R. L. Patel, B. L. Green , and G. W. Morley

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Rev. Sci. Instrum. 90, 094701 (2019); https://doi.org/10.1063/1.5083797 90, 094701

© 2019 Author(s).
 Review of ARTICLE scitation.org/journal/rsi
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An open-source high-frequency lock-in amplifier

Cite as: Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797
Submitted: 30 November 2018 • Accepted: 19 August 2019 •
Published Online: 10 September 2019

G. A. Stimpson,1,2,a) M. S. Skilbeck,1 R. L. Patel,1,2 B. L. Green,1 and G. W. Morley1,2,b)

AFFILIATIONS
1
Department of Physics, University of Warwick, Coventry CV4 7AL, United Kingdom
2
Diamond Science and Technology Centre for Doctoral Training, University of Warwick, Gibbet Hill Road, Coventry CV4 7AL,
United Kingdom

a)
Email: [email protected]
b)
Email: [email protected]

ABSTRACT
We present characterization
√ of a lock-in amplifier based on a field programmable gate array capable of demodulation at up to 50 MHz. The
system exhibits 90 nV/ Hz of input noise at an optimum demodulation frequency of 500 kHz. The passband has a full-width half-maximum
of 2.6 kHz for modulation frequencies above 100 kHz. Our code is open source and operates on a commercially available platform.
© 2019 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license
(http://creativecommons.org/licenses/by/4.0/). https://doi.org/10.1063/1.5083797., s

I. INTRODUCTION be attenuated due to orthogonality of the sine and cosine functions

of equal frequency,21 and hence, the LIA is considered phase sensi-
The lock-in amplifier (LIA) is an invaluable tool in scientific tive.22 Components in phase with the sine function will result in a
instrumentation1 allowing the extraction of weak signals from noisy nonzero value in the X output, while those in phase with the cosine
backgrounds, even where the amplitude of the noise is much greater function will produce √a nonzero value in the Y output. X and Y can
than the signal.2 First described in 1941, early LIAs were based on be combined by R = X 2 + Y 2 to provide a magnitude value,23 while
heaters, thermocouples, and transformers.3 More modern LIAs have phase ϕ = arctan YX .
been fully digital4–7 or implemented on field programmable gate FPGAs offer easily implementable microcircuitry design via the
array (FPGA) devices,8–14 which are able to exceed the performance use of hardware description language (HDL) such as Verilog or
of their analog counterparts.15 However, the cost of modern LIAs VHDL. A broad range of applications can be realized using these
may prove prohibitive, particularly in cases where large numbers of devices,24 including LIAs without recourse to detailed knowledge of
input channels are required. By employing Red Pitaya hardware, we microelectronics.25
are able to define an open-source LIA solution that is comparable The Red Pitaya STEMlab 125-14 is a single board computer
with considerably more costly approaches. (SBC) with an integrated FPGA in the form of a Xilinx Zynq
Characterized by a wide dynamic range and the ability to 7010 SoC,26 allowing for the implementation of reprogrammable
extract signal from noisy environments,16 LIAs are phase sensitive microarchitecture that would otherwise necessitate dedicated hard-
detectors17 due to their operating principles. A reference signal in ware. The reprogrammability27 of this FPGA makes it applicable
the form of a sinusoidal wave is generated either internally by the for the LIA functionality described here and allows for further
LIA itself, along with a cosinusoidal wave, or externally by some expansion and modification by end users. Two DC coupled analog
other sources that can also be manipulated to form a cosinusoidal inputs are available in the form of user selectable ±1 V or ±20 V,
reference. This reference is multiplied by the input signal18 that car- 125 MS/s analog-to-digital converters (ADCs—Linear Technolo-
ries the desired data modulated at the reference frequency.19 A low gies LTC2145CUP-1428 ) with an input impedance/capacitance of
pass filter is then used before outputting the signal. In this way, the 1 MΩ/10 pF.
LIA amplifies and outputs the component of the input signal that In this article, we detail an LIA which we have implemented
is at the reference frequency, attenuating noise at other frequen- on the STEMlab’s FPGA chip, along with open source29 operational
cies.20 Components out of phase with the sine reference will also and data transfer software developed specifically for this application.

Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797 90, 094701-1
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Scientific Instruments

We demonstrate that this device shares many capabilities with more in Fig. 1. Signals received by the ADCs are passed to the processing
expensive alternatives such as a sweepable internal signal genera- blocks where they are multiplied by the reference signal [which is
tor, single or dual input/output modes, wave form control, and the generated internally by direct digital synthesis (DDS)] and filtered
ability to increase the number of available inputs and outputs by using a single pole infinite impulse response (IIR) filter. The result-
interfacing across multiple STEMlab units. ing output is written to the SBC’s random access memory (RAM)
Comparison is made with the Zurich Instruments HF2LI LIA, via the FPGA’s memory interface block. This data is then written to
which is specified for operation up to 50 MHz demodulation fre- a ramdisk file also contained within the STEMlab’s RAM, alleviat-
quency.30 While an extensive software application is provided with ing high read/write workloads which were observed to cause critical
the HF2LI, the open source nature and readily available software and failures of the SD card. The data are also passed to the on-board
hardware of the LIA presented here allow for an attractive option digital-to-analog converters (DACs) along with the reference signal
where cost is a consideration. Research into low-cost FPGA based that is used to modulate the desired signal. This reference can be
LIAs has produced a number of alternatives,25 including high res- extracted via the DAC output for external use.
olution designs operating at up to 6 MHz demodulation,31,32 and Data retrieval from the STEMlab to a host computer can be
simulations have been presented for a high frequency LIA based on achieved via the DACs that are provided with SubMiniature version
the Red Pitaya STEMlab.33 Typically, FPGA LIAs have been devel- A (SMA) connections for output to an oscilloscope. These DACs
oped with specific experimental objectives.13,14,34 The STEMlab is have 14-bit resolution combined with 125 MS/s data rate. Non-
the basis for a range of related measurement instrumentation from offset, digital amplification of up to 2000 times the raw output is
PyRPL, including an LIA.35–37 A low cost FPGA-based LIA has also available. However, noise introduced by the DACs makes the out-
been developed which operates at a low demodulation frequency,38 put undesirable in cases where small changes in signal intensity are
and FPGA-based LIAs have been compared with analog devices in to be detected. Alternatively, data may be transferred to a host per-
terms of signal accuracy.39 However, we believe that this article is sonal computer (PC) via file transfer from the STEMlab’s RAM. This
the first to characterize a high frequency, open source LIA. The open produces low noise data but can only be performed on the entirety
source code may lead to a range of future uses in research, education, of the LIA’s allocated storage space of approximately 65 megabytes
and industry. (MB). While this process may last for tens of seconds, all data
(X, Y, R, and ϕ) for both output channels are received simultane-
II. METHODS ously. Further limitations include the inability to operate using an
external lock-in reference, cross talk that can occur between the two
A. Hardware and software input channels and no facility for subtraction of channels (e.g., A-B).
The FPGA system design and implementation was performed Due to the programmable nature of the STEMlab, end users are able
using software provided by the manufacturer of the FPGA, Xilinx. A to implement their own data transfer methods, which may be shown
simplified version of the design circuitry block diagram can be seen to alleviate some or all of these limitations.

FIG. 1. Simplified schematic of the circuitry layout on the Red Pitaya lock-in amplifier FPGA. Signals (solid green arrows) are received at channel processing, where they
are multiplied by a reference signal generated in the direct digital synthesis (DDS) block, which takes time data (dashed brown arrows) from the timer and distributes it as a
reference. After multiplication, data are passed through a single pole infinite impulse response (IIR) filter, currently limited to single order. Filtered data (solid blue arrows) are
then passed to the memory allocation block and subsequently to the digital to analog converters (DACs) and are converted to analog data (solid red arrows) and passed out
to the user or saved to the SBC RAM where they can be accessed via Ethernet (dashed red arrow). The reference signal is extracted from the DACs in analog form (dashed
blue arrow). Operating parameters and modes are set by the user (dashed green arrows) via the command line interface (CLI) that communicates with the mode control
block on the FPGA.

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While the FPGA is responsible for signal processing and data

transfer, parameter setting takes place on the STEMlab’s Linux SBC.
This device is packaged along with the FPGA on the STEMlab board,
allowing the user to operate the Red Pitaya LIA (RePLIA) or any
other custom FPGA application entirely using the STEMlab itself.
Parameter setting and system control are performed using C and
Python codes written specifically for use with the LIA. These codes
may be accessed via secure shell (SSH) or a terminal emulator but, in
practice, are accessed via a Java-based graphical user interface (GUI)
on a client computer that allows the user to largely ignore the STEM-
lab’s Linux element. This open-source GUI allows for the setting of
all available RePLIA parameters.

B. Characterization methodology
Data were extracted from both LIAs via Ethernet connection.
In the case of the RePLIA aboard the STEMlab, this avoided noise
from its DACs which were found to increase noise by up to three
orders of magnitude.
Noise for both LIAs during operation was measured at various
demodulation frequencies with no input signal present and with a
constant amplitude signal produced with an Agilent N5172B EXG
vector signal generator. Similarly, noise was measured while varying
the time constant of the LIAs with the demodulation frequency fixed
at the value determined to be the least noisy by the previous method.
As with the input noise, these data are presented after a fast Fourier
transform (FFT).
Passbands for each LIA at various demodulation frequencies
were obtained by applying a constant amplitude signal at the spec-
ified demodulation frequency. This signal was then combined with
a sweep between the minimum and maximum frequencies passing
through the demodulation frequency, with a sweep time of 10 s.

1. Zurich instruments HF2LI

The HF2LI provides a built in input noise measurement pro-
tocol. The experimental conditions detailed in the HF2LI user notes
were replicated,30 and the input noise was measured. Noise was col-
lected while the inputs were terminated for periods of 1, 10, and
100 s. This noise was then subjected to a FFT, and the noise level
was assessed and compared
√ with the manufacturer’s stated input
noise level of 5 nV/ Hz at 1 MHz demodulation for the output
frequencies greater than 10 kHz.40 FIG. 2. Noise spectral density from (a) RePLIA at 500 kHz demodulation with a
1 ms time constant (with 1 s data zero padded) and (b) HF2LI at 1 MHz demodula-
2. Red Pitaya lock-in amplifier tion and 700 μs time constant at 1 s, 10 s, and 100 s collection times (output data
are R for both channels).
√ (c) Noise level decays with an increased collection time
Optimal operational parameters were deduced by examining close to the predicted t relationship (top trace) calculated based on the noise
the output of the RePLIA at varying demodulation frequencies and measured after 1 s of collection. The lower trace indicates theoretical values back
time constants. The optima chosen were those which resulted in calculated from the 100 s data point.
the lowest output noise level. This behavior was examined both
with an applied signal and with the terminated inputs. The RePLIA
maintains capability over a wide range of demodulation frequen- √
cies (10 kHz–50 MHz), which were also characterized, but figures expected to produce a t decrease in noise. Both LIAs remained
are quoted with respect to optimal parameters unless otherwise within close agreement of this prediction after a 100 s collection time
stated. [Fig. 2(c)]. Noise levels were obtained by taking an average of base-
lined data from each LIA at the relevant collection time. In Fig. 2(a),
the data for 1 s of collection time has been zero padded, by adding
III. RESULTS 4 s worth of zeros, to reduce the width of the frequency bins. These
Figure 2 shows input noise spectral density for both LIAs at 1 s, averages produce figures of 89, 21, and 6 nV for the RePLIA for the
10 s, and 100 s collection periods. Increasing collection time t was collection times of 1, 10, and 100 s, respectively, corresponding to the

Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797 90, 094701-3
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from those appropriate to the RePLIA. It should be noted that the

manufacturer specified sampling rate for the HF2LI limits the span
of the FFT output to 120 Hz. Frequencies beyond this limit can
be found in the HF2LI’s user manual in section 8.4 on page 665.30
A wider output frequency plot for the RePLIA can be found in
Appendixes A and B (Fig. 13).
The noise spectrum for the HF2LI [Fig. 2(b)] shows greater
noise below 80 Hz and lower noise at higher output frequencies.
By contrast, the RePLIA shows a higher level of noise that is largely
steady up to 120 Hz [Fig. 2(a)] output frequency.
Figure 3 shows FFTs of the RePLIA output collected for 100 s at
a range of demodulation frequencies, with time constants optimized
for the relevant demodulation period (see Appendixes A and B).
There is a marked difference in noise at demodulation frequencies
below 100 kHz, although above this threshold the noise is roughly
FIG. 3. FFTs of terminated input data, extracted via file transfer, at various RePLIA constant.
demodulation frequencies with 100 s collection time. Two distinct noise regimes Output from the RePLIA digital-to-analog converters (DACs)
seem to exist, with demodulation frequencies above 100 kHz producing signifi- was also produced (see Appendixes A and B), showing a con-
cantly lower noise. Time constants were varied depending on the demodulation stant noise level at frequencies below 100 kHz. Although this noise
frequency (see Appendixes A and B). Note that low frequency and high intensity level is several orders of magnitude greater than that incurred
data have been cropped for visual clarity.
in data extracted via the Ethernet connection, this may be an
acceptable trade-off in certain cases. This consistency suggests that
noise inherent to the DACs is the limiting factor when obtain-
√ ing data using this method, although this noise can be reduced
sensitivities of 89, 66, and 60 nV/ Hz. When the RePLIA was oper- as described in Ref. 28. Signal-to-noise as measured at the DACs
ated using the conditions stipulated for measurement of√
the HF2LI increases with an increase in the DAC multipliers, plateauing toward
input noise, the noise levels are 131, 133, and 130 nV/ Hz. This saturation of the RePLIA’s outputs (see Fig. 7 in Appendixes A
shows that the optimal operating parameters for the HF2LI differ and B).

FIG. 4. Output of the frequency sweep for MHz demod-

ulation frequencies for the (a) RePLIA and (b) HF2LI. (c)
Maximum output voltage of the RePLIA plotted against the
demodulation frequency, showing the half power point. Note
that the RePLIA has a sampling rate of 125 MHz.

Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797 90, 094701-4
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ACKNOWLEDGMENTS
We thank Ben Breeze and Matt Dale for assistance and advice.
This research was funded by Bruker Biospin and the Engineer-
ing and Physical Sciences Research Council (EPSRC) via Grant
No. EP/L015315/1, and G. W. Morley was supported by the Royal
Society.

APPENDIX A: OPERATIONAL NOTES

The RePLIA was operated in a dual channel input mode with
the output producing amplitude data. These data were collected at
a rate of 20 ksamples/s. It is important to note that in setting a
sample rate, the actual rate per sample will be 1/8 of that set, as
the set rate includes one sample per output channel per time incre-
ment (2 input channels comprising R, X, Y, and ϕ for each input
channel). This sample rate is dependent on both the system being
measured and the hardware over which data are transmitted but
can be set by the user to any rate within the sample rate range of
FIG. 5. Demodulated RePLIA output against the input voltage, operating at 500
kHz demodulation for a ±1 V input range. Solid red line is a linear fit of the
0–0.7 V linear region.
TABLE I. Experimental parameters used for the measurement of HF2LI input noise,
as detailed in manufacturer’s instructions.

HF2LI input noise settings

Figures 4(a) and 4(b) show the shape of LIA passbands when
modulating at varying frequencies with time constants optimized Setting Parameter Value
for each frequency. The HF2LI demonstrates a narrower pass-
band with less transmission at unwanted frequencies. These pass- Range 10 mV
bands are shown to be approximately Lorentzian in line shape with AC On
Signal input
a full-width half-maxima of 2.6 kHz for demodulation frequen- Diff Off
cies above 100 kHz (see Appendixes A and B), and they begin to 50 Ω On
reduce in intensity above 30 MHz demodulation with the HF2LI, Demodulator low-pass filter Bandwidth 3 dB 100 Hz
whereas the output is consistent up to 50 MHz demodulation with Order 4
the RePLIA. Figure 5(c) shows the normalized output at mega-
hertz demodulation frequencies for both LIAs. The half power Oscillator Frequency 1 MHz
point is indicated ( V√max2 , where V max is the peak voltage output), Signal output Switch Off
which for the RePLIA is encountered at a demodulation frequency
of around 60 MHz, which is close to half of the device’s 125
MHz sample rate, as can be expected from the Nyquist sampling
theorem.41 TABLE II. Time constants τ for RePLIA at various demodulation frequencies. The
Linearity of the output relative to the input is demon- central column contains the minimum usable time constant and the right-hand column
strated in Fig. 5. Input voltages were varied, and the resul- details the actual time constants used which were determined by ensuring a near-
tant DAC output voltage were measured for both the ±1 V Lorentzian passband at the relevant demodulation frequency. Note that this table is
and ±20 V input ranges. Linearity is observed over ±700 mV not exhaustive and longer/shorter time constants may be used.
and ±1100 mV, respectively. Outside these regions, the STEM-
lab’s input, having only 14 bits, introduces significant nonlinear- Time constants (τ)
ities, as does the improper impedance matching of the RePLIA’s
inputs. F mod (MHz) τ min (ms) τ (ms)

0.001 10 100
0.01 1 100
IV. CONCLUSIONS 0.1 0.1 10
The RePLIA performs lock-in amplification 0.5 2 × 10− 2 1
√ at frequencies up
to 50 MHz, with an input noise level of 90 nV/ Hz. The respective 1 1 × 10− 2 1
figures from√the Zurich Instruments HF2LI (50 MHz demodulation 10 1 × 10− 3 1
with 5 nV/ Hz input noise) show that the FPGA LIA detailed in 100 1 × 10− 4 0.1
this article is an open source alternative.

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the STEMlab, although this sample rate may ultimately affect the
accuracy of resultant signals. When obtaining data via the DAC out-
puts, collection has been performed by a Pico Technology Picoscope
4424 digital oscilloscope. The Picoscope and DAC outputs were also
used when determining the time constants for the RePLIA. Data
extracted via the RePLIA’s Ethernet port were converted to milli-
volt values by dividing the actual numerical value by 2.1 × 106 , a
conversion factor that was determined by comparing the Ethernet
values with the corresponding values produced at the DACs with no
DAC multiplication applied.
The Zurich Instruments HF2LI was operated according to the
instructions laid out in section 3.5 of the HF2 User Manual,30 using
the parameters in Table I.

FIG. 6. (a) FFT of 10 kHz demodulation data taken from the RePLIA’s DAC outputs, FIG. 7. FFTs of RePLIA input noise at varying DAC multiplier settings (a) with
demonstrating significantly greater noise than the data taken from the Ethernet extremes only plotted for clarity (b). (c) The signal to noise ratio at the RePLIA’s
output. (b) Output signal to noise ratio from the DAC outputs improves dramati- digital-to-analog outputs increases with a larger DAC multiplier. However, even
cally with demodulation frequency throughout lower frequency ranges due to the small signals can lead to saturation of these outputs. Data are obtained at 500 kHz
increased signal. demodulation frequency and a 10 ms time constant.

Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797 90, 094701-6
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The time constants detailed in Table II were used for measure-

ments made with the RePLIA. For frequencies in between those
listed, the time constant corresponding to the lower frequency
was used. Minimum time constants τ min have been determined by
τ min = 10/f mod , where f mod is the demodulation frequency. This
ensures that for a given time constant, 10 modulation periods or
more elapse during the time constant. The actual time constants
used were chosen based on the line shape of passbands as seen in
Fig. 5(a) in the main text. Time constants were made as large as
possible without distortion of the Lorentzian line shape of these
passbands.
Figure 6(a) shows an FFT of the terminated input data at 10
kHz. These data were extracted from the digital-to-analog convert-
ers (DACs), with the noise level indicating that the DACs themselves
are the most significant source of noise. Contrasting this with Fig. 3,
where we see that without DAC noise, the varying demodulation fre-
quency causes a distinct change to noise levels. Figure 7(b) demon-
strates an increase in the output signal to noise ratio with increasing
demodulation frequency.
Figure 7(a) shows the effect on an FFT while varying the
DAC amplification multiplier, with the extremes in this range
shown in Fig. 7(b). There is no significant difference in noise level
between these extremes. Although Fig. 7(c) shows that an increase
in the DAC multiplier does improve the signal-to-noise ratio, care
should be taken not to saturate the STEMlab’s 1 V maximum
output.
Figure 8 demonstrates the effect of the time constant on the
shape of the passband for a given demodulation frequency, with
500 kHz used as an example. Excessively long time constants
produce a narrower passband at the expense of line shape; fringes

FIG. 8. The effect of the time constant setting on the resulting passband. An 80
kHz sweep over 10 s through the demodulation frequency of 500 kHz at varying
time constants results in distortion of the passband. Longer time constants result
in fringes in the unwanted frequency regions, and shorter time constants result in
excessive acceptance of unwanted frequencies. For 500 kHz, a time constant of
1 ms was chosen as a suitable compromise. The small section of the sweep FIG. 9. Low frequency (1–10 kHz) FFTs of RePLIA input noise from (a) 1 s, (b)
output shown above shows only the part of the passband affected by the time 10 s, and (c) 100 s of DAC data. Frequency-specific spikes are common at a low
constant. demodulation frequency.

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appear at output frequencies close to but greater than the demod-

ulation frequency, leading to the distortion of output signals.
Shorter time constants produce a more consistent line shape at
the cost of passband linewidth. Further to this, extremely short
time constants (below those detailed in Table II) are unable to
detect changes on time scales appropriate to the demodulation
frequency. In terms of software, the time constant can be set
to any value above 9 × 10−6 s. However, appropriate setting of
the time constant is necessary to ensure the correct represen-
tation of output signals, and an understanding of the physical
nature of systems being measured is also necessary for accurate
results.
Figure 9 shows FFTs of low demodulation frequency data
at varying collection times. Certain frequency elements are
evident throughout, which are not evident at higher demodula-
tion frequencies. These components are visible in data
extracted both via the DACs and via the STEMlab’s Ethernet
port.
Figure 10 shows the effect of time constant on noise. Although
noise decreases with longer time constants, signal distortions as seen
in Fig. 8 limit the choice of time constant used.
Figure 11 shows the measured 10 MHz passband of both
the RePLIA and HF2LI along with a Lorentzian fit of the data,
demonstrating a rough conformation with such a line shape. These
data give a full-width half-maximum of 2.6 kHz for the RePLIA
and 2 kHz for the HF2LI. Figures 8 and 9 both contain arti-
facts arising from the single order filter. Increasing the order of
the filter may reduce the prominence of these features, although
experiments with the HF2LI suggest that such benefits may be
marginal.
Higher noise at lower frequencies, as seen in Fig. 3, is consistent
with flicker noise of the input stage, as demonstrated in Fig. 12, in
that it is of the form of 1/f.
FIG. 11. (a) RePLIA and (b) HF2LI 10 MHz passbands with Lorentzian fits with 2.6
kHz and 2 kHz linewidths, respectively. Note that the x-axes cover different ranges
for these data.

FIG. 10. FFTs of noise at varying time constant at a demodulation frequency of

500 kHz. Note that the 0.00 001 s trace is below the minimum time constant as FIG. 12. FFT of the signal demodulated at 30 kHz, with a fit of f (x) = a + b ⋅ 1/f ,
detailed in Table II. where a = 5.6 × 10−5 , b = 0.001, consistent with flicker noise of the board.

Rev. Sci. Instrum. 90, 094701 (2019); doi: 10.1063/1.5083797 90, 094701-8
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APPENDIX B: HARDWARE AND SOFTWARE NOTES Cross talk between input channels results in a signal 0.3% of the
Largely, the RePLIA is limited by the factors introduced by input signal amplitude reflected in the secondary input. The output
the STEMlab’s hardware and software. The maximum sample rate voltage range is limited by the board to ±1 V.
of the demodulated signal corresponds to the output sample rate of Figure 13 represents the same data as Fig. 2 in the main
the STEMlab (125 MS/s) when using the DAC outputs. However, text, but as plain FFTs of noise data as opposed to noise spectral
this sampling rate is limited instead by the network connection when density.
extracting data via the Ethernet adapter. The RePLIA has been used for magnetometry using an ensem-
Mathematical operations such as Aout = Ain − Bin have not been ble of nitrogen vacancy centers in diamond. We intend to apply this
implemented at the current time, although this is entirely plausible technique to magnetocardiography, where it would be preferable to
by adding such functionality within the FPGA code. use approximately 200 sensors, requiring 100 dual channel lock-in
Power consumption for the RePLIA is 4 W when idle and <6 W amplifiers.42
during lock-in operation.
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