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Roll no 001 dld assignment

LAB SESSION 4 (Open Ended Lab)

LABORATORY TASK:

Design and Implement a four bit adder using logic gate ICs.

Introduction
The Full Adder is capable of adding only two single-digit binary number along with a
carry input. But in practice, you need to add binary numbers which are much longer
than just one bit. To add two n-bit binary numbers you need to use the n-bit parallel
adder. It uses several full adders in cascade. The carry output of the previous full adder
is connected to carry input of the next full adder.

4-bit binary adder

In the 4 bit adder, first block is a half-adder that has two inputs as A0B0 and produces their sum
S0 and a carry bit C1. Next block should be full adder as there are three inputs applied to it.
Hence this full adder produces their sum S1 and a carry C2. This will be followed by other two
full adders and thus the final sum is C4S3S2S1S0. 

Consider two 4-bit binary numbers A and B as inputs to the Digital Circuit for the operation with
digits

A0 A1 A2 A3 for A

B0 B1 B2 B3 for B
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Roll no 001 dld assignment

 These full adders perform the addition of two 4-bit binary numbers. The sum (∑) outputs are
provided for each bit and the resultant carry (C4) is obtained from the fourth bit.
These adders feature full internal look ahead across all four bits.

TRUTHTABLE
A B Ci S Cout
n
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1`
1 1 0 0 1
1 1 1 1 1

SIMULATION
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Roll no 001 dld assignment

LAB SESSION 5 (Open Ended Lab)

LABORATORY TASK:
Design and Implement a four bit subtractor using logic gate ICs.

INTRODUCTION

A combinational logic circuit performs a subtraction between the two binary

bits by considering borrow of the lower significant stage is called as the full
subtractor. In this, subtraction of the two digits is performed by taking into
consideration whether a 1 has already borrowed by the previous adjacent
lower minuend bit or not.

Four bit subtractor

As their name implies, a Binary Subtractor is a decision making circuit that
subtracts two binary numbers from each other, for example, X – Y to find the
resulting difference between the two numbers.
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Roll no 001 dld assignment
Unlike the Binary Adder which produces a SUM and a CARRY bit when two
binary numbers are added together, the binary subtractor produces a
DIFFERENCE, D by using a BORROW bit, B from the previous column. Then
obviously, the operation of subtraction is the opposite to that of addition.

It has three input terminals in which two terminals corresponds to the two bits
to be subtracted (minuend A and subtrahend B), and a borrow bit Bi
corresponds to the borrow operation. There are two outputs, one corresponds
to the difference D output and other borrow output Bo.

To perform the subtraction of binary numbers with more than one bit is
performed through the parallel subtractors. This 4 bit parallel subtractor can
be designed in several ways, including combination of half and full
subtractors, all full subtractors, all full adders with subtrahend complement
input, etc.

It is also possible to design a 4 bit parallel subtractor 4 full adders as shown in

the above figure. This circuit performs the subtraction operation by
considering the principle that the addition of minuend and the complement of
the subtrahend is equivalent to the subtraction process.

TRUTHTABLE
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Roll no 001 dld assignment
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

SIMULATION
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Roll no 001 dld assignment

LAB SESSION 9 (Open Ended Lab)

LABORATORY TASK:

TASK 1: Parity Generator: [CLO-3]

• Design a parity generator by using a 74151 multiplexer. Fill the output column of the

following Table for a 5-bit code in which four of the bits (A, B, C, D) represents the
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Roll no 001 dld assignment
information to be sent and fifth bit (x), represents the parity bit. The required parity is an

odd parity. The inputs A, B, C and D correspond to the select inputs of 74151. Complete

the Table by filling in the last column with 0,1 or A, A’.

CONNECT
INPUT OUTPU DATA
T TO

A B C D X
0 0 0 0 1
0 0 0 1 0 A’
0 0 1 0 0
0 0 1 1 1 A
0 1 0 0 0
0 1 0 1 1 A
0 1 1 0 1
0 1 1 1 0 A’
1 0 0 0 0
1 0 0 1 1 A
1 0 1 0 1
1 0 1 1 0 A’
1 1 0 0 1
1 1 0 1 0 A’
1 1 1 0 0
1 1 1 1 1 A

• Simulate the circuit using proteus, use 74151 multiplexer and Binary switches for inputs.

Connect an LED to the multiplexer output so that it represents the parity bit which lights

any time when the four bits input have even parity. Simulate the circuit and test each input

combination filling in the table shown below.

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Roll no 001 dld assignment

SIMULATION

Vote counter
A committee is composed of a chairman (C), a senior member (S), and a member (M).

The rules of the committee state that:

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Roll no 001 dld assignment
1. The vote of the member (M) will be counted as 2 votes

2. The vote of the senior member (S) will be counted as 3 votes.

3. The vote of the chairman (C) will be counted as 5 votes.

• Each of these persons has a switch to close (“l”) when voting yes and to open (“0”) when

voting no. It is necessary to design a circuit that displays the total number of votes for

each issue. Use a seven-segment display and a decoder to display the required number. If

all members vote no for an issue the display should be blank. (Recall from Lab#5, that a

binary input 15 into the 7446 blanks all seven segments).

• If all members vote yes for an issue, the display should be 0. Otherwise the display shows

a decimal number equal to the number of 'yes' votes. Use two 74153 units, which include

four multiplexers to design the combinational circuit that converts the inputs from the

members’ switch to the BCD digit for the 7446. In Proteus use +5V for Logic 1 and

ground for Logic 0 and use switches for C, S, and M and verify your design.

simulation
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Roll no 001 dld assignment