Scribd Logo
Upload

Welcome to Scribd!

  • 98 views

    EE-221 - Digital Logic Design: DE-41 (EE) - Syn A&B Final Project

    Uploaded by

    Hafsa Awan
    The document describes a final project assignment to design and simulate a 4-bit arithmetic logic unit (ALU) that performs various logic and arithmetic operations on 4-bit inputs A and B. The ALU must output the result to C and status flags to Status1 and Status2 depending on the selected operation from the OpSel input. The design must include a 4-bit ripple carry adder, 4-bit counter, and other logic. The submission requires a report with circuit diagram, operation truth table, design explanation, and logic expressions along with a working Proteus simulation file.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    EE-221 - Digital Logic Design: DE-41 (EE) - Syn A&B Final Project

    Uploaded by

    Hafsa Awan
    98 views2 pages
    The document describes a final project assignment to design and simulate a 4-bit arithmetic logic unit (ALU) that performs various logic and arithmetic operations on 4-bit inputs A and B. The ALU must output the result to C and status flags to Status1 and Status2 depending on the selected operation from the OpSel input. The design must include a 4-bit ripple carry adder, 4-bit counter, and other logic. The submission requires a report with circuit diagram, operation truth table, design explanation, and logic expressions along with a working Proteus simulation file.

    Original Title

    ALUProject_DE41_DLD

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document describes a final project assignment to design and simulate a 4-bit arithmetic logic unit (ALU) that performs various logic and arithmetic operations on 4-bit inputs A and B. The ALU must output the result to C and status flags to Status1 and Status2 depending on the selected operation from the OpSel input. The design must include a 4-bit ripple carry adder, 4-bit counter, and other logic. The submission requires a report with circuit diagram, operation truth table, design explanation, and logic expressions along with a working Proteus simulation file.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    98 views2 pages

    EE-221 - Digital Logic Design: DE-41 (EE) - Syn A&B Final Project

    Uploaded by

    Hafsa Awan
    The document describes a final project assignment to design and simulate a 4-bit arithmetic logic unit (ALU) that performs various logic and arithmetic operations on 4-bit inputs A and B. The ALU must output the result to C and status flags to Status1 and Status2 depending on the selected operation from the OpSel input. The design must include a 4-bit ripple carry adder, 4-bit counter, and other logic. The submission requires a report with circuit diagram, operation truth table, design explanation, and logic expressions along with a working Proteus simulation file.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 2

    EE-221 – Digital Logic Design

    DE-41(EE) - Syn A&B

    Final Project
    Design and simulate a 4-Bit ALU that performs following operations.

    Operation Output / Description


    Addition Output C = A+B
    Status1 = Carry_out
    Status2 = Overflow
    Subtraction Output C = A-B
    Status1 = Carry_out
    Status2 = Overflow
    2’s Complement Output C = 2’s Complement of A or B
    of A or B Status = Don’t Care
    1’s Complement Output C = 1’s Complement of A or B
    of A or B Status = Don’t Care
    Increment A or Output C = A + 1 or B + 1
    B Status1 = Carry_out
    Status2 = Overflow
    Decrement A or Output C = A - 1 or B - 1
    B Status1 = Carry_out
    Status2 = Overflow
    Bitwise OR Output C = Bitwise OR of A, B
    Status = Don’t Care
    Bitwise AND Output C = Bitwise AND of A, B
    Status = Don’t Care
    Bitwise XOR Output C = Bitwise XOR of A, B
    Status = Don’t Care
    Load A Load A into a 4 Bit Counter
    Output C = A
    Status = Don’t Care
    Count Up Count Up from initial value of A
    Output C = Count Value
    Status = Don’t Care
    Comparison Compare A and B
    Status1 = 1 if A and B are equal, else zero
    Status2 = 1 if A > B, else zero
    Output C = Don’t Care
    Inputs
    You can apply Inputs (A, B and OpSel) using DIP switches

    Outputs
    Display your outputs (Status1, Status2 and Output C) on LEDs. LEDs should show result
    according to the selected operation (OpSel).

    OpSel
    You can select between different operations using OpSel input. It is up to you to decide OpSel
    value for various operations.

    4-Bit ALU
    Logic inside this block should consist of at least one 4 bit Ripple carry adder, a 4 bit counter and
    any other logic required to implement your design (multiplexers, gates, decoders etc.)

    Clock
    Use a 1 Hz clock from a function generator.

    Submission
    Your submission should include
    1) A report including
    o Complete circuit / block diagram
    o Table listing the OpSel value of various operations
    o Detailed explanation of the working of your design
    o Expressions and K-map for all custom combinational logic functions/blocks
    2) Working proteus simulation file

    You might also like