MC14027B

Dual J-K Flip-Flop

The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.

Features
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• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge−Clocked Flip−Flop Design
SOIC−16
• Logic State is Retained Indefinitely with Clock Level Either High or D SUFFIX
Low; Information is Transferred to the Output Only on the CASE 751B
Positive−Going Edge of the Clock Pulse
• Capable of Driving Two Low−Power TTL Loads or One Low−Power PIN ASSIGNMENT
Schottky TTL Load Over the Rated Temperature Range
QA 1 16 VDD
• Pin−for−Pin Replacement for CD4027B
QA 2 15 QB
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 CA 3 14 QB
Qualified and PPAP Capable RA 4 13 CB
• This Device is Pb−Free and is RoHS Compliant KA 5 12 RB
JA 6 11 KB
MAXIMUM RATINGS (Voltages Referenced to VSS)
SA 7 10 JB
Symbol Parameter Value Unit
VSS 8 9 SB
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V
(DC or Transient) MARKING DIAGRAM
Iin, Iout Input or Output Current ± 10 mA
(DC or Transient) per Pin 16
PD Power Dissipation, per Package 500 mW 14027BG
(Note 1) AWLYWW
TA Ambient Temperature Range −55 to +125 °C
1
Tstg Storage Temperature Range −65 to +150 °C
TL Lead Temperature 260 °C A = Assembly Location
(8−Second Soldering) WL = Wafer Lot
Stresses exceeding those listed in the Maximum Ratings table may damage the YY, Y = Year
device. If any of these limits are exceeded, device functionality should not be WW = Work Week
assumed, damage may occur and reliability may be affected. G = Pb−Free Indicator
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high ORDERING INFORMATION
static voltages or electric fields. However, precautions must be taken to avoid See detailed ordering and shipping information in the package
applications of any voltage higher than maximum rated voltages to this dimensions section on page 2 of this data sheet.
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 8 MC14027B/D
 MC14027B

TRUTH TABLE
Inputs Outputs*
C† J K S R Qn‡ Qn+1 Qn+1
1 X 0 0 0 1 0
X 0 0 0 1 1 0
0 X 0 0 0 0 1
X 1 0 0 1 0 1
1 1 0 0 Qo Qo Qo
X X 0 0 X Qn Qn No
Change
X X X 1 0 X 1 0
X X X 0 1 X 0 1
X X X 1 1 X 1 1
X = Don’t Care ‡ = Present State
† = Level Change * = Next State

BLOCK DIAGRAM

S
6 J Q 1

3 C
5 K Q 2
R
4

S
10 J Q 15

13 C
11 K Q 14
R
12

VDD = PIN 16
VSS = PIN 8

ORDERING INFORMATION
Device Package Shipping†
MC14027BDG SOIC−16 48 Units / Rail
(Pb−Free)

NLV14027BDG* SOIC−16 48 Units / Rail

(Pb−Free)

MC14027BDR2G SOIC−16 2500 Units / Tape & Reel

(Pb−Free)

NLV14027BDR2G* SOIC−16 2500 Units / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC14027B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

−55_C 25_C 125_C

VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − −0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − −1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − −3.4 −8.8 − −2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ± 0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 1.0 − 0.002 1.0 − 30 mAdc
(Per Package) 10 − 2.0 − 0.004 2.0 − 60
15 − 4.0 − 0.006 4.0 − 120
Total Supply Current (Notes 3 & 4) IT 5.0 IT = (0.8 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (1.6 mA/kHz) f + IDD
Per Package) 15 IT = (2.4 mA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002.

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 MC14027B

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

Typ
Characteristic Symbol VDD Min (Note 6) Max Unit

Output Rise and Fall Time tTLH, ns

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 − 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 − 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns 15 − 40 80

Propagation Delay Times** tPLH, ns

Clock to Q, Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 − 50 100
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 − 50 100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 − 350 450
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 − 100 200
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 − 75 150
Setup Times tsu 5.0 140 70 − ns
10 50 25 −
15 35 17 −
Hold Times th 5.0 140 70 − ns
10 50 25 −
15 35 17 −
Clock Pulse Width tWH, tWL 5.0 330 165 − ns
10 110 55 −
15 75 38 −
Clock Pulse Frequency fcl 5.0 − 3.0 1.5 MHz
10 − 9.0 4.5
15 − 13 6.5
Clock Pulse Rise and Fall Time tTLH, tTHL 5.0 − − 15 ms
10 − − 5.0
15 − − 4.0
Removal Times trem ns
5 90 10 −
Set 10 45 5 −
15 35 3 −
5 50 – 30 −
Reset 10 25 – 15 −
15 20 – 10 −
Set and Reset Pulse Width tWH 5.0 250 125 − ns
10 100 50 −
15 70 35 −
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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 MC14027B

20 ns 20 ns
VDD
90%
J 50%
10% VSS
20 ns 20 ns
VDD
K 90%
tsu 50%
10% VSS
tsu th
20 ns 20 ns
90% VDD
C 50%
10% VSS 20 ns 20 ns
tWH tWL 90% VDD
1 SET OR 50%
fcl RESET 10% VSS
tPLH tPHL tw trem
VOH 20 ns 20 ns
90% VDD
Q 50% 90%
CLOCK 50%
10% VOL 10% VSS
tTLH tTHL tw
tPLH
tPHL
Inputs R and S low. VOH
For the measurement of tWH, I/fcl, and PD Q or Q 50%
the Inputs J and K are kept high. VOL

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(J, K, Clock, and Output) (Set, Reset, Clock, and Output)

LOGIC DIAGRAM
(1/2 of Device Shown)

S
Q
C

J
C
C

C
K C C

C C
R
Q

C
C C

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 MC14027B

PACKAGE DIMENSIONS

SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
−A− CASE 751B−05 NOTES:
ISSUE K 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
−B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
1 8
0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F F 0.40 1.25 0.016 0.049
K R X 45 _
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
C K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
−T− SEATING P 5.80 6.20 0.229 0.244
PLANE
M J R 0.25 0.50 0.010 0.019
D 16 PL

0.25 (0.010) M T B S A S

SOLDERING FOOTPRINT*
8X
6.40
16X 1.12
1 16

16X
0.58

1.27
PITCH

8 9

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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6