MC14521B 24-Stage Frequency Divider: Marking Diagrams
MC14521B 24-Stage Frequency Divider: Marking Diagrams
MC14521B 24-Stage Frequency Divider: Marking Diagrams
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
BLOCK DIAGRAM
RESET
2
STAGES STAGES
9 6 1 THRU 17 18 THRU 24
IN 1 IN 2 Q18 Q19 Q20 Q21 Q22 Q23 Q24
VDD = PIN 16
PIN ASSIGNMENT VSS = PIN 8
5 4
7 VDD′ 3 OUT2 10 11 12 13 14 15 1
OUT 1 VSS′
Q24 1 16 VDD
RESET 2 15 Q23 Output Count Capacity
VSS′ 3 14 Q22 Q18 218 = 262,144
Q19 219 = 524,288
OUT 2 4 13 Q21 Q20 220 = 1,048,576
VDD′ 5 12 Q20 Q21 221 = 2,097,152
Q22 222 = 4,194,304
IN 2 6 11 Q19 Q23 223 = 8,388,608
OUT1 7 10 Q18 Q24 224 = 16,777,216
VSS 8 9 IN 1
ORDERING INFORMATION
Device Package Shipping†
MC14521BCPG PDIP−16
25 Units / Rail
(Pb−Free)
MC14521BDG SOIC−16
48 Units / Rail
(Pb−Free)
MC14521BDR2G SOIC−16
2500 / Tape & Reel
(Pb−Free)
MC14521BFG SOEIAJ−16
50 Units / Rail
(Pb−Free)
MC14521BFELG SOEIAJ−16
2000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD
− 55_C 25_C
Typ
125_C
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level
VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 or VDD
10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
“1” Level
VIH Vdc
(VO = 0.5 or 4.5 Vdc)
5.0 3.5 − 3.5 2.75 − 3.5 −
(VO = 1.0 or 9.0 Vdc)
10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc)
15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 4.5 Vdc) Source 5.0 – 0.25 − – 0.2 – 0.36 − – 0.14 −
(VOH = 9.0 Vdc) Pin 4 10 – 0.62 − – 0.5 – 0.9 − – 0.35 −
(VOH = 13 Vdc) 15 – 1.8 − – 1.5 – 3.5 − – 1.1 −
(VOH = 2.5 Vdc) Source
5.0 – 3.0 − – 2.4 – 4.2 − – 1.7 − mAdc
(VOH = 4.6 Vdc) Pins 1, 7, 10,
5.0 – 0.64 − – 0.51 – 0.88 − – 0.36 −
(VOH = 9.5 Vdc) 11, 12, 13, 14
10 – 1.6 − – 1.3 – 2.25 − – 0.9 −
(VOH = 13.5 Vdc) and 15
15 – 4.2 − – 3.4 – 8.8 − – 2.4 −
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc) IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 1.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
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MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol
VDD
Vdc Min
Typ
(Note 6) Max Unit
Output Rise and Fall Time (Counter Outputs) tTLH, tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 − 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 − 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns 15 − 40 80
Propagation Delay Time tPHL, tPLH ms
Clock to Q18
tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns 5.0 − 4.5 9.0
tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns 10 − 1.7 3.5
tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns 15 − 1.3 2.7
Clock to Q24
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
5.0 − 6.0 12
tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns
10 − 2.2 4.5
tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns
15 − 1.7 3.5
Propagation Delay Time tPHL ns
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns 5.0 − 1300 2600
tPHL = (0.66 ns/pF) CL + 467 ns 10 − 500 1000
tPHL = (0.5 ns/pF) CL + 350 ns 15 − 375 750
Clock Pulse Width tWH(cl) 5.0 385 140 − ns
10 150 55 −
15 120 40 −
Clock Pulse Frequency fcl 5.0 − 3.5 2.0 MHz
10 − 9.0 5.0
15 − 12 6.5
Clock Rise and Fall Time tTLH, tTHL 5.0 − − 15 ms
10 − − 5.0
15 − − 4.0
Reset Pulse Width tWH(R) 5.0 1400 700 − ns
10 600 300 −
15 450 225 −
Reset Removal Time trem 5.0 30 – 200 − ns
10 0 – 160 −
15 – 40 – 110 −
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
500 mF 0.01 mF
ID
CERAMIC
VDD VDD
Q18 20 ns 20 ns
PULSE CL VDD
IN 2 Q19 Vin 90%
GENERATOR CL 50%
Q20 10% 0V
CL
Q21 50% DUTY CYCLE
Q22 CL
Q23 CL
R
Q24 CL
CL
VSS VSS
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MC14521B
VDD
VDD VDD′
20 ns 20 ns 20 ns
IN 2
Q18
PULSE IN 2 CL 90%
GENERATOR Q19 50%
CL 10%
Q20
CL tWL tWH
Q21
Q22 CL
90%
Q23 CL 50%
R Qn
CL 10%
Q24
CL tPLH tPHL
VSS VSS′ tTLH tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
*Optional for low power operation,
10 kW ≤ R ≤ 70 kW. *Complete oscillator includes crystal, capacitors, and resistors.
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MC14521B
100
8.0 VDD = 10 V TEST CIRCUIT
50
OF RTC
10 (C = 1000 pF)
0
5.0 (RS ≈ 2RTC)
f AS A FUNCTION
10 V OF C
-4.0 2.0 (RTC = 56 kW)
1.0 (RS = 120 k)
-8.0 5.0 V 0.5
-12 0.2
RTC = 56 kW, RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
C = 1000 pF
{ RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
0.1
-16 1.0 k 10 k 100 k 1.0 m
-55 -25 0 25 50 75 100 125 RTC, RESISTANCE (OHMS)
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY 0.0001 0.001 0.01 0.1
C, CAPACITANCE (mF)
Figure 5. RC Oscillator Stability Figure 6. RC Oscillator Frequency as a
Function of RTC and C
RS RTC VDD VDD
C
VDD′
VDD VDD′
IN 1 Q18
IN 1 OUT 1 Q19
OUT 2 Q20
Q18 Q21
Q19 PULSE IN 2 Q22
IN 2 Q20 GENERATOR Q23
Q21 Q24
Q22 OUT 1
Q23 R OUT 2
R Q24
VSS VSS
VSS VSS′
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
FUNCTIONAL TEST SEQUENCE
Inputs Outputs Comments
Reset In 2 Out 2 VSS′ VDD′ Q18 Counter is in three 8−stage sections
thru in parallel mode Counter is reset. In 2
Q24 and Out 2 are connected together.
1 0 0 VDD GND 0
0 1 1 First “0” to “1” transition on In 2,
A test function (see Figure 8) has been included Out 2 node.
for the reduction of test time required to exercise all
24 counter stages. This test function divides the 0 0 255 “0” to “1” transitions are clocked
counter into three 8−stage sections, and 255 1 1 into this In 2, Out 2 node.
counts are loaded in each of the 8−stage sections − −
in parallel. All flip−flops are now at a logic “1”. The − −
counter is now returned to the normal 24−stages in − −
series configuration. One more pulse is entered into 1 1 1 The 255th “0” to “1” transition.
Input 2 (In 2) which will cause the counter to ripple
from an all “1” state to an all “0” state. 0 0 1
0 0 1
GND Counter converted back to 24−stages
1 0 1
in series mode.
VDD
1 0 1 Out 2 converts back to an output.
Counter ripples from an all “1” state
0 1 0 to an all “0” stage.
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MC14521B
LOGIC DIAGRAM
VDD RESET
5 2
9 STAGES
1 2 8
3 THRU 7
IN 1
6 4
IN 2 OUT 2
7 3
OUT 1 VSS
9 10 STAGES 16
11 THRU 15
17 18 19 20 21 22 23 24
10 11 12 13 14 15 1 VDD = PIN 16
Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS = PIN 8
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MC14521B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE
1 8 MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F INCHES MILLIMETERS
C L DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
S B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
SEATING
−T− PLANE
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H K M
J H 0.050 BSC 1.27 BSC
G J 0.008 0.015 0.21 0.38
D 16 PL K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
0.25 (0.010) M T A M M 0_ 10 _ 0_ 10 _
S 0.020 0.040 0.51 1.01
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
16 9 MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B− P 8 PL
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 8
0.25 (0.010) M B S PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
F C 1.35 1.75 0.054 0.068
K R X 45 _ D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
C G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
−T− SEATING K 0.10 0.25 0.004 0.009
PLANE
M J M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
D 16 PL R 0.25 0.50 0.010 0.019
0.25 (0.010) M T B S A S
SOLDERING FOOTPRINT
8X
6.40
16X 1.12
1 16
16X
0.58
1.27
PITCH
8 9
DIMENSIONS: MILLIMETERS
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MC14521B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
16 9 LE 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
Q1 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
E HE M_ MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1 8 L 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
DETAIL P INCLUDE DAMBAR PROTRUSION. ALLOWABLE
Z DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
D TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
VIEW P
e A RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
c TO BE 0.46 ( 0.018).
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A --- 2.05 --- 0.081
A1 A1 0.05 0.20 0.002 0.008
b b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.007 0.011
0.13 (0.005) M 0.10 (0.004) D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z --- 0.78 --- 0.031
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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