MC14512B

8-Channel Data Selector

The MC14512B is an 8–channel data selector constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
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sequence generation.
• Diode Protection on All Inputs
• Single Supply Operation MARKING
DIAGRAMS
• 3–State Output (Logic “1”, Logic “0”, High Impedance)
16
• Supply Voltage Range = 3.0 Vdc to 18 Vdc PDIP–16
• Capable of Driving Two Low–power TTL Loads or One Low–power P SUFFIX MC14512BCP
AWLYYWW
Schottky TTL Load Over the Rated Temperature Range CASE 648
1

16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) SOIC–16
14512B
D SUFFIX AWLYWW
Symbol Parameter Value Unit
CASE 751B
VDD DC Supply Voltage Range – 0.5 to +18.0 V 1
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V
(DC or Transient) 16
Iin, Iout Input or Output Current ± 10 mA SOEIAJ–16
(DC or Transient) per Pin F SUFFIX MC14512B
CASE 966 AWLYWW
PD Power Dissipation, 500 mW
per Package (Note NO TAG) 1
TA Ambient Temperature Range – 55 to +125 °C
A = Assembly Location
Tstg Storage Temperature Range – 65 to +150 °C
WL or L = Wafer Lot
TL Lead Temperature 260 °C YY or Y = Year
(8–Second Soldering) WW or W = Work Week
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C ORDERING INFORMATION

This device contains protection circuitry to guard against damage due to high Device Package Shipping
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this MC14512BCP PDIP–16 2000/Box
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
MC14512BD SOIC–16 48/Rail
Unused inputs must always be tied to an appropriate logic voltage level (e.g., MC14512BDR2 SOIC–16 2500/Tape & Reel
either VSS or VDD). Unused outputs must be left open.
MC14512BF SOEIAJ–16 See Note 1.

MC14512BFL1 SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local
ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 3 MC14512B/D
 MC14512B

TRUTH TABLE
C B A Inhibit Disable Z
0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3
1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7
X X X 1 0 0
X X X X 1 High
Impedance
X = Don’t Care

PIN ASSIGNMENT
X0 1 16 VDD
X1 2 15 DIS
X2 3 14 Z
X3 4 13 C
X4 5 12 B
X5 6 11 A
X6 7 10 INH
VSS 8 9 X7

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 MC14512B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT 5.0 IT = (0.8 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.6 µA/kHz) f + IDD
Per Package) 15 IT = (2.4 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

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 MC14512B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C, See Figure 1)

All Types
Characteristic Symbol VDD Typ (8.) Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time (Figure 2) tPLH ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
Propagation Delay Time (Figure 2) tPHL ns
Inhibit, Control, or Data to Z 5.0 330 650
10 125 250
15 85 170
3–State Output Delay Times (Figure 3) tPHZ, tPLZ, 5.0 60 150 ns
“1” or “0” to High Z, and tPZH, tPZL 10 35 100
High Z to “1” or “0” 15 30 75
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ID VDD

DISABLE
INHIBIT Z
A CL
B
C
X0
X1
PULSE X2
Vin 50% GENERATOR
50% X3
DUTY X4
CYCLE X5
X6
X7
VSS

Figure 1. Power Dissipation Test Circuit and Waveform

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 MC14512B

VDD
20 ns 20 ns
90% VDD
DISABLE DATA 50%
INHIBIT Z 10% VSS
A tPLH tPHL
CL 90% VOH
B 50%
C Z 10%
VOL
X0 tTLH tTHL
PULSE X1
GENERATOR TEST CONDITIONS:
X2 INHIBIT = VSS
X3 A, B, C = VSS
X4
X5 20 ns 20 ns
X6 INHIBIT, VDD
90%
X7 A, B, OR C 50%
10% VSS
tPHL tPLH
VSS Parameter Test Conditions 90% VOH
50%
Inhibit to Z A, B, C = VSS, XO = VDD Z 10% VOL
A, B, C to Z Inh = VSS, XO = VDD tTHL tTLH

Figure 2. AC Test Circuit and Waveforms

VDD
PULSE 20 ns
VDD 20 ns
GENERATOR VDD
DISABLE 90%
VDD 50%
INHIBIT Z DISABLE 10%
CL VSS
A INPUT
B 1k S1 tPZL
S3 tPLZ
C VOH
90%
X0 S2 OUTPUT 10% VOL ≈ 2.5 V @ VDD = 5 V,
S4 X1 10 V, AND 15 V
tPHZ tPZH
X2 ≈ 2 V @ VDD = 5 V
X3 VSS OUTPUT
90%
VOH ≈ 6 V @ VDD = 10 V
VSS X4 10% ≈ 10 V @ VDD = 15 V
VOL
X5
X6 Switch Positions for 3–State Test
X7 Test S1 S2 S3 S4
tPHZ Open Closed Closed Open
VSS
tPLZ Closed Open Open Closed
tPZL Closed Open Open Closed
tPZH Open Closed Closed Open

Figure 3. 3–State AC Test Circuit and Waveform

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 MC14512B

LOGIC DIAGRAM
13
C
12
B 15
11 DISABLE
A
1 10 DATA
X0 SELECTED
BUS
INHIBIT DEVICE
2 VDD IOD
X1
MC14512B
3 IL
X2
14 LOAD
Z ITL
4
X3 MC14512B

5
X4
ITL
6 MC14512B
X5

7 VSS
X6

9
X7 1 1
OUT
IN IN OUT

2 2
TRANSMISSION
GATE

3–STATE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit Data (including fanout to other device inputs), and can be
Selectors can be connected to a single date bus as shown. calculated by:
One MC14512B is selected by the 3–state control, and the IOD – IL
remaining devices are disabled into a high–impedance “off” N= +1
ITL
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive N must be calculated for both high and low logic state of the
current, IOD, 3–state or disable output leakage current, ITL, bus line.
and the load current, IL, required to drive the bus line

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 MC14512B

PACKAGE DIMENSIONS

PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08 NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE R Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
–A– ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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 MC14512B

PACKAGE DIMENSIONS

SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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