MC14585B

4-Bit Magnitude
Comparator
The MC14585B 4–Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A http://onsemi.com
< B, A = B, and A > B). This device compares two 4–bit words (A and
B) and determines whether they are “less than”, “equal to”, or “greater MARKING
than” by a high level on the appropriate output. For words greater than DIAGRAMS
4–bits, units can be cascaded by connecting outputs (A > B), (A < B), 16
and (A = B) to the corresponding inputs of the next significant PDIP–16
P SUFFIX MC14585BCP
comparator. Inputs (A < B), (A = B), and (A > B) on the least AWLYYWW
CASE 648
significant (first) comparator are connected to a low, a high, and a low,
respectively. 1
Applications include logic in CPU’s, correction and/or detection of 16
instrumentation conditions, comparator in testers, converters, and SOIC–16
14585B
D SUFFIX AWLYWW
controls. CASE 751B
• Diode Protection on All Inputs 1
• Expandable 16
• Applicable to Binary or 8421–BCD Code SOEIAJ–16
MC14585B
•
F SUFFIX
Supply Voltage Range = 3.0 Vdc to 18 Vdc CASE 966 AWLYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power
1
Schottky TTL Load over the Rated Temperature Range
• Can be Cascaded – See Fig. 3 A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) WW or W = Work Week
Symbol Parameter Value Unit
VDD DC Supply Voltage Range – 0.5 to +18.0 V
ORDERING INFORMATION
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V
(DC or Transient) Device Package Shipping

Iin, Iout Input or Output Current ±10 mA MC14585BCP PDIP–16 2000/Box

(DC or Transient) per Pin
MC14585BD SOIC–16 48/Rail
PD Power Dissipation, 500 mW
per Package (Note 3.) MC14585BDR2 SOIC–16 2500/Tape & Reel

TA Ambient Temperature Range – 55 to +125 °C MC14585BF SOEIAJ–16 See Note 1.

Tstg Storage Temperature Range – 65 to +150 °C 1. For ordering information on the EIAJ version of
TL Lead Temperature 260 °C the SOIC packages, please contact your local
ON Semiconductor representative.
(8–Second Soldering)
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 3 MC14585B/D
 MC14585B

PIN ASSIGNMENT
B2 1 16 VDD
A2 2 15 A3
(A = B)out 3 14 B3
(A u B)in 4 13 (A u B)out
(A t B)in 5 12 (A t B)out
(A = B)in 6 11 B0
A1 7 10 A0
VSS 8 9 B1

BLOCK DIAGRAM

4 (A > B)in
6 (A = B)in
5 (A < B)in (A > B)out 13
10 A0
11 B0
7 A1 (A = B)out 3
9 B1
2 A2
1 B2 (A < B)out 12
15 A3
14 B3

VDD = PIN 16
VSS = PIN 8

TRUTH TABLE (x = Don’t Care)

Inputs
Comparing Cascading Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A<B A=B A>B A<B A=B A>B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0

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 MC14585B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
– 55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current (5.) (6.) IT 5.0 IT = (0.6 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (1.2 µA/kHz) f + IDD
Per Package) 15 IT = (1.8 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

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 MC14585B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Output Rise and Fall Time
Symbol
tTLH,
VDD Min Typ (8.) Max Unit
ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Turn–On, Turn–Off Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 345 ns tPHL 5.0 — 430 860
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns 10 — 180 360
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns 15 — 130 260
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

20 ns
20 ns
VDD
A3
1 VSS
2f VDD
B3
VSS
20 ns 20 ns
VOH
(A > B)out VDD
90%
VOL 50%
B0
VOH 10% VSS
(A = B)out tPLH tPHL
VOL VOH
90%
VOH 50%
(A < B)out
(A < B)out 10% VOL
VOL
tTLH tTHL
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low. Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
f in respect to a system clock. A2, B1, A1, A0, and (A<B) low.

Figure 1. Dynamic Power Dissipation Figure 2. Dynamic Signal Waveforms

Signal Waveforms

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 MC14585B

WORD
B = B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
WORD
A= A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
VSS VDD VSS

(A<B)
(A=B)
(A>B)
B3 A3 B2 A2 B1 A1 B0 A0
OUTPUT MC14585B

(A<B)
(A=B)
(A>B)
INPUTS

MC14585B

MC14585B

WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.
(A<B)
(A=B)
(A>B)

OUTPUTS
Figure 3. Cascading Comparators

LOGIC DIAGRAM
15
A3

14
B3
2
A2

1
B2
7 12
A1 (A < B)out

9
B1
10
A0

11
B0

5
(A < B)in
3
6 (A = B)out
(A = B)in
13
4 (A > B)out
(A > B)in

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 MC14585B

PACKAGE DIMENSIONS

PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08 NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE R Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
–A– ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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 MC14585B

PACKAGE DIMENSIONS

SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031

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 MC14585B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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