LPC540xx/LPC54S0xx: 1. General Description

LPC540xx/LPC54S0xx
32-bit ARM Cortex-M4 microcontroller; 360 kB SRAM;

High-speed USB device/host + PHY; Full-speed USB
device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD, SDIO;
12-bit 5 Msamples/s ADC; DMIC subsystem
Rev. 2.1 — 15 September 2020 Product data sheet
1. General description
The LPC540xx/LPC54S0xx is a family of ARM Cortex-M4 based microcontrollers for
embedded applications featuring a rich peripheral set with very low power consumption
and enhanced debug features.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC540xx/LPC54S0xx family includes 360 KB of on-chip SRAM, a quad SPI Flash
Interface (SPIFI) for expanding program memory, one high-speed and one full-speed USB
host and device controller, Ethernet AVB, LCD controller, Smart Card Interfaces,
SD/MMC, CAN FD, an External Memory Controller (EMC), a DMIC subsystem with PDM
microphone interface and I2S, five general-purpose timers, SCTimer/PWM, RTC/alarm
timer, Multi-Rate Timer (MRT), a Windowed Watchdog Timer (WWDT), ten flexible serial
communication peripherals (USART, SPI, I2S, I2C interface), Secure Hash Algorithm
(SHA), AES-256 engine, Physical Unclonable Function (PUF), secure boot features,
12-bit 5.0 Msamples/sec ADC, and a temperature sensor.
2. Features and benefits

 ARM Cortex-M4 core (version r0p1):
 ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.
 Floating Point Unit (FPU) and Memory Protection Unit (MPU).
 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
 Non-maskable Interrupt (NMI) input with a selection of sources.
 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points. Includes Serial Wire Output and ETM Trace for enhanced
debug capabilities, and a debug timestamp counter.
 System tick timer.
NXP Semiconductors LPC540xx/LPC54S0xx
32-bit ARM Cortex-M4 microcontroller
 On-chip memory:
 Up to 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB
traffic.
 General-purpose One-Time Programmable (OTP) memory for user application
specific data and for AES keys.
 ROM API support:
 In-Application Programming (IAP) and In-System Programming (ISP).
 ROM-based USB drivers (HID, CDC, MSC, and DFU).
 Supports serial interface booting (UART, I2C, SPI) from an application processor,
automated booting from NOR flash (SPI on device revision 1B, quad SPIFI,
8/16/32-bit external parallel flash), and USB booting (full-speed, high-speed).
 FRO API for selecting FRO output frequency.
 OTP API for programming OTP memory.
 Random Number Generator (RNG) API.
 RSA API calls (LPC54S0xx only).
 Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or single-bit
SPI mode), and parallel NOR flash.
 Secure Boot features on LPC54S0xx devices:
 Supports boot image authentication using RSASSA-PKCS1-v1_5 signature
verification with 2048-bit public keys (2048-bit modulus, 32-bit exponent).
 Supports Root of Trust (RoT) establishment by comparing the SHA-256 hash
digest of the RoT public key with OTP memory contents.
 Supports secure anti-rollback of images through revocation of image key
certificate. Supports up to 8 revocations through OTP fuses.
 Supports boot of AES-GCM encrypted images with a 128-bit symmetric key stored
in OTP memory or a 256-bit symmetric key stored using on-chip SRAM PUF.
 Secure Authentication Only Boot. Enforce booting of RSA-2048 signed images
only.
 Encrypted Image Boot. Enforce booting of AES-GCM encrypted images only.
 Enhanced Image Boot. Enforce booting of encrypted then signed images only.
 Supports Device Identifier Composition Engine (DICE) Specification (version
Family 2.0, Level 00 Revision 69) specified by Trusted Computing Group.
 Security features:
 AES-256 encryption/decryption engine with keys stored in polyfuse OTP
(LPC54S0xx only).
 Random number generator can be used to create keys with DMA support.
 Secure Hash Algorithm (SHA1/SHA2) module supports boot with dedicated DMA
controller.
 Physical Unclonable Function (PUF) root key using dedicated SRAM for silicon
fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits
(LPC54S0xx only).
LPC540xx/LPC54S0xx All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet Rev. 2.1 — 15 September 2020 2 of 174

 Serial interfaces:
 Flexcomm Interface contains up to 11 serial peripherals. Each Flexcomm Interface
(except flexcomm 10, which is dedicated for SPI) can be selected by software to be
a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S
interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI,
and I2S if supported by that Flexcomm Interface. A variety of clocking options are
available to each Flexcomm Interface and include a shared fractional baud-rate
generator.
 I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
 Two ISO 7816 Smart Card Interfaces with DMA support.
 USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
 USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode using software library.
See Technical note TN00033 for more details.
 SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
 Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and
dedicated DMA controller.
 Two CAN FD modules with dedicated DMA controller.
 Digital peripherals:
 DMA controller with 32 channels and up to 24 programmable triggers, able to
access all memories and DMA-capable peripherals.
 LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
 External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC bus
width (bit) on TFBGA180, TFBGA100, and LQFP100 packages supports up to 8/16
data line wide static memory.
 Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
 CRC engine block can calculate a CRC on supplied data using one of three
standard polynomials with DMA support.
 Up to 171 General-Purpose Input/Output (GPIO) pins.
 GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
 Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,
falling or both input edges.
 Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
 Analog peripherals:
 12-bit ADC with 12 input channels and with multiple internal and external trigger
inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two
independent conversion sequences.
 Integrated temperature sensor connected to the ADC.

 DMIC subsystem includes a dual-channel PDM microphone interface with decimators,

filtering, and hardware voice activity detection. The processed output data can be
routed directly to an I2S interface if needed.
 Timers:
 Five 32-bit general purpose timers/counters. All five timers support up to four
capture inputs and four compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests.
 One SCTimer/PWM with eight input and ten output functions (including capture
and match). Inputs and outputs can be routed to or from external pins and internally
to or from selected peripherals. Internally, the SCTimer/PWM supports 16
match/captures, 16 events, and 16 states.
 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution.
 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
 Windowed Watchdog Timer (WWDT).
 Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose
use.
 Clock generation:
 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a
selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the
selected higher frequency) that can be used as a system clock. The FRO is
trimmed to 1 % accuracy over the entire voltage and temperature range.
 Crystal oscillator with an operating range of 1 MHz to 25 MHz.
 Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.
 32.768 kHz low-power RTC oscillator.
 System PLL allows CPU operation up to the maximum CPU rate and can run from
the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz
RTC oscillator.
 Two additional PLLs for USB clock and audio subsystem.
 Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
 Clock output function with divider.
 Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
 Power control:
 Programmable PMU (Power Management Unit) to minimize power consumption
and to match requirements at different performance levels.
 Reduced power modes: sleep, deep-sleep, and deep power-down.
 Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C
peripherals when operating as slaves.
 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be
used to wake up the device from low power modes.
 Power-On Reset (POR).
 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
 Single power supply 1.71 V to 3.6 V.
 Power-On Reset (POR).

 Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
 JTAG boundary scan supported.
 128 bit unique device serial number for identification.
 Operating temperature range 40 °C to +105 °C.
 Available in TFBGA180, TFBGA100, LQFP208, and LQFP100 packages.

3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC54018JET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54018JBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1
LPC54016JET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54016JET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
LPC54005JET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
LPC54S018JET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54S018JBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1
LPC54S016JET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC54S016JET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1
LPC54S005JET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1

3.1 Ordering options

Table 2. Ordering options
EMC data bus width (bit)
Flexcomm Interface
Package Name
Ethernet AVB
Type number
Classic CAN
SRAM/kB
HS USB
CAN FD
FS USB
GPIO
SHA
LCD
AES
PUF
LPC54018 devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, LCD, SHA)
LPC54018JET180 TFBGA180 360 yes yes yes yes yes yes 8/16 11 145 yes - -
LPC54018JBD208 LQFP208 360 yes yes yes yes yes yes 8/16/32 11 171 yes - -
LPC54S018 devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, LCD, SHA, AES, PUF)
LPC54S018JET180 TFBGA180 360 yes yes yes yes yes yes 8/16 11 145 yes yes yes
LPC54S018JBD208 LQFP208 360 yes yes yes yes yes yes 8/16/32 11 171 yes yes yes
LPC54016 devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, SHA)
LPC54016JET180 TFBGA180 360 yes yes yes yes yes - 8/16 11 145 yes - -
LPC54016JBD208 LQFP208 360 yes yes yes yes yes - 8/16/32 11 171 yes - -
LPC54016JBD100 LQFP100 360 yes yes yes yes yes - 8/16 10 64 yes - -
LPC54016JET100 TFBGA100 360 yes yes yes yes yes - 8/16 10 64 yes - -
LPC54S016 devices (HS/FS USB, Ethernet, CAN 2.0+CAN FD, SHA, AES, PUF)
LPC54S016JET180 TFBGA180 360 yes yes yes yes yes - 8/16 11 145 yes yes yes
LPC54S016JBD208 LQFP208 360 yes yes yes yes yes - 8/16/32 11 171 yes yes yes
LPC54S016JBD100 LQFP100 360 yes yes yes yes yes - 8/16 10 64 yes yes yes
LPC54S016JET100 TFBGA100 360 yes yes yes yes yes - 8/16 10 64 yes yes yes
LPC54005 devices (HS/FS USB, SHA)
LPC54005JET100 TFBGA100 360 yes yes - - - - 8/16 10 64 yes - -
LPC54005JBD100 LQFP100 360 yes yes - - - - 8/16 10 64 yes - -
LPC54S005 devices (HS/FS USB, SHA, AES, PUF)
LPC54S005JET100 TFBGA100 360 yes yes - - - - 8/16 10 64 yes yes yes
LPC54S005JBD100 LQFP100 360 yes yes - - - - 8/16 10 64 yes yes yes

4. Marking
Terminal 1 index area
n
Terminal 1 index area 1
aaa-025721 aaa-011231
Fig 1. TFBGA180 and TFBGA 100 package markings Fig 2. LQFP208 package marking
n
Terminal 1 index area 1
aaa-029374
Fig 3. LQFP100 package marking
The LPC540xx/LPC54S0xx TFBGA180 and TFBGA100 packages have the following

top-side marking:
• First line: LPC540xx/LPC54S0xxJ

• Second line: ET180 or ET100
• Third line: xxxxxxxxxxxx
• Fourth line: xxxyywwx[R]x
– yyww: Date code with yy = year and ww = week.
– xR = boot code version and device revision.
The LPC540xx/LPC54S0xx LQFP208 and LQFP100 packages have the following

top-side marking:
• First line: LPC540xx/LPC54S0xxJ

• Second line: BD208 or BD100
• Third line: xxxxxxxxxxxx
• Fourth line: xxxyywwx[R]x
– yyww: Date code with yy = year and ww = week.

– xR = Boot code version and device revision.
Table 3. Device revision table

Revision identifier (R) Revision description
0A Initial device revision with Boot ROM version 21.0 for
LPC540xx only.
1B Initial device revision with Boot ROM version 21.1 for
LPC540xx and LPC54S0xx.

5. Block diagram
Figure 4 shows the LPC540xx/LPC54S0xx block diagram. In this figure, orange shaded
blocks support general purpose DMA and yellow shaded blocks include dedicated DMA
control.

JTAG test and

ISP access boundary scan ethernet LCD FS USB SDIO CAN
port interface PHY interface panel bus interface interface Xtalin Xtalout RST
DEBUG INTERFACE GENERAL ETHERNET USB 2.0 CLOCK GENERATION,

LCD clocks
PURPOSE 10/100 HOST/ CAN CAN POWER CONTROL, CLK
PANEL SDIO SHA and
ARM CORTEX-M4 DMA MAC DEVICE FD FD AND OTHER OUT
INTERFACE controls
WITH FPU/MPU CONTROLLER +AVB H D SYSTEM FUNCTIONS
I-code D-code system internal
VOLTAGE REGULATOR Vdd
bus bus bus power
BOOT ROM HS USB HS USB

64 kB PHY bus
SRAM
192 kB
SPI FLASH
SPIFI
INTERFACE
SRAM
64 kB
SRAM
32 kB
MULTILAYER
AHB MATRIX
SRAM
32 kB
SRAM
32 kB
SHA SLAVE FS USB HS USB AES256 12b ADC ADC

INTERFACE HOST HOST ENGINE 12-CH inputs
REGISTERS REGISTERS
USB RAM POLYFUSE OTP TEMP

INTERFACE 256 b SENSOR
SRAM
8 kB
D[31:0]
STATIC/DYNAMIC EXT
A[25:0]
MEMORY CONTROLLER
control
HS GPIO
GPIO
0-5
SPIFI EMC DMA LCD FS USB SCTimer/ FlexComms 0-4

REGISTERS REGISTERS REGISTERS REGISTERS DEVICE PWM -UARTs 0-4 - I2Cs 0-4
REGISTERS -SPI0s 0-4
CAN 0 CAN 1 ETHERNET HS USB CRC SDIO FlexComms 5-9

REGISTERS REGISTERS REGISTERS DEVICE ENGINE REGISTERS -UARTs 5-9
REGISTERS -SPI0s 5-9
AUDIO SUBSYS -I2Cs 5-9 - I2Ss 0,1
AHB TO D-MIC,
APB slave group 0
APB BRIDGE DECIMATOR, ETC
SYSTEM CONTROL ASYNC AHB TO APB slave group 2
APB BRIDGE
SYSTEM CONTROL (async regs)
I/O CONFIGURATION
AHB TO
2 x 32-BIT TIMERS (T3, 4)
GPIO GLOBAL INTRPTS (0, 1) APB BRIDGE APB slave group 1
GPIO INTERRUPT CONTROL PMU REGS (+BB, PVT)
PERIPH INPUT MUX SELECTS 32-BIT TIMERS (T2)
2 x 32-BIT TIMERS (T0, 1) RIT
MULTI-RATE TIMER 2 x SMARTCARDS
OTP CONTROLLER RANDOM NUMBER GEN

RTC POWER
RTC ALARM
WATCHDOG WINDOWED WDT DOMAIN
OSC REAL TIME 32 kHz
DIVIDER
CLOCK Osc
MICRO TICK TIMER
PUF
Note:
- Orange shaded blocks support Gen. Purpose DMA.
- Yellow shaded blocks include dedicated DMA Ctrl.
aaa-030339
Fig 4. LPC540xx/LPC54S0xx Block diagram

6. Pinning information
6.1 Pinning
ball A1
index area
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
aaa-026026
Transparent top view
Fig 5. TFBGA 180 Pin configuration
ball A1
index area
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
aaa-029079
Transparent top view
Fig 6. TFBGA 100 Pin configuration

208
157
1 156
52 105
104
53
aaa-026027
Fig 7. LQFP 208 Pin configuration
100
76
1 75
25 51
50
26
aaa-029081
Fig 8. LQFP 100 Pin configuration

6.2 Pin description

On the LPC540xx/LPC54S0xx, digital pins are grouped into several ports. Each digital pin
can support several different digital functions (including General Purpose I/O (GPIO)) and
an additional analog function.
Table 4. Pin description

Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_0 C4 D6 196 93 [2] PU; Z I/O PIO0_0 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI
SCK function.
I CAN1_RD — Receiver input for CAN 1.
I/O FC3_SCK — Flexcomm 3: USART or SPI clock.
O CTimer_MAT0 — Match output 0 from Timer 0.
I SCT0_GPI0 — Pin input 0 to SCTimer/PWM.
O PDM0_CLK — Clock for PDM interface 0, for digital
microphone.
PIO0_1 A1 A1 207 100 [2] PU; I/O PIO0_1 — General-purpose digital input/output pin.
ZPU; Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI
Z SSEL0 function.
O CAN1_TD — Transmitter output for CAN 1.
I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART
clear-to-send, I2C data I/O, SPI Slave Select 0.
I CT0_CAP0 — Capture input 0 to Timer 0.
I PDM0_DATA — Data for PDM interface 0 (digital
microphone).
PIO0_2/ A7 E9 174 83 [2] PU; Z I/O PIO0_2 — General-purpose digital input/output pin. In
TRST boundary scan mode: TRST (Test Reset).
MISO function.
I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter,
I2C clock, SPI master-in/slave-out data.
O SCT0_OUT0 — SCTimer/PWM output 0.
I SCT0_GPI[2] — Pin input 2 to SCTimer/PWM.
I/O EMC_D[0] — External Memory interface data [0].

Table 4. Pin description …continued

Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_3/ A6 A10 178 85 [2] PU; Z I/O PIO0_3 — General-purpose digital input/output pin. In
TCK boundary scan mode: TCK (Test Clock In).
MOSI function.
I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver,
I2C data I/O, SPI master-out/slave-in data.
O CT0_MAT1 — Match output 1 from Timer 0.
R — Reserved.
PIO0_4/ B6 C8 185 87 [2] PU; Z I/O PIO0_4 — General-purpose digital input/output pin. In
TMS boundary scan mode: TMS (Test Mode Select).
Remark: The state of this pin at Reset in conjunction with
PIO0_5 and PIO0_6 will determine the boot source for the
part or if ISP handler is invoked. See the Boot Process
chapter in UM11060 for more details.
R — Reserved.
O ENET_MDC — Ethernet management data clock.
PIO0_5/ A5 E7 189 89 [2] PU; Z I/O PIO0_5 — General-purpose digital input/output pin.
TDI In boundary scan mode: TDI (Test Data In).
R — Reserved.
I/O ENET_MDIO — Ethernet management data I/O.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_6/ A4 A5 191 90 [2] PU; Z I/O PIO0_6 — General-purpose digital input/output pin. In
TDO boundary scan mode: TDO (Test Data Out).
R — Reserved.
I ENET_RX_DV — Ethernet receive data valid.
PIO0_7 F9 H12 125 61 [2] PU; Z I/O PIO0_7 — General-purpose digital input/output pin.
I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART
request-to-send, I2C clock, SPI slave select 1.
O SD_CLK — SD/MMC clock.
microphone.
I ENET_RX_CLK — Ethernet Receive Clock (MII interface)
or Ethernet Reference Clock (RMII interface).
PIO0_8 E9 H10 133 64 [2] PU; Z I/O PIO0_8 — General-purpose digital input/output pin.
I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.
I/O SD_CMD — SD/MMC card command I/O.
O SWO — Serial Wire Debug trace output.
microphone).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_9 E10 G12 136 65 [2] PU; Z I/O PIO0_9 — General-purpose digital input/output pin.
O SD_POW_EN — SD/MMC card power enable.
R — Reserved.
I/O SCI1_IO — SmartCard Interface 1 data I/O.
PIO0_10/ J1 P2 50 23 [4] PU; Z I/O; PIO0_10/ADC0_0 — General-purpose digital input/output
ADC0_0 AI pin. ADC input channel 0 if the DIGIMODE bit is set to 0 in
the IOCON register for this pin.
I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.
R — Reserved.
O SWO — Serial Wire Debug trace output.
PIO0_11/ K1 L3 51 24 [4] PU; Z I/O; PIO0_11/ADC0_1 — General-purpose digital input/output
I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART
receiver, I2C data I/O, SPI master-out/slave-in data, I2S
data I/O.
I FREQME_GPIO_CLK_A — Frequency Measure pin clock
input A.
R — Reserved.
R — Reserved.
I SWCLK — Serial Wire Debug clock. This is the default
function after booting.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_12/ J2 M3 52 25 [4] PU; Z I/O; PIO0_12/ADC0_2 — General-purpose digital input/output
R — Reserved.
I FREQME_GPIO_CLK_B — Frequency Measure pin clock
input B.
R — Reserved.
I/O SWDIO — Serial Wire Debug I/O. This is the default
function after booting.
PIO0_13 C10 F11 141 67 [3] Z I/O PIO0_13 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C
SDA function.
I UTICK_CAP0 — Micro-tick timer capture input 0.
R — Reserved.
R — Reserved.
I ENET_RXD0 — Ethernet receive data 0.
PIO0_14 D9 E13 144 69 [3] Z I/O PIO0_14 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C
SCL function.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_15/ K2 L4 53 26 [4] PU; Z I/O; PIO0_15/ADC0_3 — General-purpose digital input/output
R — Reserved.
O EMC_WEN — External memory interface Write Enable
(active low).
O ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
PIO0_16/ H3 M4 54 27 [4] PU; Z I/O; PIO0_16/ADC0_4 — General-purpose digital input/output
the IOCON register for this pin.ws
O CLKOUT — Output of the CLKOUT function.
R — Reserved.
R — Reserved.
O EMC_CSN[0] — External memory interface static chip
select 0 (active low).
O ENET_TXD0 — Ethernet transmit data 0.
PIO0_17 B10 E14 146 70 [2] PU; Z I/O PIO0_17 — General-purpose digital input/output pin.
I SD_CARD_DET_N — SD/MMC card detect (active low).
R — Reserved.
O EMC_OEN — External memory interface output enable
(active low)


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_18 C9 C14 150 72 [2] PU; Z I/O PIO0_18 — General-purpose digital input/output pin.
I SD_WR_PRT — SD/MMC write protect.
O SCI1_SCLK — SmartCard Interface 1 clock.
O EMC_A[0] — External memory interface address 0.
PIO0_19 C5 C6 193 91 [2] PU; Z I/O PIO0_19 — General-purpose digital input/output pin.
R — Reserved.
I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART
transmitter, I2C clock, SPI master-in/slave-out data I/O, I2S
word-select/frame.
I/O SCI0_IO — SmartCard Interface 0 data I/O.
data I/O.
PIO0_21 B9 C13 158 77 [2] PU; Z I/O PIO0_21 — General-purpose digital input/output pin.
O SCI0_SCLK — SmartCard Interface 0 clock.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_22 B8 B12 163 80 [2][8] PU; Z I/O PIO0_22 — General-purpose digital input/output pin.
word-select/frame.
R — Reserved.
R — Reserved.
I USB0_VBUS — Monitors the presence of USB0 bus
power.
PIO0_23/ K5 N7 71 35 [4] PU; Z I/O; PIO0_23/ADC0_11 — General-purpose digital input/output
I/O MCLK — MCLK input or output for I2S and/or digital
microphone.
clear-to-send, I2C data I/O, SPI slave select 0.
I/O SPIFI_CSN — SPI Flash Interface chip select (active low).
PIO0_24 J5 M7 76 38 [2] PU; Z I/O PIO0_24 — General-purpose digital input/output pin.
I/O SD_D[0] — SD/MMC data 0.
R — Reserved.
I/O SPIFI_IO0 — Data bit 0 for the SPI Flash Interface.
PIO0_25 J6 K8 83 40 [2] PU; Z I/O PIO0_25 — General-purpose digital input/output pin.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_26 H10 M13 110 56 [2] PU; Z I/O PIO0_26 — General-purpose digital input/output pin.
microphone.
O SPIFI_CLK — Clock output for the SPI Flash Interface.
I USB0_IDVALUE — Indicates to the transceiver whether
connected as an A-device (USB0_ID LOW) or B-device
(USB0_ID HIGH).
PIO0_27 H7 L9 87 42 [2] PU; Z I/O PIO0_27 — General-purpose digital input/output pin.
R — Reserved.
microphone).
PIO0_28 J7 M9 91 44 [2] PU; Z I/O PIO0_28 — General-purpose digital input/output pin.
R — Reserved.
I CT2_CAP3 — Capture 3 input to Timer 2.
O TRACEDATA[3] — Trace data bit 3.
I USB0_OVERCURRENTN — USB0 bus overcurrent
indicator (active low).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO0_29 B7 B13 167 82 [2] PU; Z I/O PIO0_29 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 0
USART RXD function.
R — Reserved.
PIO0_30 A2 A2 200 95 [2] PU; Z I/O PIO0_30 — General-purpose digital input/output pin.
Remark: In ISP mode, this pin is set to the Flexcomm 0
USART TXD function.
R — Reserved.
PIO0_31/ K3 M5 55 28 [4] PU; Z I/O; PIO0_31/ADC0_5 — General-purpose digital input/output
PIO1_0/ J3 N3 56 29 [4] PU; Z I/O; PIO1_0/ADC0_6 — General-purpose digital input/output
O TRACECLK — Trace clock.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_1 J10 K12 109 55 [2] PU; Z I/O PIO1_1/ — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
I/O FC10_MOSI — Flexcomm 10: SPI master-out/slave-in
data.
PIO1_2 G9 L14 117 58 [2] PU; Z I/O PIO1_2 — General-purpose digital input/output pin.
O CAN0_TD — Transmitter output for CAN0.
R — Reserved.
O CT0_MAT3 — Match output 3 from Timer0.
microphone.
I/O FC10_MISO — Flexcomm 10: SPI master-in/slave-out
data.
O USB1_PORTPWRN — USB1 VBUS drive indicator
(Indicates VBUS must be driven).
PIO1_3 F10 J13 120 60 [2] PU; Z I/O PIO1_3 — General-purpose digital input/output pin.
I CAN0_RD — Receiver input for CAN0.
R — Reserved.
R — Reserved.
microphone).
R — Reserved.
I/O FC10_SCK — Flexcomm 10: SPI clock.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
I FREQME_GPIO_CLK_A — Frequency Measure pin clock
input A.
I/O EMC_D[11]) — External Memory interface data [11].
PIO1_5 C2 E4 5 4 [2] PU; Z I/O PIO1_5 — General-purpose digital input/output pin.
R — Reserved.
PIO1_6 F1 G4 30 15 [2] PU; Z I/O PIO1_6 — General-purpose digital input/output pin.
R — Reserved.
PIO1_7 H1 N1 38 18 [2] PU; Z I/O PIO1_7 — General-purpose digital input/output pin.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_8 H5 P8 72 36 [2] PU; Z I/O PIO1_8 — General-purpose digital input/output pin.
R — Reserved.
PIO1_9 K7 K6 78 39 [2] PU; Z I/O PIO1_9 — General-purpose digital input/output pin.
O EMC_CASN — External memory interface column access
strobe (active low).
R — Reserved.
O EMC_RASN — External memory interface row address
strobe (active low).
PIO1_11 B4 B4 198 94 [2][8] PU; Z I/O PIO1_11 — General-purpose digital input/output pin.
interface).
power.
R — Reserved.
O EMC_CLK[0] — External memory interface clock 0.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_12 F8 K9 128 62 [2] PU; Z I/O PIO1_12 — General-purpose digital input/output pin.
O EMC_DYCSN[0] — External Memory interface SDRAM
chip select 0 (active low).
PIO1_13 D10 G10 139 66 [2] PU; Z I/O PIO1_13 — General-purpose digital input/output pin.
data I/O.
O USB0_FRAME — USB0 frame toggle signal.
O EMC_DQM[0] — External memory interface data mask 0.
PIO1_14 A9 C12 160 78 [2] PU; Z I/O PIO1_14 — General-purpose digital input/output pin.
O USB0_LEDN — USB0-configured LED indicator (active
low).
PIO1_15 C7 A11 176 84 [2] PU; Z I/O PIO1_15 — General-purpose digital input/output pin.
O EMC_CKE[0] — External memory interface SDRAM clock
enable 0.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_16 B5 B7 187 88 [2] PU; Z I/O PIO1_16 — General-purpose digital input/output pin.
word-select/frame.
R — Reserved.
R — Reserved.
O EMC_BLSN[0] — External memory interface byte lane
PIO1_18 D2 D1 15 5 [2] PU; Z I/O PIO1_18 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_19 F3 L1 33 16 [2] PU; Z I/O PIO1_19 — General-purpose digital input/output pin.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_20 G2 M1 35 17 [2] PU; Z I/O PIO1_20 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_21 K6 N8 74 37 [2] PU; Z I/O PIO1_21 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_22 K8 P11 89 43 [2] PU; Z I/O PIO1_22 — General-purpose digital input/output pin.
enable 1.
PIO1_23 K10 M10 97 46 [2] PU; Z I/O PIO1_23 — General-purpose digital input/output pin.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_24 G8 N14 111 57 [2] PU; Z I/O PIO1_24 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_25 G10 M12 119 59 [2] PU; Z I/O PIO1_25 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_26 E8 J10 131 63 [2] PU; Z I/O PIO1_26 — General-purpose digital input/output pin.
R — Reserved.
PIO1_27 D8 F10 142 68 [2] PU; Z I/O PIO1_27 — General-purpose digital input/output pin.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO1_28 A10 E12 151 73 [2] PU; Z I/O PIO1_28 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
PIO1_29 A8 C11 165 81 [2][8] PU; Z I/O PIO1_29 — General-purpose digital input/output pin.
data I/O.
PIO1_30 C6 A8 182 86 [2] PU; Z I/O PIO1_30 — General-purpose digital input/output pin.
word-select/frame.
low).
PIO1_31 A3 C5 195 92 [2] PU; Z I/O PIO1_31 — General-purpose digital input/output pin.
microphone.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO2_0/ - P3 57 - [4] PU; Z I/O; PIO2_0/ADC0_7 — General-purpose digital input/output
R — Reserved.
R — Reserved.
O CT1_CAP0 — Capture input 0 to Timer 1.
R — Reserved.
R — Reserved.
PIO2_2 - C3 4 - [2] PU; Z I/O PIO2_2 — General-purpose digital input/output pin.
I ENET_CRS — Ethernet Carrier Sense (MII interface) or
Ethernet
Carrier Sense/Data Valid (RMII interface).
PIO2_3 - B1 7 - [2] PU; Z I/O PIO2_3 — General-purpose digital input/output pin.
O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
PIO2_4 - D3 9 - [2] PU; Z I/O PIO2_4 — General-purpose digital input/output pin.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
O SD_POW_EN — SD/MMC card power enable
PIO2_6 - F3 17 - [2] PU; Z I/O PIO2_6 — General-purpose digital input/output pin.
I ENET_TX_CLK — Ethernet Transmit Clock (MII interface).
PIO2_7 - J2 29 - [2] PU; Z I/O PIO2_7 — General-purpose digital input/output pin.
I ENET_COL — Ethernet Collision detect (MII interface).
I/O SD_D(1) — SD/MMC data 1.
I FREQME_GPIO_CLK_B — Frequency Measure pin clock
input B.
I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
R — Reserved.
PIO2_9 - K2 36 - [2] PU; Z I/O PIO2_9 — General-purpose digital input/output pin.
R — Reserved.
PIO2_10 - P1 39 - [2] PU; Z I/O PIO2_10 — General-purpose digital input/output pin.
I ENET_RX_ER — Ethernet receive error (RMII/MII
interface).
O LCD_PWR — LCD panel power enable.
O SD_VOLT[0] — SD/MMC card regulator voltage control [0].
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO2_12 - M2 45 - [2] PU; Z I/O PIO2_12 — General-purpose digital input/output pin.
O LCD_LE — LCD line end signal.
(USB0_ID HIGH).
R — Reserved.
O LCD_DCLK — LCD panel clock.
R — Reserved.
R — Reserved.
PIO2_14 - L7 77 - [2][8] PU; Z I/O PIO2_14 — General-purpose digital input/output pin.
O LCD_FP — LCD frame pulse (STN). Vertical
synchronization pulse (TFT).
O LCD_AC — LCD STN AC bias drive or TFT data enable
output.
low).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO2_16 - L8 81 - [2][8] PU; Z I/O PIO2_16 — General-purpose digital input/output pin.
O LCD_LP — LCD line synchronization pulse (STN).
Horizontal synchronization pulse (TFT).
I LCD_CLKIN — LCD clock input.
low).
PIO2_18 - N10 90 - [2] PU; Z I/O PIO2_18 — General-purpose digital input/output pin.
O LCD_VD[0] — LCD Data [0].
data I/O.
word-select/frame.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO2_21 - L10 99 - [2] PU; Z I/O PIO2_21 — General-purpose digital input/output pin.
microphone.
R — Reserved.
R — Reserved.
FC10_SSEL1 — Flexcomm 10: SPI Slave Select 1.
R — Reserved.
R — Reserved.
R — Reserved.
I/O FC10_SSEL2 — Flexcomm 10: SPI Slave Select 2.
R — Reserved.
R — Reserved.
R — Reserved.
I/O FC10_SSEL3 — Flexcomm 10: SPI Slave Select 3.
PIO2_25 - J11 121 - [2][8] PU; Z I/O PIO2_25 — General-purpose digital input/output pin.
power.
PIO2_26 - H11 124 - [2] PU; Z I/O PIO2_26 — General-purpose digital input/output pin.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO2_28 - G13 134 - [2] PU; Z I/O PIO2_28 — General-purpose digital input/output pin.
O LCD_VD[10]) — LCD Data [10].
R — Reserved
R — Reserved.
R — Reserved.
microphone.
R — Reserved.
microphone).
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
PIO3_3 - A13 169 - [2] PU; Z I/O PIO3_3 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
chip select 1(active low).
microphone.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
O EMC_CLK[1] — External memory interface clock 1.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
I EMC_FBCK — External memory interface feedback clock.
PIO3_14 - E3 13 - [2] PU; Z I/O PIO3_14 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO3_20 - N2 46 - [2] PU; Z I/O PIO3_20 — General-purpose digital input/output pin.
I SD_CARD_INT_N —
R — Reserved.
O SD_BACKEND_PWR — SD/MMC back-end power supply
for embedded device.
PIO3_22/ - N5 62 - [4] PU; Z I/O; PIO3_22/ADC0_10 — General-purpose digital input/output
PIO3_23 - C2 8 - [3] Z I/O PIO3_23 — General-purpose digital input/output pin.
R — Reserved.
PIO3_24 - E2 16 - [3] Z I/O PIO3_24 — General-purpose digital input/output pin.
power.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
select 1(active low).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.
data I/O.
R — Reserved.
R — Reserved.
R — Reserved.
word-select/frame.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
enable 2.
R — Reserved.
R — Reserved.
R — Reserved.
enable 3.
PIO4_7 - A14 166 - [2][8] PU; Z I/O PIO4_7 — General-purpose digital input/output pin.
R — Reserved.
low).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
PIO4_9 - A12 173 - [2][8] PU; Z I/O PIO4_9 — General-purpose digital input/output pin.
low).
SCT0_GPI3 — Pin input 3 to SCTimer/PWM.
(USB0_ID HIGH).
R — Reserved.
R — Reserved.
interface).
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
PIO4_17 - - 6 - [2] PU; Z I/O PIO4_17 — General-purpose digital input/output pin.
R — Reserved.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
O SD_POW_EN — SD/MMC card power enable.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
I SD_CARD_INT_N — Card interrupt line.
R — Reserved.
R — Reserved.
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
interface).
R — Reserved.
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
R — Reserved.
I ENET_RX_ER — Ethernet receive error (RMII/MII
interface).
R — Reserved.
I ENET_TX_CLK — Ethernet Transmit Clock (MII interface).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
R — Reserved.
I ENET_CRS — Ethernet Carrier Sense (MII interface) or
Ethernet
Carrier Sense/Data Valid (RMII interface).
R — Reserved.
I ENET_COL — Ethernet Collision detect (MII interface).
R — Reserved.


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
R — Reserved.
O SD_BACKEND_PWR — SD/MMC back-end power supply
for embedded device.
R — Reserved.
microphone.
microphone).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
microphone.
microphone.
microphone).
R — Reserved.
USB1_AVSSC D1 F2 20 6 USB1 analog 3.3 V ground.
USB1_REXT B1 F1 21 7 USB1 analog signal for reference resistor, 12.4 k +/-1%
USB1_ID C1 G1 22 8 Indicates to the transceiver whether connected as an
A-device (USB1_ID LOW) or B-device (USB1_ID HIGH).


Symbol Description
100-pin, TFBGA
180-pin, TFBGA
Reset state[1] [9]

208-pin, LQFP
100-pin, LQFP
Type
USB1_VBUS D3 G2 23 9 [6][8] I/O VBUS pin (power on USB cable). 5 V tolerant when
USB1_AVDD3V3 and USB1_AVDDTX3V3 = 0 V.
USB1_AVDDC3V3 E1 G3 24 10 USB1 analog 3.3 V supply.
USB1_AVDDTX3V3 E2 H1 25 11 USB1 analog 3.3 V supply for line drivers.
USB1_DP F2 H3 27 13 [6] I/O USB1 bidirectional D+ line.
USB1_DM E3 H2 26 12 [6] I/O USB1 bidirectional D- line.
USB1_AVSSTX3V3 G1 J1 28 14 USB1 analog ground for line drivers.
USB0_DP B3 E5 204 97 [6] I/O USB0 bidirectional D+ line.
USB0_DM B2 D5 205 98 [6] I/O USB0 bidirectional D- line.
RESETN J8 N13 101 48 [5] External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and the boot code to execute. Wakes up the part
from deep power-down mode.
VDD D5; E6; 1; 1; - - Single 1.71 V to 3.6 V power supply powers internal digital
D7; E8; 48; 21; functions and I/Os.
E4; F5; 65; 33;
E6; G5; 104; 50;
F5; J12; 108; 54;
F7; L6; 156; 75;
G4; L11 157; 76;
G6 206 99
VSS D4; B3; 2; 2; - - Ground.
D6; D7; 49; 22;
E5; D8; 66; 34;
E7; E11; 103; 49;
F4; H5; 107; 53;
F6; J5; 148; 71;
G5; K7 162; 79;
G7 201 96
VDDA J4 N6 64 32 - - Analog supply voltage.
VREFN - N4 59 - - - ADC negative reference voltage. On TFBGA100 and
LQFP100 packages, the ADC negative reference voltage is
internally tied to the VSSA pin.
VREFP K4 P6 63 31 - - ADC positive reference voltage.
VSSA H4 L5 60 30 - - Analog ground. On On TFBGA100 and LQFP100
packages, the ADC negative reference voltage is internally
tied to the VSSA pin.
XTALIN H2 K4 41 20 [7] - - Main oscillator input.
XTALOUT G3 J4 40 19 [7] - - Main oscillator output.
VBAT K9 N11 94 45 - - Battery supply voltage. If no battery is used, tie VBAT to
VDD or to ground.
RTCXIN J9 L12 105 51 - - RTC oscillator input.
RTCXOUT H9 K11 106 52 - - RTC oscillator output.

[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). Z = high impedance; pull-up or pull-down disabled, AI = analog
input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the
different power modes, see Section 6.2.2 “Pin states in different power modes”. For termination on unused pins, see Section 6.2.1
“Termination of unused pins”.
[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength. See Figure 45. Pulse width of spikes or glitches suppressed by input
filter is from 3 ns to 16 ns (simulated value).
[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode
Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not
disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
[4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to
20 ns (simulated value)
[6] 5 V tolerant transparent analog pad.
[7] The oscillator input pin (XTALIN) cannot be driven by an external clock. Must connect a crystal between XTALIN and XTALOUT.
[8] VBUS must be connected to supply voltage when using the USB peripheral.
[9] For initial device revision 0A (Boot ROM version 21.0), PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). For
future device revision 1B (Boot ROM version 21.1), Z = high impedance; pull-up or pull-down disabled. See the Errata sheet
LPC540xx/LPC54S0xx (IOCON.1) for more details. For future device revision 1B (Boot ROM version 21.1), GPIO pins PIO0_12,
PIO0_11, PIO0_2, PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON
register) and will be floating by default. If unused, it is recommended to externally terminate this pins to prevent leakage.
6.2.1 Termination of unused pins

Table 5 shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software to
minimize the overall power consumption of the part.
Unused pins with GPIO function should be configured as outputs set to LOW with their
internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the
GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0
to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 5. Termination of unused pins

Pin Default Recommended termination of unused pins
state[1][2]
RESET I; PU The RESET pin can be left unconnected if the application does not use it.
all PIOn_m (not open-drain) I; PU; Z Can be left unconnected if driven LOW and configured as GPIO output with pull-up
disabled by software.
PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by
software.
RTCXIN - Connect to ground. When grounded, the RTC oscillator is disabled.
RTCXOUT - Can be left unconnected.
XTALIN - Connect to ground. When grounded, the RTC oscillator is disabled.
XTALOUT - Can be left unconnected.
VREFP - Tie to VDD.
VREFN - Tie to VSS.
VDDA - Tie to VDD.
VSSA - Tie to VSS.

Table 5. Termination of unused pins

Pin Default Recommended termination of unused pins
state[1][2]
VBAT - Tie to VDD.
USBn_DP F Can be left unconnected. If USB interface is not used, pin can be left unconnected
except in deep power-down mode where it must be externally pulled low. When the
USB PHY is disabled, the pins are floating.
USBn_DM F Can be left unconnected. If USB interface is not used, pin can be left unconnected
except in deep power-down mode where it must be externally pulled low. When the
USB PHY is disabled, the pins are floating.
USB1_AVSCC F Tie to VSS.
USB1_VBUS F Tie to VDD.
USB1_AVDDC3V3 F Tie to VDD.
USB1_AVDDTX3V3 F Tie to VDD.
USB1_AVSSTX3V3 F Tie to VSS.
USB1_ID F Can be left unconnected. If USB interface is not used, pin can be left unconnected.
[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating

6.2.2 Pin states in different power modes

Table 6. Pin states in different power modes
Pin Active Sleep Deep-sleep Deep
power-down[3]
PIOn_m pins (not I2C) As configured in the IOCON[1]. Default: internal pull-up enabled Floating
or high Z [2].
PIO0_13 to PIO0_14 (open-drain As configured in the IOCON[1]. Floating
I2C-bus pins)
PIO3_23 to PIO3_24 (open-drain As configured in the IOCON[1]. Floating
I2C-bus pins)
RESET Reset function enabled. Default: input, internal pull-up enabled.
Reset function disabled.
[1] Default and programmed pin states are retained in sleep and deep-sleep.
[3] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.

7. Functional description
7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses allow for concurrent code and data
accesses from different slave ports.
The LPC540xx/LPC54S0xx uses a multi-layer AHB matrix to connect the ARM Cortex-M4
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slave ports of the matrix to be
accessed simultaneously by different bus masters.
7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M4 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and
divide, interruptable/continuable multiple load and store instructions, automatic state save
and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point
and floating-point data formats, and floating-point constant instructions.
The FPU provides floating-point computation functionality that is compliant with the
ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to
as the IEEE 754 standard.
7.4 Memory Protection Unit (MPU)

The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve
the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.

7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4

The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• Supports up to 54 vectored interrupts.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.5.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.6 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a
dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the
Cortex-M4 core clock.
7.7 On-chip static RAM

The LPC540xx/LPC54S0xx support 360 kB SRAM with separate bus master access for
higher throughput and individual power control for low-power operation.
7.8 On-chip ROM

The 64 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-Application Programming (IAP) and In-System Programming (ISP).

• ROM-based USB drivers (HID, CDC, MSC, and DFU).
• Supports serial interface booting (UART, I2C, SPI) from an application processor,
automated booting from NOR flash (SPI on device revision 1B, quad SPIFI,
8/16/32-bit external parallel flash), and USB booting (full-speed, high speed).
• Execute in place (XIP) from SPIFI NOR flash (in quad, dual SPIFI mode or single-bit
SPI mode), and parallel NOR flash.
• FRO API for selecting FRO output frequency.
• OTP API for programming OTP memory.
• Random Number Generator (RNG) API.
• RSA API calls (LPC54S0xx only).
• Secure Boot features on LPC54S0xx devices:
– Supports boot image authentication using RSASSA-PKCS1-v1_5 signature
verification with 2048-bit public keys (2048-bit modulus, 32-bit exponent).

– Supports Root of Trust (RoT) establishment by comparing the SHA-256 hash

digest of the RoT public key with OTP memory contents.
– Supports secure anti-rollback of images through revocation of image key
certificate. Supports up to 8 revocations through OTP fuses.
– Supports boot of AES-GCM encrypted images with a 128-bit symmetric key stored
in OTP memory or a 256-bit symmetric key stored using on-chip SRAM PUF.
– Secure Authentication Only Boot. Enforce booting of RSA-2048 signed images
only.
– Encrypted Image Boot. Enforce booting of AES-GCM encrypted images only.
– Enhanced Image Boot. Enforce booting of encrypted then signed images only.
– Supports Device Identifier Composition Engine (DICE) Specification (version
Family 2.0, Level 00 Revision 69) specified by Trusted Computing Group.
7.9 Memory mapping

The LPC540xx/LPC54S0xx incorporates several distinct memory regions. The APB
peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.Each
peripheral is allocated 4 kB of space simplifying the address decoding. The registers
incorporated into the CPU, such as NVIC, SysTick, and sleep mode control, are located
on the private peripheral bus.
The ARM Cortex-M4 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC540xx/LPC54S0xx.
Table 7. Memory usage and details

Address range General Use Address range details and description
0x0000 0000 to 0x1FFF FFFF SRAMX 0x0000 0000 - 0x0002 FFFF I&D SRAM bank (192 kB).
Boot ROM 0x0300 0000 - 0x0300 FFFF Boot ROM with API services in a 64 kB
space.
SPI Flash 0x1000 0000 - 0x17FF FFFF SPIFI memory mapped access space
Interface (SPIFI) (128 MB).
0x2000 0000 to 0x3FFF FFFF Main SRAM 0x2000 0000 - 0x2002 7FFF SRAM0, SRAM1, SRAM2, SRAM3
Banks banks (Total 160 kB).
SRAM bit band 0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing
alias addressing (32 MB).
SRAM Bank 0x4010 0000 0x4010 2000 USB SRAM (8 kB).
0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral
blocks of 4 kB each (128 kB).
0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral
blocks of 4 kB each (128 kB).
0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to
32 peripheral blocks of 4 kB each
(128 kB).
AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 kB).
Peripheral bit 0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing
band alias (32 MB).
addressing

Table 7. Memory usage and details …continued

Address range General Use Address range details and description
0x8000 0000 to 0xDFFF FFFF Off-chip Memory Four static memory chip selects:
via the External 0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64
Memory MB)[1]
Controller
0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64
MB)[2]
0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64
MB).
0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64
MB).
Four dynamic memory chip selects:
0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to
256 MB).
0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to
256 MB).
0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to
256 MB).
0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to
256 MB).
0xE000 0000 to 0xE00F FFFF Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 related functions, includes
Private the NVIC and System Tick Timer.
Peripheral Bus
[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See the
EMCSYSCTRL register bit 0 in the LPC540xx/LPC54S0xx user manual.
[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See the
EMCSYSCTRL register bit 0 in the LPC540xx/LPC54S0xx user manual.
Figure 9 shows the overall map of the entire address space from the user program
viewpoint following reset.

Memory space
AHB peripherals
0xFFFF FFFF
(reserved)
0xE010 0000 0x4010 BFFF
private peripheral bus (reserved)
0xE000 0000 0x4010 2000
(EMC) USB SRAM (8 kB)
0x4010 0000
0x8000 0000 (reserved)
(reserved) 0x400A 5000
0x4400 0000 SHA registers
peripheral 0x400A 4000
bit-band addressing HS USB host registers
0x400A 3000
0x4200 0000 FS USB host registers
(reserved) 0x400A 2000
0x4010 C000 AES256
AHB 0x400A 1000
peripheral ADC
0x4008 0000 0x400A 0000
Flexcomm 10
(reserved) 0x4009 F000
0x4006 0000 CAN 1
Asynchronous 0x4009 E000
APB peripherals CAN 0
0x4004 0000 0x4009 D000
see APB (reserved)
APB peripherals on memory 0x4009 C000
APB bridge 1 SDIO
0x4002 0000 map figure 0x4009 B000
APB peripherals on Flexcomm 9
0x4009 A000
APB bridge 0 Flexcomm 8
0x4000 0000 0x4009 9000
(reserved) Flexcomm 7
0x2400 0000 0x4009 8000
SRAM bit-band Flexcomm 6
0x4009 7000
addressing Flexcomm 5
0x2200 0000 0x4009 6000
(reserved) CRC engine
0x4009 5000
0x2002 8000 HS USB device
SRAM3 0x4009 4000
Ethernet
(up to 32 kB) 0x4009 2000
0x2002 0000 (reserved)
SRAM2 0x4009 1000
(up to 32 kB) DMIC interface
0x2001 8000 0x4009 0000
SRAM1 High Speed GPIO
0x4008 C000
(up to 32 kB) (reserved)
0x2001 0000 0x4008 B000
SRAM0 Flexcomm 4
(up to 64 kB) 0x4008 A000
0x2000 0000 Flexcomm 3
(reserved) 0x4008 9000
Flexcomm 2
0x1800 0000 0x4008 8000
SPIFI Flash Interface Flexcomm 1
memory mapped space 0x4008 7000
Flexcomm 0
0x1000 0000 0x4008 6000
(reserved) SC Timer / PWM
0x0301 0000 0x4008 5000
Boot ROM FS USB device registers
0x4008 4000
0x0300 0000 LCD registers
(reserved) 0x4008 3000
DMA registers
0x0003 0000 0x4008 2000
SRAMX (192 kB) EMC registers
0x4008 1000
0x0000 0000 SPIFI registers
0x4008 0000
0x0000 00C0
active interrupt vectors
0x0000 0000
aaa-030340
The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.
Fig 9. LPC540xx/LPC54S0xx Memory mapping

APB bridge 1
APB bridge 0 0x4003 FFFF
31-28 (reserved)
0x4003 C000
0x4001 FFFF 27 PUF
31-22 (reserved) 0x4003 B000
0x4001 6000 26 RNG
21 OTP controller 0x4003 A000
0x4001 5000 25-24 (reserved)
20-15 (reserved) 0x4003 8000
0x4001 F000 23 Smart card 1
14 Micro-Tick 0x4003 7000
0x4000 E000 22 Smart card 0
13 MRT 0x4003 6000
0x4000 D000 21-14 (reserved)
0x4002 E000
12 WDT 13 RIT
0x4000 C000 0x4002 D000
11-10 (reserved) 12 RTC
0x4000 A000 0x4002 C000
9 CTIMER1 11-9 (reserved)
0x4000 9000 0x4002 9000
8 CTIMER0 8 CTIMER2
0x4000 8000 0x4002 8000
7 (reserved) 7-0 (reserved)
0x4000 7000 0x4002 0000
6 (reserved)
0x4000 6000
5 Input muxes
0x4000 5000
4 Pin Interrupts (PINT)
0x4000 4000 Asynchronous APB bridge
3 GINT1
0x4000 3000 0x4005 FFFF
2 GINT0 31-10 (reserved)
0x4000 2000 0x4004 A000
1 IOCON 9 CTIMER4
0x4000 1000 0x4004 9000
0 Syscon 8 CTIMER3
0x4000 0000 0x4004 8000
7-1 (reserved)
0x4004 1000
0 Asynch. Syscon
0x4004 0000
aaa-030341
Fig 10. LPC540xx/LPC54S0xx APB Memory map
7.10 One-Time Programmable (OTP) memory

The OTP memory contains four memory banks of 128 bits each. The first memory bank
(OTP Bank 0) is reserved. The other three OTP banks are programmable. In LPC540xx
devices, OTP banks 1 and 2 are available for storing general purpose data. In LPC54S0xx
devices, OTP banks 1 and 2 are used for storing the AES keys. OTP bank 3 is used for
customer programmable device configuration data.
7.10.1 Features
• The OTP memory stores user settings in bank 3, register 0 to configure:
– ISP and boot source modes
– Secure boot
– SPIFI boot delay
– Customer definable bits
• Root of Trust (RoT) hash digest for secure authenticated boot (OTP Banks 1, 2).
• Scrambled 128-bit AES key for secure encrypted boot (OTP Bank 2).
• USB Vendor and Product IDs (OTP Bank 2).
• Boot ROM API support for programming the OTP memory provided.
Remark: OTP programming requires a supply voltage of at least 3.3 V. To use the OTP
API, the main system clock must be running from the 12 MHz clock.

7.11 System control
7.11.1 Clock sources

The LPC540xx/LPC54S0xx supports one external and two internal clock sources:
• Free Running Oscillator (FRO).

• Watchdog oscillator (WDOSC).
• Crystal oscillator.
7.11.1.1 Free Running Oscillator (FRO)
The FRO 12 MHz oscillator provides the default clock at reset and provides a clean
system clock shortly after the supply pins reach operating voltage.
• 12 MHz internal FRO oscillator, factory trimmed for accuracy, that can optionally be
used as a system clock as well as other purposes.
• Selectable 48 MHz or 96 MHz FRO oscillator, factory trimmed for accuracy, that can
optionally be used as a system clock as well as other purposes.
7.11.1.2 Watchdog oscillator (WDOSC)

The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to
provide a clock to the WWDT and to the entire chip. The low-power watchdog oscillator
provides a selectable frequency in the range of 6 kHz to 1.5 MHz. The accuracy of this
clock is limited to  40% over temperature, voltage, and silicon processing variations.
7.11.1.3 Crystal oscillator

The LPC540xx/LPC54S0xx include four independent oscillators. These are the main
oscillator, the FRO, the watchdog oscillator, and the RTC oscillator.
Following reset, the LPC540xx/LPC54S0xx will operate from the Internal FRO until
switched by software. This allows systems to operate without any external crystal and the
boot loader code to operate at a known frequency. See Figure 11 and Figure 12 for an
overview of the LPC540xx/LPC54S0xx clock generation.
7.11.2 System PLL (PLL0)

The system PLL accepts an input clock frequency in the range of 32.768 kHz to 25 MHz.
The input frequency is multiplied up to a high frequency with a Current Controlled
Oscillator (CCO).
The PLL can be enabled or disabled by software.
7.11.3 USB PLL (PLL1)

The USB PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO).

7.11.4 Audio PLL (PLL2)

The audio PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO).

7.11.5 Clock Generation
00 to CPU, AHB bus,

“none”
01 CPU CLOCK Sync APB
pll_clk
fro_12m 10 DIVIDER
00 32k_clk (1) main_clk
clk_in 11 EMC ClOCK to EMC
01
wdt_clk AHBCLKDIV DIVIDER (function
10 Main clock select B clock)
fro_hf
11 (1) MAINCLKSELB[1:0] fro_hf
000 EMCCLKDIV
pll_clk
001
Main clock select A usb_pll_clk ADC CLOCK to ADC
010
MAINCLKSELA[1:0] audio_pll_clk DIVIDER
011
“none”
fro_12m 111
000 ADCCLKDIV
clk_in
001
32k_clk ADC clock select
011 SYSTEM PLL pll_clk ADCCLKSEL[2:0]
“none”
111
System PLL fro_hf

000 to USB0
PLL clock select settings pll_clk
SYSPLLCLKSEL[2:0] 001 USB0 CLOCK (FS USB)
usb_pll_clk
010 DIVIDER
“none”
111
xtalin Crystal clk_in USB0CLKDIV
xtalout oscillator USB0 clock select
USB0CLKSEL[2:0]
Range select
SYSOSCCTRL[1:0]
main_clk
000
pll_clk
001 USB1 CLOCK to USB1 PHY
usb_pll_clk
fro_hf FRO Clock fro_hf_div 010 DIVIDER
“none”
Divider 111
USB1CLKDIV
FROHFCLKDIV USB1 clock select
USB1CLKSEL[2:0]
clk_in usb_pll_clk fro_12

USB PLL 000 to DMIC
fro_hf_div subsystem
001 DMIC CLOCK
audio_pll_clk DIVIDER
USB PLL 010
mclk_in
settings 011
main_clk DMICCLKDIV
100
fro_12m wdt_in
000 101
clk_in “none”
audio_pll_clk 111
001 Audio PLL
“none” 111
DMIC clock select
DMICCLKSEL[2:0]
AUDIO PLL Settings
Audio clock select
AUDPLLCKSEL[2:0] fro_hf_div
000 to MCLK pin
audio_pll_clk MCLK (output)
001
main_clk “none” DIVIDER
00 111
fro_12m
01 to Async APB
audio_pll_clk MCLKDIV
10 MCLK clock select
fc6_fclk (1) MCLKCLKSEL[1:0]
11
main_clk
APB clock select B 000
pll_clk
ASYNCAPBCLKSELA[1:0] 001 to SDIO
usb_pll_clk SDIO CLOCK (function clock)
010
fro_hf DIVIDER
011
audio_pll_clk
100
“none” SDIOCLKDIV
111
(1): synchronized multiplexer,
see register descriptions for details. SDIO clock select
SDIOCLKSEL[2:0] aaa-029067
Fig 11. LPC540xx/LPC54S0xx clock generation

(1 per Flexcomm)
main_clk
000 fro_12m
pll_clk 000 fcn_fclk
001 fro_hf_div
fro_12m 001 (function clock
010 audio_pll_clk
fro_hf 010 of Flexcomm[0-9])
011 mclk_in
“none” 011 (up to 11 Flexcomm
111 FRG CLOCK frg_clk
DIVIDER 100 Interfaces on these
“none” devices)
111 to MCAN0
main_clk function clock
MCAN0 clock
FRG clock select FRGCTRL[15:0]
FCLKSEL[0-9] divider
FRGCLKSEL[2:0]
32k_clk to CLK32K of all Flexcomms (fc0-fc9) CAN0CLKDIV
to MCAN1
main_clk function clock
MCAN1 clock
main_clk divider
000 fcn_fclk
pll_clk
001 (function clock
usb_pll_clk CAN1CLKDIV
010 of Flexcomm10)
fro_hf
011
audio_pll_clk to Smartcard0
100 main_clk function clock
“none” Smartcard0
111
clock divider
FCLKSEL10
SC0CLKDIV
main_clk to Smartcard1
000 to SCTimer/PWM main_clk function clock
pll_clk Smartcard1
001 SCTimer/PWM input clock 7 clock divider
fro_hf
010 Clock Divider
audio_pll_clk
011 SC1CLKDIV
“none”
111 SCTCLKDIV
to ARM Trace
SCT clock select main_clk function clock
ARM Trace
SCTCLKSEL[2:0]
clock divider
ARMTRACECLKDIV
main_clk
00 to LCD
lcdclkin
01 LCD CLOCK (function clock)
fro_hf
10 DIVIDER
“none” main_clk
11 000
pll_clk
LCDCLKDIV 001 to SPIFI
usb_pll_clk
LCD clock select 010 SPIFI CLOCK (function clock)
fro_hf
LCDCLKSEL[1:0] 011 DIVIDER
audio_pll_clk
100
“none”
111 SPIFI CLKDIV
main_clk SPIFI clock select

000
clk_in SPIFICLKSEL[2:0]
001
wdt_clk
010
fro_hf to Cortex-M4
011 CLKOUT CLKOUT main_clk Systick Clock
pll_clk 000 System Tick
100 DIVIDER Divider wdt_clk
usb_pll_clk 001 Timer
101 32k_clk
audio_pll_clk 010
110 CLKOUTDIV SYSTICKCLKDIV fro_12
32k_clk 011
111 “none”
111
CLKOUT select Systic clock select

CLKOUTSEL[2:0] SYSTICKCLKSEL[2:0]
aaa-029070
Fig 12. LPC540xx/LPC54S0xx clock generation (continued)

7.11.6 Brownout detection

The LPC540xx/LPC54S0xx includes a monitor for the voltage level on the VDD pin. If this
voltage falls below a fixed level, the BOD sets a flag that can be polled or cause an
interrupt. In addition, a separate threshold level can be selected to cause chip reset.
7.11.7 Safety
The LPC540xx/LPC54S0xx includes a Windowed WatchDog Timer (WWDT), which can
be enabled by software after reset. Once enabled, the WWDT remains locked and cannot
be modified in any way until a reset occurs.
7.12 Power control

The LPC540xx/LPC54S0xx support a variety of power control features. In Active mode,
when the chip is running, power and clocks to selected peripherals can be adjusted for
power consumption. In addition, there are three special modes of processor power
reduction with different peripherals running: sleep mode, deep-sleep mode, and deep
power-down mode that can be activated using the power API library from the SDK
software package.
7.12.1 Sleep mode

In sleep mode, the system clock to the CPU is stopped and execution of instructions is
suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be
clocked can continue operation during Sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and related controllers, internal buses, and unused
peripherals. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
7.12.2 Deep-sleep mode

In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down by default but can be selected to keep running through
the power API if needed as wake-up sources. The main clock and all peripheral clocks are
disabled by default. The FRO is disabled.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB0,
USB1, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left
running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be
left running.In some cases, DMA can operate in deep-sleep mode.
7.12.3 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power
domain and the RESET pin. The LPC540xx/LPC54S0xx can wake up from deep
power-down mode via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC

control register generates an RTC wake-up interrupt request, which can wake up the part.
During deep power-down mode, the contents of the SRAM and registers are not retained.
All functional pins are tri-stated in deep power-down mode.
Table 8 shows the peripheral configuration in reduced power modes.
Table 8. Peripheral configuration in reduced power modes

Peripheral Reduced power mode
Sleep Deep-sleep Deep power-down
FRO Software configured Software configured Off
BOD Software configured Software configured Off
PLL Software configured Off Off
Watchdog osc and Software configured Software configured Off
WWDT
Micro-tick Timer Software configured Software configured Off
DMA Active Configurable some for operations. Off
USART Software configured Off; but can create a wake-up interrupt in synchronous Off
slave mode or 32 kHz clock mode
SPI Software configured Off; but can create a wake-up interrupt in slave mode Off
I2C Software configured Off; but can create a wake-up interrupt in slave mode Off
USB0 Software configured Software configured Off
USB1 Software configured Software configured Off
Ethernet Software configured Off Off
DMIC Software configured Software configured Off
Other digital peripherals Software configured Off Off
RTC oscillator Software configured Software configured Software configured

Table 9 shows wake-up sources for reduced power modes.
Table 9. Wake-up sources for reduced power modes

Power mode Wake-up source Conditions
Sleep Any interrupt Enable interrupt in NVIC.
HWWAKE Certain Flexcomm Interface and DMIC subsystem activity.
Deep-sleep Pin interrupts Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers.
BOD interrupt • Enable interrupt in NVIC and STARTER0 registers.
• Enable interrupt in BODCTRL register.
• Configure the BOD to keep running in this mode with the power API.
BOD reset Enable reset in BODCTRL register.
Watchdog interrupt • Enable the watchdog oscillator in the PDRUNCFG0 register.
• Enable the watchdog interrupt in NVIC and STARTER0 registers.
• Enable the watchdog in the WWDT MOD register and feed.
• Enable interrupt in WWDT MOD register.
• Configure the WDTOSC to keep running in this mode with the power API.
Watchdog reset • Enable the watchdog oscillator in the PDRUNCFG0 register.
• Enable the watchdog and watchdog reset in the WWDT MOD register and feed.
Reset pin Always available.
RTC 1 Hz alarm timer • Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.
• Enable the RTC bus clock in the AHBCLKCTRL0 register.
• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.
• Enable the RTCALARM interrupt in the STARTER0 register.
RTC 1 kHz timer • Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL
time-out and alarm register.
• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.
• Enable the RTC wake-up interrupt in the STARTER0 register.
Micro-tick timer • Enable the watchdog oscillator in the PDRUNCFG0 register.
(intended for ultra-low • Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 register.
power wake-up from
deep-sleep mode
• Start the Micro-tick timer by writing UTICK CTRL register.
• Enable the Micro-tick timer interrupt in the STARTER0 register.
I2C interrupt Interrupt from I2C in slave mode.
SPI interrupt Interrupt from SPI in slave mode.
USART interrupt Interrupt from USART in slave or 32 kHz mode.
USB0 need clock Interrupt from USB0 when activity is detected that requires a clock.
interrupt
USB1 need clock Interrupt from USB1 when activity is detected that requires a clock.
interrupt
Ethernet interrupt Interrupt from ethernet.
DMA interrupt Interrupt from DMA.
HWWAKE Certain Flexcomm Interface and DMIC subsystem activity.

Table 9. Wake-up sources for reduced power modes

Power mode Wake-up source Conditions
Deep RTC 1 Hz alarm timer • Enable the RTC 1 Hz oscillator in the RTC CTRL register.
power-down • Start RTC alarm timer by writing a time-out value to the RTC COUNT register.
RTC 1 kHz timer • Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTCO-
time-out and alarm SCCTRL register.
• Enable the RTC bus clock in the AHBCLKCTRL0 register.
• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.
Reset pin Always available.
7.13 General Purpose I/O (GPIO)

The LPC540xx/LPC54S0xx provides six GPIO ports with a total of up to 171 GPIO pins.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The current level
of a port pin can be read back no matter what peripheral is selected for that pin.
7.13.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt
request.
• One GPIO group interrupt can be triggered by a combination of any pin or pins.
7.14 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight
external interrupts connected to the NVIC. The pattern match engine can be used in
conjunction with software to create complex state machines based on pin inputs. Any
digital pin, independent of the function selected through the switch matrix can be
configured through the SYSCON block as an input to the pin interrupt or pattern match
engine. The registers that control the pin interrupt or pattern match engine are located on
the I/O+ bus for fast single-cycle access.

7.14.1 Features
• Pin interrupts:
– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as
edge-sensitive or level-sensitive interrupt requests. Each request creates a
separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.
• Pattern match engine:

– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute
to a boolean expression. The boolean expression consists of specified levels
and/or transitions on various combinations of these pins.
– Each bit slice minterm (product term) comprising of the specified boolean
expression can generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can also be programmed to generate an RXEV
notification to the CPU. The RXEV signal can be connected to a pin.
– Pattern match can be used in conjunction with software to create complex state
machines based on pin inputs.
– Pattern match engine facilities wake-up only from active and sleep modes.
7.15 Serial peripherals
7.15.1 Full-speed USB Host/Device interface (USB0)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
7.15.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory. The serial
interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Features
• Supports 10 physical (5 logical) endpoints including two control endpoints.

• Single and double-buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
• Supports wake-up from reduced power mode on USB activity and remote wake-up.
• Supports SoftConnect.
• Link Power Management (LPM) supported.

7.15.1.2 USB0 host controller

The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the Open Host Controller Interface (OHCI) specification.
Features
• OHCI compliant.
• Two downstream ports.
7.15.2 High-speed USB Host/Device interface (USB1)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
7.15.2.1 USB1 device controller

The device controller enables 480 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory. The serial
interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Features
• Fully compliant with USB 2.0 Specification (high speed).

• Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• While USB is in the Suspend mode, the LPC540xx/LPC54S0xx can enter one of the
reduced power modes and wake up on USB activity.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.15.2.2 USB1 host controller
The host controller enables high speed data exchange with USB devices attached to the
bus. It consists of register interface and serial interface engine. The register interface
complies with the Enhanced Host Controller Interface (EHCI) specification.
Features
• EHCI compliant.
• Two downstream ports.
• Supports per-port power switching.

7.15.3 Ethernet AVB

The Ethernet block enables a host to transmit and receive data over Ethernet in
compliance with the IEEE 802.3-2008 standard. The Ethernet interface contains a full
featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to
provide optimized performance through the use of DMA hardware acceleration.
7.15.3.1 Features
• 10/100 Mbit/s
• DMA support
• Power management remote wake-up frame and magic packet detection
• Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Supports IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic.
– Software support for AVB feature is available from NXP Professional Services. See
nxp.com for more details.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.
• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE
1588-2008 v2).
7.15.4 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost serial flash memories to be connected to the
LPC540xx/LPC54S0xx microcontroller with little performance penalty compared to
parallel flash devices with higher pin count.
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Simple sequences of commands handle erasure and
programming.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.15.4.1 Features
• Interfaces to serial flash memory in the main memory map.

• Supports classic and 4-bit bidirectional serial protocols.
• Half-duplex protocol compatible with various vendors and devices.
• Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.

• Supports DMA access.

• Provides XIP (execute in place) feature to execute code directly from serial flash.
7.15.5 CAN Flexible Data (CAN FD) interface

The LPC540xx/LPC54S0xx contains two CAN FD interfaces, CAN FD 1 and CAN FD 2.
7.15.5.1 Features
• Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1.
• CAN FD with up to 64 data bytes supported.
• CAN Error Logging.
• AUTOSAR support.
• SAE J1939 support.
• Improved acceptance filtering.
7.15.6 DMIC subsystem
7.15.6.1 Features
• Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2
buses.
• Flexible decimation.
• 16 entry FIFO for each channel.
• DC blocking or unaltered DC bias can be selected.
• Data can be transferred using DMA from deep-sleep mode without waking up the
CPU, then automatically returning to deep-sleep mode.
• Data can be streamed directly to I2S on Flexcomm Interface 7.
7.15.7 Smart card interface
7.15.7.1 Features
• Two DMA supported ISO 7816 Smart Card Interfaces.

• Both asynchronous protocols, T = 0 and T = 1 are supported.
7.15.8 Flexcomm Interface serial communication
7.15.8.1 Features
• USART with asynchronous operation or synchronous master or slave operation.

• SPI master or slave, with up to 4 slave selects.
• I2C, including separate master, slave, and monitor functions.
• Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7.
• Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C
function does not use the FIFO.

7.15.8.2 SPI serial I/O controller
Features
• Maximum data rates of 48 Mbit/s in master mode and 14 Mbit/s in slave mode for SPI
functions. (Flexcomm Interface 0-9).
• Maximum data rates of 50 Mbit/s in master mode and 50 Mbit/s in slave mode for SPI
functions (Flexcomm Interface10).
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or
DMA set-up.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• Four Slave Select input/outputs with selectable polarity and flexible usage.
• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
7.15.8.3 I2C-bus interface

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and
can be controlled by more than one bus master connected to it.
Features
• All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to
1 Mbit/s.
• All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C-bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Activity on the I2C in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.

7.15.8.4 USART
Features
• Maximum bit rates of 6.25 Mbit/s in asynchronous mode.

• The maximum supported bit rate for USART master synchronous mode is 24 Mbit/s,
and the maximum supported bit rate for USART slave synchronous mode is
12.5 Mbit/s.
• 7, 8, or 9 data bits and 1 or 2 stop bits.
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare.
• RS-485 transceiver output enable.
• Autobaud mode for automatic baud rate detection
• Parity generation and checking: odd, even, or none.
• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
• One transmit and one receive data buffer.
• RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
• Received data and status can optionally be read from a single register
• Break generation and detection.
• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
• Built-in Baud Rate Generator with auto-baud function.
• A fractional rate divider is shared among all USARTs.
• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Loopback mode for testing of data and flow control.
• In synchronous slave mode, wakes up the part from deep-sleep mode.
• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz
RTC oscillator as the UART clock. This mode can be used while the device is in
deep-sleep mode and can wake-up the device when a character is received.
• USART transmit and receive functions work with the system DMA controller.
7.15.8.5 I2S-bus interface
The I2S bus provides a standard communication interface for streaming data transfer
applications such as digital audio or data collection. The I2S bus specification defines a
3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,
providing single or dual (mono or stereo) audio data transfer as well as other
configurations. In the LPC540xx/LPC54S0xx, the I2S function is included in Flexcomm
Interface 6 and Flexcomm Interface 7. Each of the Flexcomm Interface implements four
I2S channel pairs.

The I2S interface within one Flexcomm Interface provides at least one channel pair that
can be configured as a master or a slave. Other channel pairs, if present, always operate
as slaves. All of the channel pairs within one Flexcomm Interface share one set of I2S
signals, and are configured together for either transmit or receive operation, using the
same mode, same data configuration and frame configuration. All such channel pairs can
participate in a time division multiplexing (TDM) arrangement. For cases requiring an
MCLK input and/or output, this is handled outside of the I2S block in the system level
clocking scheme.
Features
• A Flexcomm Interface may implement one or more I2S channel pairs, the first of which
could be a master or a slave, and the rest of which would be slaves. All channel pairs
are configured together for either transmit or receive and other shared attributes. The
number of channel pairs is defined for each Flexcomm Interface, and may be from 0
to 4.
• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to
32 bits. Each channel pair can also be configured independently to act as a single
channel (mono as opposed to stereo operation).
• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and
word select/frame trigger (WS), and data line (SDA).
• Data for all I2S traffic within one Flexcomm Interface uses the Flexcomm Interface
FIFO. The FIFO depth is 8 entries.
• Left justified and right justified data modes.
• DMA support using FIFO level triggering.
• TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is
supported. Each channel pair can act as any data slot. Multiple channel pairs can
participate as different slots on one TDM data line.
• The bit clock and WS can be selectively inverted.
• Sampling frequencies supported depends on the specific device configuration and
applications constraints (for example, system clock frequency and PLL availability.)
but generally supports standard audio data rates.
Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz.
7.16 Digital peripheral
7.16.1 LCD controller

The LCD controller provides all of the necessary control signals to interface directly to
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024  768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of
the displayed data) while still supporting many colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time required to operate the display.

7.16.1.1 Features
• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320  200, 320  240,
640  200, 640  240, 640  480, 800  600, and 1024  768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
• 16 bpp true-color non-palettized for color STN and TFT.
• 24 bpp true-color non-palettized for color TFT.
• Programmable timing for different display panels.
• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.
• Frame, line, and pixel clock signals.
• AC bias signal for STN, data enable signal for TFT panels.
• Supports little and big-endian, and Windows CE data formats.
• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.16.2 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:
7.16.2.1 Features
• Secure Digital memory (SD version 1.1).

• Secure Digital I/O (SDIO version 2.0).
• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1).
• MultiMedia Cards (MMC version 4.1).
• Supports up to a maximum of 50 MHz of interface frequency.
7.16.3 External memory controller

The LPC540xx/LPC54S0xx EMC is an ARM PrimeCell MultiPort Memory Controller
peripheral offering support for asynchronous static memory devices such as RAM, ROM,
and flash. In addition, it can be used as an interface with off-chip memory-mapped
devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture
(AMBA) compliant peripheral.

7.16.3.1 Features
• Read and write buffers to reduce latency and to improve performance.
• Low transaction latency.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• 8/16/32 data and 16/20/26 address lines wide static memory support.
• Static memory features include:
– Asynchronous page mode read.
– Programmable Wait States.
– Bus turnaround delay.
– Output enable and write enable delays.
– Extended wait.
• Dynamic memory interface support including single data rate SDRAM.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• EMC bus width (bit) on LQFP100 and TFBGA100 packages supports up to 8/16 data
line wide static memory.
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.

7.16.4 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional DMA
transfers for a single source and destination.
7.16.4.1 Features
• One channel per on-chip peripheral direction: typically one for input and one for output
for most peripherals.
• DMA operations can optionally be triggered by on- or off-chip events.
• Priority is user selectable for each channel.
• Continuous priority arbitration.
• Address cache.
• Efficient use of data bus.
• Supports single transfers up to 1,024 words.
• Address increment options allow packing and/or unpacking data.
7.17 Counter/timers
7.17.1 General-purpose 32-bit timers/external event counter

The LPC540xx/LPC54S0xx includes five general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.17.1.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.
• Up to four 32-bit captures can take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt. The number of
capture inputs for each timer that are actually available on device pins may vary by
device.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
– Shadow registers are added for glitch-free PWM output.
• For each timer, up to four external outputs corresponding to match registers with the
following capabilities (the number of match outputs for each timer that are actually
available on device pins may vary by device):
– Set LOW on match.
– Set HIGH on match.

– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• Up to four match registers can be configured for PWM operation, allowing up to three
single edged controlled PWM outputs. (The number of match outputs for each timer
that are actually available on device pins may vary by device.)
7.17.2 SCTimer/PWM
The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input
capture operations. The inputs and outputs of the SCTimer/PWM are shared with the
capture and match inputs/outputs of the 32-bit general-purpose counter/timers.
The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In
the two-counter case, in addition to the counter value the following operational elements
are independent for each half:
• State variable.
• Limit, halt, stop, and start conditions.
• Values of Match/Capture registers, plus reload or capture control values.
In the two-counter case, the following operational elements are global to the
SCTimer/PWM, but the last three can use match conditions from either counter:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts
7.17.2.1 Features
• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.
• Up counter(s) or up-down counter(s).
• State variable allows sequencing across multiple counter cycles.
• Event combines input or output condition and/or counter match in a specified state.
• Events control outputs, interrupts, and the SCTimer/PWM states.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• Selected event(s) can limit, halt, start, or stop a counter.
• Supports:

– 8 inputs
– 10 outputs
– 16 match/capture registers
– 16 events
– 16 states
• PWM capabilities including dead time and emergency abort functions
7.17.3 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.17.3.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
• The Watchdog Clock (WDCLK) uses the WDOSC as the clock source.
7.17.4 Real Time Clock (RTC) timer

The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero,
the preset value is reloaded and the counter continues. The RTC timer uses the 32.768
kHz clock input to create a 1 Hz or 1 kHz clock.
7.17.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
7.17.5.1 Features
• 24-bit interrupt timer.

• Four channels independently counting down from individually set values.
• Repeat and one-shot interrupt modes.

7.17.6 Repetitive Interrupt Timer (RIT)

The repetitive interrupt timer provides a free-running 48-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
7.17.6.1 Features
• 48-bit counter running from the main clock. Counter can be free-running or can be
reset when an RIT interrupt is generated.
• 48-bit compare value.
• 48-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
• Can be used for ETM debug time stamping.
7.18 12-bit Analog-to-Digital Converter (ADC)

The ADC supports a resolution of 12-bit and fast conversion rates of up to 5 Msamples/s.
Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible
trigger sources are the SCTimer/PWM, external pins, and the ARM TXEV interrupt.
The ADC supports a variable clocking scheme with clocking synchronous to the system
clock or independent, asynchronous clocking for high-speed conversions
The ADC includes a hardware threshold compare function with zero-crossing detection.
The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for
tight timing control between the ADC and the SCTimer/PWM.
7.18.1 Features
• 12-bit successive approximation analog to digital converter.
• Input multiplexing among up to 12 pins.
• Two configurable conversion sequences with independent triggers.
• Optional automatic high/low threshold comparison and “zero crossing” detection.
• Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
• 12-bit conversion rate of 5.0 Msamples/s. Options for reduced resolution at higher
conversion rates.
• Burst conversion mode for single or multiple inputs.
• Synchronous or asynchronous operation. Asynchronous operation maximizes
flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger
latency and can eliminate uncertainty and jitter in response to a trigger.

7.19 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.19.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.
• Supports CPU PIO or DMA back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation.
– 16-bit write: 2-cycle operation (8-bit x 2-cycle).
– 32-bit write: 4-cycle operation (8-bit x 4-cycle).
7.20 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage
varies inversely with device temperature with an absolute accuracy of better than ±5 C
over the full temperature range (40 C to +105 C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines.
After power-up, the temperature sensor output must be allowed to settle to its stable value
before it can be used as an accurate ADC input.
7.21 Security features

The LPC540xx/LPC54S0xx consists of an AES engine (LPC54S0xx only), a SHA engine,
a random number generator, and a key storage block that supports keys stored in OTP or
keys from an SRAM based PUF (LPC54S0xx only). Additionally, for each device there is a
128-bit unique device serial number for identification.
7.21.1 SHA-1 and SHA-2

All LPC540xx/LPC54S0xx devices provide on-chip hash support to perform SHA-1 and
SHA-2 with 256-bit digest (SHA-256). Hashing is a way to reduce arbitrarily large
messages or code images to a relatively small fixed size “unique” number called a digest.
The SHA-1 Hash produces a 160 bit digest (5 words), and the SHA-256 hash produces a
256 bit digest (8 words).
7.21.1.1 Features
• Performs SHA-1 and SHA-2(256) based hashing.


• Used with HMAC to support a challenge/response or to validate a message.
7.21.2 AES encryption/decryption

The LPC54S0xx devices provide an on-chip hardware AES encryption and decryption
engine to protect the image content and to accelerate processing for data encryption or
decryption, data integrity, and proof of origin. Data can be encrypted or decrypted by the
AES engine using the scrambled key from the OTP or a software supplied key.
7.21.2.1 Features
• Encryption and Decryption of data.

• Secure storage of AES key that cannot be read.
• AES engine peak performance of 0.5 bytes/clock cycle.
• GF128 Hash Engine.
• AES engine supports 128, 192 or 256-bit key in:
– Electronic Codebook (ECB) mode.
– Cipher Block Chaining (CBC) mode.
– Cipher Feedback (CFB) mode.
– Output Feedback (OFB) mode.
– Counter (CTR) mode.
– Galois/Counter Mode (GCM).
• The AES engine is compliant with the FIPS (Federal Information Processing
Standard) Publication 197, Advanced Encryption Standard (AES).
• Data is processed in little endian mode. This means that the first byte read from
memory is integrated into the AES codeword as least significant byte. The 16th byte
read from memory is the most significant byte of the first AES codeword.
• DMA transfers supported through the DMA controller.
7.21.3 PUF
The PUF controller on the LPC54S0xx provides a secure key storage without injecting or
provisioning device unique PUF root key.The PUF block can generate, store, and
reconstruct key sizes from 64 to 4096 bits.
7.21.3.1 PUF keys

The PUF controller provides secure key storage without storing the key. This is done by
using the digital fingerprint of a device derived from SRAM. Instead of storing the key, a
Key Code is generated, which in combination with the digital fingerprint is used to
reconstruct keys that are routed to the AES engine or for use by software. The PUF
controller provides generation and secure storage for keys.
7.21.3.2 PUF controller features

The PUF controller has the following features:
• Key strength of 256 bits.

– The PUF constructs 256-bit strength device unique PUF root key using the digital
fingerprint of a device derived from SRAM and error correction data called
Activation Code (AC). The Activation Code is generated during enrollment
process. The Activation Code should be stored on external non-volatile memory
device in the system.
• Generation, storage, and reconstruction of keys.
• Key sizes from 64 to 4096 bits.
– PUF controller allows storage of keys, generated externally or on chip, of sizes 64
to 4096 bits.
– PUF Controller combines keys with digital fingerprint of device to generate key
codes. These key codes should be provided to the controller to reconstruct original
key. They can be stored on external non-volatile memory device in the system.
• Key output via dedicated hardware interface or through register interface.
– PUF controller allows to assign a 4-bit index value for each key while generating
key codes. Keys that are assigned index value zero are output through HW bus,
accessible to AES engine only. Keys with non-zero index are available through
APB register interface.
• 32-bit APB interface.
7.22 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported. The ARM Cortex-M4 is configured to support up to eight
breakpoints and four watch points.
The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,
execute the boot code, restart from address 0x0000 0000, and break at the user entry
point.
The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the
SWD functions by default.

8. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage (core and on pin VDD [2] -0.5 +4.6 V
external rail)
VDDA analog supply voltage on pin VDDA -0.5 +4.6 V
VBAT battery supply voltage on pin VBAT -0.5 +4.6 V
Vref reference voltage on pin VREFP - -0.5 +4.6 V
VI input voltage only valid when the VDD > 1.8 V; [6][7] -0.5 +5.0 V
5 V tolerant I/O pins
on I2C open-drain pins [5] -0.5 +5.0 V
USB_DM, -0.5 +5.0 V
USB_DP pins
VIA analog input voltage on digital pins configured for an [8][9] -0.5 VDD V
analog function
IDD supply current per supply pin, [3] - 200 mA

1.71 V  VDD < 2.7 V
supply current per supply pin, [3] - 300 mA
2.7 V  VDD < 3.6 V
ISS ground current per ground pin, [3] - 200 mA
1.71 V  VDD < 2.7 V
ground current per ground pin, [3] - 300 mA
2.7 V  VDD < 3.6 V
Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); - 100 mA
Tj < 125 C
Tstg storage temperature [10] -65 +150 C
Tj(max) maximum junction - +150 C
temperature

Table 10. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Ptot(pack) total power dissipation LQFP208, based on package heat [11] - 1.2 W
(per package) transfer, not device power
consumption
LQFP208, based on package heat [12] - 0.95 W
transfer, not device power
consumption
consumption
consumption
TFBGA180, based on package [11] - 0.95 W
heat transfer, not device power
consumption
consumption
consumption
consumption
VESD electrostatic discharge human body model; all pins [4] - 2000 V
voltage
[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 20.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 20) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] The peak current is limited to 25 times the corresponding maximum current.
[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[6] Applies to all 5 V tolerant I/O pins except true open-drain pins.
[7] Including the voltage on outputs in 3-state mode.
[8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
[11] JEDEC (4.5 in  4 in); still air.
[12] Single layer (4.5 in  3 in); still air.
[13] 8-layer (4.5 in  3 in); still air.

9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb +  P D  R th  j – a   (1)
• Tamb = ambient temperature (C),

• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 11. Thermal resistance

Symbol Parameter Conditions Max/Min Unit
LQFP208 Package
Rth(j-a) thermal resistance from JEDEC (4.5 in  4 in); still air 33 15 % C/W
junction to ambient Single-layer (4.5 in  3 in); still air 41 15 % C/W
Rth(j-c) thermal resistance from 16 15 % C/W
junction to case
LQFP100 Package
junction to ambient Single-layer (4.5 in  3 in); still air 65 15 % C/W
junction to case
TFBGA180 Package
junction to ambient 8-layer (4.5 in  3 in); still air 33 15 % C/W
junction to case
TFBGA100 Package
junction to ambient 8-layer (4.5 in  3 in); still air 60 15 % C/W
junction to case

10. Static characteristics
10.1 General operating conditions

Table 12. General operating conditions
Tamb = −40 °C to +105 °C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
fclk CPU clock frequency - - 180 MHz
CPU clock frequency For USB high-speed device and 90 - 180 MHz
host operations
CPU clock frequency For USB full-speed device and host 12 - 180 MHz
operations
VDD supply voltage (core 1.71 - 3.6 V
and external rail) For OTP programming only [2] 2.7 - 3.6 V
For USB full-speed operation only 3.0 - 3.6 V
For USB high-speed operation only 1.71 - 3.6 V
VDDA analog supply voltage 1.71 - 3.6 V
VBAT battery supply voltage 1.71 - 3.6 V
Vrefp ADC positive reference VDDA 2 V 2.0 - VDDA V
voltage
VDDA < 2 V VDDA - VDDA V
USB1_AVDD3V3, USB1 analog supply 3.0 3.3 3.6 V
USB1_AVDDTX3V3
RTC oscillator pins
Vi(rtcx) 32.768 kHz oscillator on pin RTCXIN -0.5 - +3.6 V
input voltage
Vo(rtcx) 32.768 kHz oscillator on pin RTCXOUT -0.5 - +3.6 V
output voltage
Vi(xtal) crystal input voltage on pin XTALIN 0.5 - 1.95 V
Vo(xtal) crystal output voltage on pin XTALOUT 0.5 - 1.95 V
[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
[2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state.
10.2 CoreMark data

Table 13. CoreMark score
Tamb = 25°C, VDD = 3.3V
Parameter Conditions Typ Unit
ARM Cortex-M4 in active mode
CoreMark score CoreMark code executed from SRAMX;
CCLK = 12 MHz [1][3][4][5] 3.38 (Iterations/s) / MHz
[1] Clock source FRO. PLL disabled.

[2] Clock source 12 MHz FRO. PLL enabled.
[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.
[5] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered.
aaa-028920
5
Coremark score
(iterations/s/MHz)
3
M4 SRAM
0
12 33 54 75 96 117 138 159 180
Frequency (MHz)
Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled;
Measured with IAR ver 8.22.2. Optimization level 3, optimized for time ON.
12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,
and 180 MHz: FRO enabled; PLL enabled.
CoreMark score from SRAMX: SRAM0 is powered.
Fig 13. Typical CoreMark score ((iterations/s)/MHz) vs. Frequency (MHz) from SRAMX

10.3 Power consumption

Power measurements in Active, sleep, and deep-sleep modes were performed under the
following conditions:
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIO DIR register.
• Write 1 to the GPIO CLR register to drive the outputs LOW.
• All peripherals disabled.
Table 14. Static characteristics: Power consumption in active and sleep mode
Tamb = −40 °C to +105 °C, unless otherwise specified.1.71 V ≤ VDD ≤ 3.6 V.
Active mode
IDD supply current CoreMark code executed from
SRAMX:
CCLK = 12 MHz [2][3][4] - 3.0 - mA
CCLK = 96 MHz [2][3][4] - 16.0 - mA
CCLK = 180 MHz [3][4][5] - 35.0 - mA
Sleep mode
IDD supply current CCLK = 12 MHz [2][3][4] - 1.7 - mA
CCLK = 96 MHz [2][3][4] - 4.1 - mA
CCLK = 180 MHz [3][4][5] - 8.3 - mA
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[2] Clock source FRO. PLL disabled.
[4] Compiler settings: Keil uVision v.5.23, optimization level 0, optimized for time off.
[5] Clock source FRO. PLL enabled.

aaa-028921
340
(μA/MHz)
290
240
M4 SRAM (FRO, PLL)
M4 SRAM (FRO)
190
140
90
12 40 68 96 124 152 180
Frequency (MHz)
Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled;
Measured with Keil uVision v.5.23. Optimization level 0, optimized for time off.
12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,
and 180 MHz: FRO enabled; PLL enabled.
CoreMark A/MHz from SRAMX: SRAM0 is powered.
Fig 14. CoreMark power consumption: typical A/MHz vs. frequency (MHz) SRAMX
Table 15. Static characteristics: Power consumption in deep-sleep and deep power-down modes
Tamb = −40 °C to +105 °C, unless otherwise specified, 1.71 V ≤ VDD ≤ 2.2 V.
Symbol Parameter Conditions Min Typ[1][2] Max[3] Unit
IDD supply current Deep-sleep mode:
SRAMX (64KB) powered - 54 175 A
Tamb = 25 C
SRAMX (64 KB) powered - - 2092 A
Tamb = 105 C
Deep power-down mode
RTC oscillator input grounded (RTC oscillator - 709 1.1 A
disabled)
Tamb = 25 C
RTC oscillator input grounded (RTC oscillator - - 27 A
disabled)
Tamb = 105 C
RTC oscillator running with external crystal - 320 - nA
VDD = VDDA = VREFP = VBAT = 1.8 V
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 1.8 V.
[3] Tested in production. VDD = 1.71 V. At hot temperature and below 2.0 V, the supply current increases slightly because of reduction of
available RBB (reverse body bias) voltage.

Table 16. Static characteristics: Power consumption in deep-sleep and deep power-down modes
Symbol Parameter Conditions Min Typ[1][2] Max[3] Unit
IDD supply current Deep-sleep mode:
SRAMX (64 KB) powered - 55 175 A
Tamb = 25 C
SRAMX (64 KB) powered - - 2020 A
Tamb = 105 C
Deep power-down mode
RTC oscillator input grounded (RTC oscillator - 0.89 1.6 A
disabled)
Tamb = 25 C
RTC oscillator input grounded (RTC oscillator - - 42 A
disabled)
Tamb = 105 C
RTC oscillator running with external crystal - 660 - nA
VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 3.3 V.
[3] Tested in production, VDD = 3.6 V.
Table 17. Static characteristics: Power consumption in deep power-down mode

Symbol Parameter Conditions Min Typ[1][2] Max Unit
IBAT battery supply deep power-down mode;
current RTC oscillator running with external crystal
VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V - 0 - nA
VDD = VDDA= VREFP = 0 V or tied to ground, VBAT = - 380[3] - nA
3.0 V
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).
[3] If VBAT> VDD, the external reset pin must be floating to prevent high VBAT leakage.

aaa-028923
1200
IDD
(μA)
1000
800
600
3.6 V
400 3.3 V
1.8 V
1.71 V
200
0
-40 -10 20 50 80 110
Temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks disabled; all SRAM disabled except
64 KB SRAMX.
Remark: At hot temperature and below 2.0 V, the supply current increases slightly because of
reduction of available RBB (reverse body bias) voltage.
Fig 15. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
aaa-028924
25
IDD
(μA)
20
15
10
3.6 V
3.3 V
1.8 V
5 1.71 V
0
-40 -10 20 50 80 110
Temperature (°C)
RTC disabled (RTC oscillator input grounded).

Fig 16. Deep power-down mode: Typical supply current IDD versus temperature for
different supply voltages VDD
Table 18 shows the typical peripheral power consumption measured on a typical sample
at Tamb = 25 °C and VDD = 3.3 V. The supply current per peripheral is measured as the
difference in supply current between the peripheral block enabled and the peripheral block
disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1/2, and PDRUNCFG0/1

registers. All other blocks are disabled and no code accessing the peripheral is executed.
The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz
and 180MHz.
Table 18. Typical peripheral power consumption[1][2]

VDD = 3.3 V; Tamb = 25 °C
Peripheral IDD in uA
FRO 100
WDT OSC 2.0
BOD 2.0
[1] The supply current per peripheral is measured as the difference in supply current between the peripheral
block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are
disabled and no code accessing the peripheral is executed.
[2] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.
Table 19. Typical AHB/APB peripheral power consumption [3][4][5]

Tamb = 25 °C, VDD = 3.3 V;
Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz
AHB peripheral CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync
APB bus: 12 MHz APB bus: 48 MHz APB bus: 96 MHz APB bus: 180 MHz
USB0 device 0.3 0.3 0.3 0.4
USB1 device 4.4 4.4 4.4 5.0
DMIC 0.2 0.2 0.2 0.2
GPIO0 [1] 0.9 0.9 0.9 1.0
GPIO1 [1] 0.8 0.8 0.8 1.0
GPIO2 [1] 1.0 1.0 1.0 1.1
GPIO3 [1] 1.1 1.1 1.1 1.3
GPIO4 [1] 1.0 1.0 1.0 1.2
GPIO5 [1] 0.7 0.7 0.7 0.8
DMA 0.7 0.7 0.7 0.8
CRC 1.0 1.0 1.0 1.0
ADC0 1.6 1.6 1.6 1.9
SCTimer/PWM 4.5 4.5 4.5 5.3
Ethernet AVB 24.0 24.0 24.0 28.0
LCD 13.0 13.0 13.0 15.0
EMC 39.0 39.0 39.0 45.4
CAN0 10.8 10.8 10.8 12.6
CAN1 10.7 10.7 10.7 12.4
SD/MMC 7.9 7.9 7.9 9.3
Flexcomm Interface 0 1.6 1.6 1.6 1.9
(USART, SPI, I2C)
Flexcomm Interface1 1.6 1.6 1.6 1.8
(USART, SPI, I2C)
(USART, SPI, I2C)


Tamb = 25 °C, VDD = 3.3 V;
(USART, SPI, I2C)
(USART, SPI, I2C)
(USART, SPI, I2C)
(USART, SPI, I2C, I2S)
(USART, SPI, I2C, I2S)
(USART, SPI, I2C)
(USART, SPI, I2C)
(SPI)
Sync APB peripheral CPU: 12 MHz, sync CPU: 48 MHz, sync CPU: 96 MHz, sync CPU: 180 MHz, sync
APB bus: 12 MHz APB bus: 48 MHz APB bus: 96 MHz APB bus: 180 MHz
INPUTMUX [1] 0.83 0.85 0.86 1.0
IOCON [1] 2.67 2.65 2.65 3.13
PINT 1.1 1.1 1.1 1.3
GINT0 and GINT1 1.33 1.35 1.34 1.52
WWDT 0.42 0.42 0.42 0.46
RTC 0.3 0.3 0.3 0.3
MRT 0.3 0.3 0.3 0.3
RIT 0.1 0.1 0.1 0.1
UTICK 0.2 0.2 0.2 0.2
CTimer0 0.8 0.8 0.8 0.9
CTimer1 0.8 0.9 0.9 1.0
CTimer2 0.83 0.85 0.88 0.99
Smart card0 2.5 2.5 2.5 2.8
Smart card1 2.5 2.5 2.5 2.8
RNG 1.4 1.4 1.4 1.5
OTP controller 4.0 4.0 4.0 4.5
SHA 1.2 1.2 1.2 1.3
AES <tbd> <tbd> <tbd> <tbd>
PUF <tbd> <tbd> <tbd> <tbd>


Tamb = 25 °C, VDD = 3.3 V;
Async APB peripheral CPU: 12 MHz, CPU: 48 MHz, sync CPU: 96 MHz, CPU: 180 MHz,
Async APB bus: 12 APB bus: 12 MHz[2] Async APB bus: 12 Async APB bus:
MHz MHz[2] 12 MHz[2]
Timer3 0.9 0.9 0.9 0.9
Timer4 0.9 0.9 0.9 0.9
[1] Turn off the peripheral when the configuration is done.

[2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a
higher frequency.
[3] The supply current per peripheral is measured as the difference in supply current between the peripheral
block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and
PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed.
[4] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz and 180 MHz.
[5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.
10.4 Pin characteristics

Table 20. Static characteristics: pin characteristics
Tamb = −40 °C to +105 °C, unless otherwise specified. 1.71 V ≤ VDD ≤ 3.6 V unless otherwise specified. Values tested in
production unless otherwise specified.
RESET pin
VIH HIGH-level input voltage 0.8  VDD - 5.0 V
VIL LOW-level input voltage 0.5 - 0.3  VDD V
Vhys hysteresis voltage [14] 0.05  VDD - - V
Standard I/O pins
Input characteristics
IIL LOW-level input current VI = 0 V; on-chip pull-up resistor - 3.0 180 nA
disabled.
IIH HIGH-level input current VI = VDD; VDD = 3.6 V; for RESETN 3.0 180 nA
pin.
IIH HIGH-level input current VI = VDD; on-chip pull-down resistor - 3.0 180 nA
disabled
VI input voltage pin configured to provide a digital [3]
function;
VDD  1.8 V
0 - 5.0 V
VDD = 0 V 0 - 3.6 V
VIH HIGH-level input voltage 1.71 V  VDD < 2.7 V 1.5 - 5.0 V
2.7 V  VDD  3.6 V 2.0 - 5.0 V
VIL LOW-level input voltage 1.71 V  VDD < 2.7 V 0.5 - +0.4 V
2.7 V  VDD  3.6 V 0.5 - +0.8 V
Vhys hysteresis voltage [14] 0.1  VDD - - V
Output characteristics
VO output voltage output active 0 - VDD V

Table 20. Static characteristics: pin characteristics …continued

IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip - 3 180 nA
pull-up/pull-down resistors disabled
VOH HIGH-level output voltage IOH = 4 mA; 1.71 V  VDD < 2.7 V VDD  0.4 - - V
IOH = 6 mA; 2.7 V  VDD  3.6 V VDD  0.4
VOL LOW-level output voltage IOL = 4 mA; 1.71 V  VDD < 2.7 V - - 0.4 V
IOL = 6 mA; 2.7 V  VDD 3.6 V - - 0.4 V
IOH HIGH-level output current VOH = VDD  0.4 V; 4.0 - - mA
1.71 V  VDD < 2.7 V
VOH = VDD  0.4 V; 6.0 - - mA
2.7 V  VDD  3.6 V
IOL LOW-level output current VOL = 0.4 V; 1.71 V  VDD < 2.7 V 4.0 - - mA
VOL = 0.4 V; 2.7 V  VDD  3.6 V 6.0 - - mA
IOHS HIGH-level short-circuit 1.71 V  VDD < 2.7 V [2][4] - - 35 mA
output current
drive HIGH; connected to 2.7 V  VDD  3.6 V - - 87 mA
ground;
IOLS LOW-level short-circuit 1.71 V  VDD < 2.7 V [2][4] - - 30 mA
output current
drive LOW; connected to 2.7 V  VDD  3.6 V - - 77 mA
VDD
Weak input pull-up/pull-down characteristics
Ipd pull-down current VI = VDD 25 80 A
VI = 5 V [2] 80 100 A
Ipu pull-up current VI = 0 V 25 80 A
VDD < VI < 5 V [2][7] 6 30 A
Open-drain I2C pins
VIH HIGH-level input voltage 1.71 V  VDD < 2.7 V 0.7  VDD - - V
2.7 V  VDD  3.6 V 0.7  VDD - - V
VIL LOW-level input voltage 1.71 V  VDD < 2.7 V 0 - 0.3  VDD V
2.7 V  VDD  3.6 V 0 - 0.3  VDD V
Vhys hysteresis voltage 0.1  VDD - - V
ILI input leakage current VI = VDD [5] - 2.5 3.5 A
VI = 5 V - 5.5 10 A
IOL LOW-level output VOL = 0.4 V; pin configured for 4.0 - - mA
current standard mode or fast mode
VOL = 0.4V; pin configured for 20 - - mA
Fast-mode Plus

Table 20. Static characteristics: pin characteristics …continued

USB0_DM and USB0_DP pins
VI input voltage 0 - VDD V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
Vhys hysteresis voltage 0.4 - - V
Zout output impedance [11] 33.0 - 44 Ω
VOH HIGH-level output voltage [12] 2.8 - - V
VOL LOW-level output voltage [13] - - 0.3 V
IOH HIGH-level output current VOH = VDD  0.3 V [9][10] 38 - 74 mA
VOH = VDD  0.3 V [10][11] 6.0 9.0 mA
IOL LOW-level output current VOL = 0.3 V [9][10] 38 - 74 mA
VOL = 0.3 V [10][11] 6.0 9.0 mA
IOLS LOW-level short-circuit drive LOW; pad connected to [10] - - 100 mA
output current ground
IOHS HIGH-level short-circuit drive HIGH; pad connected to [10] - - 100 mA
output current ground
Pin capacitance
Cio input/output capacitance I2C-bus pins [8] - - 6.0 pF
pins with digital functions only [6] - - 2.0 pF
Pins with digital and analog [6] - - 7.0 pF
functions
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.
[2] Based on characterization. Not tested in production.
[3] With respect to ground.
[4] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[5] To VSS.
[6] The values specified are simulated and absolute values, including package/bondwire capacitance.
[7] The weak pull-up resistor is connected to the VDD rail and pulls up the I/O pin to the VDD level.
[8] The value specified is a simulated value, excluding package/bondwire capacitance.
[9] Without 33 Ω  2 % series external resistor.
[10] The parameter values specified are simulated and absolute values.
[11] With 33 Ω  2 % series external resistor.
[12] With 15 KΩ  5 % resistor to VSS.
[13] With 1.5 KΩ  5% resistor to 3.6 V external pull-up.
[14] Guaranteed by design, not tested in production.

VDD
IOL
Ipd
- +
pin PIO0_n A
IOH
Ipu
+ -
pin PIO0_n A
aaa-010819
Fig 17. Pin input/output current measurement
10.4.1 Electrical pin characteristics
aaa-017309 aaa-017310
60 60
-40C
IOL IOL
25C
(mA) (mA)
90C
50 105C
45 -40C
25C
40 90C
105C
30 30
20
15
10
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
VOL (V) VOL (V)
Conditions: VDD = 1.8 V; on pins PIO0_13 to PIO0_14. Conditions: VDD = 3.3 V; on pins PIO0_13 to PIO0_16.
Fig 18. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage
VOL

aaa-017311 aaa-017312
12 15
-40C
IOL IOL
25C
(mA) (mA)
90C
10 105C
12
-40C
90C
8 25C
105C 9
6
4
3
2
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6
VOL (V) VOL (V)
Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.
Fig 19. Typical LOW-level output current IOL versus LOW-level output voltage VOL
aaa-017313 aaa-017314
1.8 3.5
VOH VOH
(V) (V)
1.7
3.2
1.6
2.9
-40C -40C
1.5 25C 25C
90C 90C
105C 2.6 105C
1.4
2.3
1.3
1.2 2
0 2.4 4.8 7.2 9.6 12 0 7 14 21 28 35
IOH (mA) IOH (mA)
Fig 20. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH

aaa-017315 aaa-017316
40 50
Ipu Ipu
(μA) (μA)
30
20
10
0 -10
-40C -40C
25C -30 25C
-20 90C 90C
105C 105C
-50
-40 -70
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 1.0 2.0 3.0 4.0 5.0
VI (V) VI (V)
Fig 21. Typical pull-up current IPU versus input voltage VI
aaa-017317 aaa-017318
70 100
Ipd Ipd
(μA) (μA)
56 80
42 60
28 40
25C 105C
-40C 90C
90C 25C
14 105C 20 -40C
0 0
0.0 0.7 1.4 2.1 2.8 3.5 0 1 2 3 4 5
VI (V) VI (V)
Conditions: VDD = 1.8V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.
Fig 22. Typical pull-down current IPD versus input voltage VI

11. Dynamic characteristics
11.1 I/O pins

Table 21. Dynamic characteristic: I/O pins[1]
Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V
Symbol Parameter Conditions Min Typ Max Unit
Standard I/O pins - normal drive strength
tr rise time pin configured as output; SLEW = 1 [2][3]
(Fast-mode);
2.7 V  VDD <= 3.6 V 1.0 - 2.5 ns
1.71 V  VDD <= 1.98 V 1.6 - 3.8 ns
tf fall time pin configured as output; SLEW = 1 [2][3]
(Fast-mode);
2.7 V  VDD <= 3.6 V 0.9 - 2.5 ns
1.71 V  VDD <= 1.98 V 1.7 - 4.1 ns
tr rise time pin configured as output; SLEW = 0 (standard [2][3]
mode);
2.7 V  VDD 3.6 V 1.9 - 4.3 ns
1.71 V  VDD  1.98 V 2.9 - 7.8 ns
tf fall time pin configured as output; SLEW = 0 (standard [2][3]
mode);
2.7 V  VDD  3.6 V 1.9 - 4.0 ns
1.71 V  VDD  1.98 V 2.7 - 6.7 ns
[1] Simulated data, not tested in production.

[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.
[3] The slew rate is configured in the IOCON block the SLEW bit.
Remark: For I/O pins that are configured as input only, there is no limitation on the rise
and fall times.

11.2 Wake-up process

Table 22. Dynamic characteristic: Typical wake-up times from low power modes
VDD = 3.3 V;Tamb = 25 °C; using FRO as the system clock.
twake wake-up from sleep mode [2][3] - 2.0 - s
time from deep-sleep mode; SRAMx [2][5] - 150 - s
powered.
SRAM0, SRAM1, SRAM2,
SRAM3, and USB SRAM powered
down.
from deep power-down mode; [4][5] - 1.2 - ms
RTC disabled; using RESET pin.
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler.
[3] FRO enabled, all peripherals off. PLL disabled.
[4] RTC disabled. Wake up from deep power-down causes the part to go through entire reset
process. The wake-up time measured is the time between when the RESET pin is triggered to wake the
device up and when a GPIO output pin is set in the reset handler.
[5] FRO disabled.

11.3 External memory interface

Table 23. Dynamic characteristics: Static external memory interface
CL = 10 pF balanced loading on all pins, Tamb = −40 °C to 105 °C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter[1] Conditions[1] Min Typ Max Unit
Read cycle parameters
tCSLAV CS LOW to address RD1 1.2 - 1.6 ns
valid time
tCSLOEL CS LOW to OE LOW RD2 [2] 0.4+ Tcy(clk)  - 0.8+ Tcy(clk)  ns
time WAITOEN WAITOEN
tCSLBLSL CS LOW to BLS LOW RD3; PB = 1 [2][6] 1.6 - 0 ns
time
tOELOEH OE LOW to OE HIGH RD4 [2] (WAITRD  - 0.3 ns
time WAITOEN + 1)  + (WAITRD 
Tcy(clk) WAITOEN + 1) 
Tcy(clk)
tam memory access time RD5 [2][3] 6.7 - - ns
+ (WAITRD 
WAITOEN +1) 
Tcy(clk)
th(D) data input hold time RD6 [2][4] 4.8 - - ns
tCSHBLSH CS HIGH to BLS HIGH PB = 1 [6] 0.8 - 1.5 ns
time
tCSHOEH CS HIGH to OE HIGH [2] 0.5 - 0.9 ns
time
tOEHANV OE HIGH to address [2] 0.4 - 0 ns
invalid time
tdeact deactivation time RD7 [2] 0.5 - 0.9 ns
Write cycle parameters
tCSLAV CS LOW to address WR1 0.1 - 0.5 ns
valid time
tCSLDV CS LOW to data valid WR2 1.0 - 2.2 ns
time
tCSLWEL CS LOW to WE LOW WR3; PB =1 [2][6] 0.6 - 0 ns
time
tCSLBLSL CS LOW to BLS LOW WR4; PB = 1 [2][6] 1.2 - 0 ns
time
tWELWEH WE LOW to WE HIGH WR5; PB =1 [2][6] (WAITWR  - 0.1 ns
time WAITWEN + 1)  + (WAITWR 
Tcy(clk) WAITWEN + 1) 
Tcy(clk)
tBLSLBLSH BLS LOW to BLS PB = 1 [2][6] 2.5 - 5.5 ns
HIGH time
tWEHDNV WE HIGH to data WR6; PB =1 [2][6] 1.6 - 2.9 ns
invalid time
tWEHEOW WE HIGH to end of WR7; PB = 1 [2][5][6] 0.6 - 0.9 ns
write time

Table 23. Dynamic characteristics: Static external memory interface …continued

tBLSHDNV BLS HIGH to data PB = 1 [6] 0.8 - 0 ns
invalid time
tWEHANV WE HIGH to address PB = 1 [6] 0.6 - 0.9 ns
invalid time
tdeact deactivation time WR8; PB = 0; [2][6] 0.8 - 0 ns
PB = 1
tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.2 - (WAITWEN + 1) ns
+ (WAITWEN + 1)  Tcy(clk)
 Tcy(clk)
tBLSLBLSH BLS LOW to BLS WR10; PB = 0 [2][6] 2.5 - 5.5 ns
HIGH time + (WAITWR  + (WAITWR 
WAITWEN + 1)  WAITWEN + 1) 
Tcy(clk) Tcy(clk)
tBLSHEOW BLS HIGH to end of WR11; PB = 0 [2][5][6] 0.8 - Tcy(clk) ns
write time + Tcy(clk)
tBLSHDNV BLS HIGH to data WR12; [2][6] 0.2 + Tcy(clk) - 0.5 + Tcy(clk) ns
invalid time PB = 0
[1] Parameters are shown as RDn or WDn in Figure 23 as indicated in the Conditions column.
[2] Tcy(clk) = 1/EMC_CLK (see UM11060 LPC540xx/LPC54S0xx manual).
[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060
LPC540xx/LPC54S0xx manual).
Table 24. Dynamic characteristics: Static external memory interface

tCSLAV CS LOW to address RD1 1.2 - 1.6 ns
valid time
tCSLOEL CS LOW to OE LOW RD2 [2] 0.5+ Tcy(clk)  - 0.8+ Tcy(clk)  WAITOEN ns
time WAITOEN
tCSLBLSL CS LOW to BLS LOW RD3; PB = 1 [2][6] 2.3 - 0 ns
time
tOELOEH OE LOW to OE HIGH RD4 [2] (WAITRD  - 0.3 ns
time WAITOEN + 1)  + (WAITRD 
Tcy(clk) WAITOEN + 1)  Tcy(clk)
tam memory access time RD5 [2][3] 7.9 - - ns
+ (WAITRD 
WAITOEN +1) 
Tcy(clk)

Table 24. Dynamic characteristics: Static external memory interface …continued

th(D) data input hold time RD6 [2][4] 5.5 - - ns
tCSHBLSH CS HIGH to BLS HIGH PB = 1 [6] 0.7 - 1.5 ns
time
tCSHOEH CS HIGH to OE HIGH [2] 0.5 - 0.9 ns
time
tOEHANV OE HIGH to address RD8 [2] 0.4 - 0 ns
invalid time
tdeact deactivation time RD7 [2] 0.5 - 0.9 ns
Write cycle parameters[2]
tCSLAV CS LOW to address WR1 0.1 - 0.5 ns
valid time
tCSLDV CS LOW to data valid WR2 1 - 2.2 ns
time
tCSLWEL CS LOW to WE LOW WR3; PB =1 [2][6] 0.5 + - (WAITWEN + 1)  Tcy(clk) ns
time (WAITWEN + 1) 
Tcy(clk)
tCSLBLSL CS LOW to BLS LOW WR4; PB = 1 [2][6] 1.9 - 0 ns
time
tWELWEH WE LOW to WE HIGH WR5; PB =1 [2][6] 0.1 + - (WAITWEN + 1)  Tcy(clk) ns
time (WAITWEN + 1) 
Tcy(clk)
tBLSLBLSH BLS LOW to BLS PB = 1 [2][6] 3.1 - 6.7 ns
HIGH time
tWEHDNV WE HIGH to data WR6; PB =1 [2][6] 1.6 + Tcy(clk) - 2.8 + Tcy(clk) ns
invalid time
tWEHEOW WE HIGH to end of WR7; PB = 1 [2][5][6] 0.5+Tcy(clk) - 0.8 + Tcy(clk) ns
write time
tBLSHDNV BLS HIGH to data PB = 1 [6] 0.8 - 0 ns
invalid time
tWEHANV WE HIGH to address PB = 1 [6] 0.5 - 0.8 ns
invalid time
tdeact deactivation time WR8; PB = 0; [2][6] 0.8 - 0 ns
PB = 1
tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.9 - (WAITWEN + 1)  Tcy(clk) ns
+ (WAITWEN + 1)
 Tcy(clk)
tBLSLBLSH BLS LOW to BLS WR10; PB = 0 [2][6] 3.1+ (WAITWR  - 6.7+ (WAITWR  ns
HIGH time WAITWEN + 1)  WAITWEN + 1)  Tcy(clk)
Tcy(clk)
tBLSHEOW BLS HIGH to end of WR11; PB = 0 [2][5][6] 0.8 - Tcy(clk) ns
write time + Tcy(clk)
tBLSHDNV BLS HIGH to data WR12; [2][6] 0.2 + Tcy(clk) - 0.5 + Tcy(clk) ns
invalid time PB = 0
[1] Parameters are shown as RDn or WDn in Figure 23 as indicated in the Conditions column.

[2] Tcy(clk) = 1/EMC_CLK (see UM11060 LPC540xx/LPC54S0xx manual).

[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060
LPC540xx/LPC54S0xx manual).
EMC_Ax
RD1 WR1
EMC_CSx
WR8
RD8
RD2
RD4
EMC_OE
RD7
WR9 WR10 WR11
EMC_BLSx
EMC_WE
RD5a
RD5b
WR2 WR12
RD5 RD6
EMC_Dx
EOR EOW
aaa-026103
Fig 23. External static memory read/write access (PB = 0)

EMC_Ax
RD1 WR1
EMC_CSx
RD2 RD8 WR8
RD4
EMC_OE
RD3 RD7 WR4
EMC_BLSx
RD7 WR8
WR3 WR5 WR7
EMC_WE
RD5a
RD5b
RD5c
WR2 WR6
RD6
RD5
EMC_Dx
EOR EOW
aaa026104
Fig 24. External static memory read/write access (PB =1)
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
RD5 RD5 RD5 RD5
EMC_Dx
002aag216
Fig 25. External static memory burst read cycle

Table 25. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2]
delays introduced by external device and PCB. Values based on simulation. tcmddly is programmable delay value for EMC
command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input
data sampling.
Symbol Parameter Min Typ Max Unit
For RD = 1
Common to read and write cycles
Tcy(clk) clock cycle time [1] 10 - - ns
td(SV) chip select valid delay time - - tcmddly + 3.7 ns
th(S) chip select hold time tcmddly + 1.7 - - ns
td(RASV) row address strobe valid - - tcmddly + 4.1 ns
delay time
th(RAS) row address strobe hold tcmddly + 1.8 - - ns
time
td(CASV) column address strobe valid - - tcmddly + 4.4 ns
delay time
th(CAS) column address strobe hold tcmddly + 1.9 - - ns
time
td(WV) write valid delay time - - tcmddly + 5.1 ns
th(W) write hold time tcmddly + 2.4 - - ns
td(AV) address valid delay time - - tcmddly + 4.8 ns
th(A) address hold time tcmddly + 1.7 - - ns
tsu(D) data input set-up time 0.5 - - ns
th(D) data input hold time 2.1 - - ns
td(QV) data output valid delay time - - 8.1 ns
th(Q) data output hold time 1.7 - - ns
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 27 for internal programmable delay.

Table 26. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2]
delays introduced by external device and PCB. Values based on simulation. tcmddly is programmable delay value for EMC
data sampling.
Symbol Parameter Min Typ Max Unit
For RD = 1
Common to read and write cycles
Tcy(clk) clock cycle time [1] 10 - - ns
td(SV) chip select valid delay time - - tcmddly + 4.9 ns
th(S) chip select hold time tcmddly + 2.4 - - ns
td(RASV) row address strobe valid - - tcmddly + 5.4 ns
delay time
th(RAS) row address strobe hold tcmddly + 2.5 - - ns
time
td(CASV) column address strobe valid - - tcmddly + 5.6 ns
delay time
th(CAS) column address strobe hold tcmddly + 2.6 - - ns
time
td(WV) write valid delay time - - tcmddly + 6.3 ns
th(W) write hold time tcmddly + 3.1 - - ns
td(AV) address valid delay time - - tcmddly + 6.1 ns
th(A) address hold time tcmddly + 2.4 - - ns
tsu(D) data input set-up time 0.5 - - ns
th(D) data input hold time 2.1 - - ns
td(QV) data output valid delay time - - 9.3 ns
th(Q) data output hold time 2.4 - - ns
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 27 for internal programmable delay.

EMC_CLKOUT0 Tcy(clk)
EMC_CLKOUT1
EMC_DYCSn,
EMC_RAS, td(xV) th(x)
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
td(QV) th(Q)
EMC_D[31:0]
write
tsu(D) th(D)
EMC_D[31:0]
read
aaa-024988
Fig 26. Dynamic external memory interface signal timing

Table 27. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY,
FBCLKDLY)
Tamb = −40 °C to 105 °C, VDD = 2.7 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC
data sampling.
Symbols Parameter Five bit value for each delay in EMCDLYCTL[1] Min Typ Max Unit
tcmddly, tfbdly delay time b00000 0.41 0.66 0.77 ns
b00001 0.52 0.85 1.03 ns
b00010 0.69 1.11 1.3 ns
b00011 0.8 1.3 1.56 ns
b00100 0.95 1.53 1.77 ns
b00101 1.06 1.72 2.03 ns
b00110 1.23 1.98 2.3 ns
b00111 1.34 2.17 2.56 ns
b01000 1.45 2.3 2.67 ns
b01001 1.56 2.49 2.93 ns
b01010 1.73 2.75 3.2 ns
b01011 1.84 2.94 3.46 ns
b01100 1.99 3.17 3.67 ns
b01101 2.1 3.36 3.93 ns
b01110 2.27 3.62 4.2 ns
b01111 2.38 3.81 4.46 ns
b10000 2.45 3.86 4.46 ns
b10001 2.56 4.05 4.72 ns
b10010 2.73 4.31 4.99 ns
b10011 2.84 4.5 5.25 ns
b10100 2.99 4.73 5.46 ns
b10101 3.1 4.92 5.72 ns
b10110 3.27 5.18 5.99 ns
b10111 3.38 5.37 6.25 ns
b11000 3.49 5.5 6.36 ns
b11001 3.6 5.69 6.62 ns
b11010 3.77 5.95 6.89 ns
b11011 3.88 6.14 7.15 ns
b11100 4.03 6.37 7.36 ns
b11101 4.14 6.56 7.62 ns
b11110 4.31 6.82 7.89 ns
b11111 4.42 7.01 8.15 ns
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0.

11.4 System PLL (PLL0)

Table 28. PLL lock times and current
Tamb = −40 °C to +105 °C, unless otherwise specified. VDD = 1.71 V to 3.6 V
PLL0 configuration: input frequency 12 MHz; output frequency 100 MHz
tlock(PLL0) PLL0 lock time [1] 96 s
IDD(PLL0) PLL0 current when locked [1][2] - - 2.0 mA
PLL0 configuration: input frequency 32 kHz; output frequency 100 MHz
tlock(PLL0) PLL0 lock time [1] - - 108 s
[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.
Table 29. Dynamic characteristics of the PLL0[1]

Reference clock input
Fin input frequency 32.768 kHz - 25 MHz
Clock output
fo output frequency for PLL0 clkout output [2] 4.3 - 550 MHz
do output duty cycle for PLL0 clkout output 46 - 54 %
fCCO CCO frequency 275 - 550 MHz
Lock detector output
lock(PFD) PFD lock criterion [3] 1 2 4 ns
Dynamic parameters at fout = fCCO = 540 MHz; standard bandwidth settings
Jrms-interval RMS interval jitter fref = 10 MHz [4][5] - 15 30 ps
Jpp-period peak-to-peak, period jitter fref = 10 MHz [4][5] - 40 80 ps

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.
[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
[4] Actual jitter dependent on amplitude and spectrum of substrate noise.
[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.5 USB PLL (PLL1)

Table 30. PLL1 lock times and current
tlock(PLL1) PLL1 lock time [1] - 7.4 - s
IDD(PLL1) PLL1 current When locked [1][2] - 260 - A


Fin input frequency 1 - 25 MHz
Clock output
fo output frequency for PLL1 clkout [2] 9.75 - 160 MHz
output
do output duty cycle for PLL1 clkout 45 - 55 %
output
Jpp-period peak-to-peak, period fref = 4 MHz [3][4] - - 300 ps
jitter
[1] Data based on simulation, not tested in production.

11.6 Audio PLL (PLL2)

Table 32. PLL2 lock times and current



Fin input frequency 1 - 25 MHz
Clock output
fo output frequency for PLL2 clkout [2] 4.3 - 550 MHz
output
do output duty cycle for PLL2 clkout 46 - 54 %
output
Lock detector output
lock(PFD) PFD lock criterion [3] 1 2 4 ns
Jrms-interval RMS interval jitter fref = 10 MHz [4][5] - 15 30 ps
Jpp-period peak-to-peak, period fref = 10 MHz [4][5] - 40 80 ps
jitter

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
11.7 FRO
The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.
Table 34. Dynamic characteristic: FRO

Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V.
fosc(RC) FRO clock frequency - 11.88 12 12.12 MHz
voltages.
11.8 Crystal oscillator

Table 35. Dynamic characteristic: oscillator
Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V.[1]
Low-frequency mode (1-20 MHz)[4]
tjit(per) period jitter time 5 MHz crystal [3] - 13.2 - ps
10 MHz crystal - 6.6 - ps

Table 35. Dynamic characteristic: oscillator …continued

Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V.[1]
High-frequency mode (20 - 25 MHz)[5]
tjit(per) period jitter time 20 MHz crystal [3] - 4.3 - ps
[1] Parameters are valid over operating temperature range unless otherwise specified.
voltages.
[3] Indicates RMS period jitter.
[4] Select Low Frequency range = 0 in the SYSOSCCTRL register.
[5] Select High Frequency = 1 in the SYSOSCCTRL register.
11.9 RTC oscillator

See Section 13.5 for connecting the RTC oscillator to an external clock source.
Table 36. Dynamic characteristic: RTC oscillator

Tamb = −40 °C to +105 °C; 1.71 ≤ VDD ≤ 3.6[1]
fi input frequency - - 32.768 - kHz
[1] Parameters are valid over operating temperature range unless otherwise specified.
voltages.

11.10 Watchdog oscillator

Table 37. Dynamic characteristics: Watchdog oscillator
Tamb = −40 °C to +105 °C; 1.71 ≤ VDD ≤ 3.6[1]
fosc(int) internal watchdog oscillator frequency [2] 200 - 1500 kHz
Dclkout clkout duty cycle 48 - 52 %
JPP-CC peak-peak period jitter [3][4] - 1 20 ns
tstart start-up time [4] - 4 - s
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.
[4] Guaranteed by design. Not tested in production samples.

11.11 I2C-bus
Table 38. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V.[2]
fSCL SCL clock frequency Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tf fall time [4][5][6][7] Both SDA and SCL signals - 300 ns
Standard-mode
Fast-mode 20 + 0.1  300 ns
Cb
Fast-mode Plus - 120 ns
tLOW LOW period of the SCL clock Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][4][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT data set-up time [9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
[1] Guaranteed by design. Not tested in production.

[2] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

tf tSU;DAT
70 % 70 %
SDA
30 % 30 %
tHD;DAT tVD;DAT
tf
tHIGH
70 % 70 % 70 % 70 %
SCL 30 % 30 %
30 % 30 %
tLOW
S 1 / fSCL
002aaf425
Fig 27. I2C-bus pins clock timing

11.12 I2S-bus interface

Table 39. Dynamic characteristics: I2S-bus interface pins [1][4]
Tamb = −40 °C to 105 °C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Common to master and slave
tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK  100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns
CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns
tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]
CCLK  100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns
CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns
Master; 1.71 V  VDD  2.7 V
tv(Q) data output valid time on pin I2Sx_TX_SDA [2]
CCLK  100 MHz 26.0 - 40.3 ns

CCLK > 100 MHz 25.0 - 39.0 ns
on pin I2Sx_WS
CCLK  100 MHz 26.0 - 41.0 ns
CCLK > 100 MHz 25.0 - 39.6 ns
tsu(D) data input set-up time on pin I2Sx_RX_SDA [2]
CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns
th(D) data input hold time on pin I2Sx_RX_SDA [2]
CCLK  100 MHz 6.1 - - ns

CCLK > 100 MHz 6.4 - - ns
Slave; 1.71 V  VDD  2.7 V
CCLK  100 MHz 18.8 - 37.1 ns

CCLK > 100 MHz 18.0 - 35.5 ns
CCLK  100 MHz 4.8 - - ns

CCLK > 100 MHz 4.4 - - ns
on pin I2Sx_WS
CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns
on pin I2Sx_WS
CCLK  100 MHz 3.2 - - ns
CCLK > 100 MHz 3.2 - - ns

Table 39. Dynamic characteristics: I2S-bus interface pins [1][4]

Tamb = −40 °C to 105 °C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
Master; 2.7 V  VDD  3.6 V
CCLK  100 MHz 21.4 - 30.4 ns

CCLK > 100 MHz 20.6 - 28.7 ns
on pin I2Sx_WS
CCLK  100 MHz 21.1 - 29 ns
CCLK > 100 MHz 20.3 - 28.3 ns
CCLK  100 MHz 1.3 - - ns

CCLK > 100 MHz 1.0 - - ns
CCLK  100 MHz 2.9 - - ns

CCLK > 100 MHz 3.3 - - ns
Slave; 2.7 V  VDD  3.6 V
CCLK  100 MHz 13.8 - 23.6 ns

CCLK > 100 MHz 13 - 21.9 ns
CCLK  100 MHz 4.7 - - ns

CCLK > 100 MHz 4.2 - - ns
on pin I2Sx_WS
CCLK  100 MHz 0.9 - - ns
CCLK > 100 MHz 0.7 - - ns
CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns
on pin I2Sx_WS
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.3 - - ns
[1] Based on characterization; not tested in production.

[2] Clock Divider register (DIV) = 0x0.
[3] Typical ratings are not guaranteed.
[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I2S chapter (UM11060) to calculate clock and sample rates.
[5] Based on simulation. Not tested in production.

Tcy(clk) tf tr
I2Sx_SCK
tWH tWL
I2Sx_TX_SDA
tv(Q)
I2Sx_RX_SDA
tsu(D) th(D)
I2Sx_WS
tv(Q) aaa-026799
Fig 28. I2S-bus timing (master)
Tcy(clk) tf tr
I2Sx_SCK
tWH tWL
I2Sx_TX_SDA
tv(Q)
I2Sx_RX_SDA
tsu(D) th(D)
I2Sx_WS
tsu(D) th(D) aaa-026800
Fig 29. I2S-bus timing (slave)

11.13 SPI interfaces (Flexcomm Interface 0-9)

The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.
Table 40. SPI dynamic characteristics[1]

Tamb = −40 °C to 105 °C; 1.71 V ≤ VDD ≤ 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.
SPI master 1.71 V  VDD  2.7 V
tDS data set-up time CCLK  100 MHz 2.2 - - ns
CCLK > 100 MHz 1.9 - - ns
tDH data hold time CCLK  100 MHz 6.3 - - ns
CCLK > 100 MHz 6.7 - - ns
tv(Q) data output valid time CCLK  100 MHz 2.6 - 5.0 ns
CCLK > 100 MHz 0.3 - 4.7 ns
SPI slave 1.71 V  VDD  2.7 V
CCLK > 100 MHz 0.9 - - ns
CCLK > 100 MHz 2.2 - - ns
CCLK > 100 MHz 18.0 - 36.0 ns
SPI master 2.7 V  VDD  3.6 V
CCLK > 100 MHz 2.2 - - ns
CCLK > 100 MHz 4.5 - - ns
CCLK > 100 MHz 1.7 - 4.0 ns
SPI slave 2.7 V  VDD  3.6 V
CCLK > 100 MHz 1.0 - - ns
tDH data hold time CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
tv(Q) data output valid time CCLK  100 MHz 14 - 23.9 ns
CCLK > 100 MHz 13.3 - 22.2 ns

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
MOSI (CPHA = 0) tv(Q) tv(Q)
DATA VALID (MSB) DATA VALID DATA VALID (LSB) IDLE DATA VALID (MSB)
tDS tDH
MISO (CPHA = 0)
DATA VALID (LSB) DATA VALID DATA VALID (MSB) IDLE DATA VALID (MSB)
MISO (CPHA = 1) tDS tDH
aaa-014969
Fig 30. SPI master timing

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
MISO (CPHA = 0) tv(Q) tv(Q)
tDS tDH
MOSI (CPHA = 0)
MOSI (CPHA = 1) tDS tDH
aaa-014970
Fig 31. SPI slave timing

11.14 SPI interfaces (Flexcomm Interface 10)

The actual SPI bit rate depends on the delays introduced by the external trace, the
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 50 Mbit/s, and the maximum supported bit rate for SPI slave mode is 50 Mbit/s.
Table 41. SPI dynamic characteristics[1]

Tamb = −40 °C to 105 °C; 1.71 V ≤ VDD ≤ 3.6 V; CL = 30 pF balanced loading on all pins; Input slew
= 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the
rising or falling edge.
SPI master
tDS data set-up time 0 - - ns
tDH data hold time 10.0 - - ns
tv(Q) data output valid time 0.8 - 10.0 ns
SPI slave
tDS data set-up time 1.2 - - ns
tDH data hold time 10.0 - - ns
tv(Q) data output valid time 4.28 - 10.0 ns

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
tDS tDH
MISO (CPHA = 0)
MISO (CPHA = 1) tDS tDH
aaa-014969
Fig 32. SPI master timing

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
SSEL
tDS tDH
MOSI (CPHA = 0)
MOSI (CPHA = 1) tDS tDH
aaa-014970
Fig 33. SPI slave timing

11.15 SPIFI
The actual SPIFI bit rate depends on the delays introduced by the external trace, the
introduced by external device and PCB, at 1.8 V, the maximum supported bit rate for
SPIFI mode is 300 Mbit/s in quad mode and 75 Mbit/s in single-bit mode (based on
interfacing with a device requiring a 2 ns data input set-up time). Excluding delays
introduced by external device and PCB, at 3.3 V, the maximum supported bit rate for
SPIFI mode is 400 Mbit/s in quad mode and 100 Mbit/s in single-bit mode (based on
interfacing with a device requiring a 2 ns data input set-up time).
Table 42. Dynamic characteristics: SPIFI [1]

Tamb = −40 °C to 105 °C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
SPIFI 1.71 V  VDD  2.7 V
tDS data set-up time [2] CCLK  100 MHz 4 - - ns
CCLK > 100 MHz 4 - - ns
tDH data hold time [2] CCLK  100 MHz 1.0 - - ns
CCLK > 100 MHz 1.0 - - ns
tv(Q) data output valid time CCLK  100 MHz - - 4.5 ns
CCLK > 100 MHz - - 4.5 ns
SPIFI 2.7 V  VDD  3.6 V
tDS data set-up time [2] CCLK  100 MHz 4 - - ns
CCLK > 100 MHz 4 - - ns
tDH data hold time [2] CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
tv(Q) data output valid time CCLK  100 MHz - - 3.0 ns
CCLK > 100 MHz - - 3.0 ns
[1] Based on simulation; not tested in production.

[2] tDS and tDH above are the same for RFCLK = 0 or 1 (data latched on SPIFI_CLK rising or falling edge
respectively).

Tcy(clk)
SPIFI_SCK
tv(Q) th(Q)
SPIFI data out DATA VALID DATA VALID
tDS tDH
SPIFI data in DATA VALID DATA VALID
002aah409
In mode 0, MODE3 bit (23) in SPIFI CTRL register is set to '0' (default). The SPIFI drives SCK low
after the rising edge at which the last bit of each command is captured, and keeps it LOW while CS
is HIGH. The signal SPIFI data above shows timing for RFCLK = 0.
Fig 34. SPIFI timing diagram

11.16 DMIC subsystem

Table 43. Dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 2.7 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Bypass bit = 0; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
CCLK > 100 MHz 14.3 - - ns
CCLK > 100 MHz 0 - - ns
[1] Based on simulated values.
CLOCK
tDH
tSU
DATA
aaa-017025
Fig 35. DMIC timing diagram
11.17 Smart card interface

Table 44. Dynamic characteristics[1]
Tamb = −40 °C to 105 °C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
2.7 V  VDD  3.6 V
CCLK > 100 MHz 2.1 - - ns
CCLK > 100 MHz 0 - - ns
CCLK > 100 MHz 11.0 - 22.5 ns
[1] Based on simulated values. VDD = 2.7 V - 3.6 V.

11.18 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the
introduced by external device and PCB, the maximum supported bit rate for USART
master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART
slave synchronous mode is 12.5 Mbit/s.
Table 45. USART dynamic characteristics[1]

Tamb = −40 °C to 105 °C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
USART master (in synchronous mode) 1.71 V  VDD  2.7 V
tsu(D) data input set-up time CCLK  100 MHz 21.2 - - ns
CCLK > 100 MHz 19.7 - - ns
th(D) data input hold time CCLK  100 MHz 0 - - ns
CCLK > 100 MHz 0 - - ns
tv(Q) data output valid time CCLK  100 MHz 0 - 4.9 ns
CCLK > 100 MHz 0 - 4.5 ns
USART slave (in synchronous mode)1.71 V  VDD  2.7 V
CCLK > 100 MHz 1.5 - - ns
th(D) data input hold time CCLK  100 MHz 1.2 - - ns
CCLK > 100 MHz 1.4 - - ns
CCLK > 100 MHz 19.3 - 37.7 ns
USART master (in synchronous mode) 2.7 V  VDD  3.6 V
CCLK > 100 MHz 18.9 - - ns
CCLK > 100 MHz 0 - - ns
CCLK > 100 MHz 1.3 - 3.2 ns
USART slave (in synchronous mode) 2.7 V  VDD  3.6 V
CCLK > 100 MHz 1 - - ns
CCLK > 100 MHz 0 - - ns
CCLK > 100 MHz 14.3 - 24.2 ns

Tcy(clk)
Un_SCLK (CLKPOL = 0)
Un_SCLK (CLKPOL = 1)
tv(Q) tvQ)
TXD START BIT0 BIT1
tsu(D) th(D)
RXD START BIT0 BIT1
aaa-015074
Fig 36. USART timing
11.19 SCTimer/PWM output timing

Table 46. SCTimer/PWM output dynamic characteristics
Tamb = −40 °C to 105 °C; 1.71 V ≤ VDD ≤ 3.6 V CL = 30 pF. Simulated skew (over process, voltage, and temperature) of any
two SCT fixed-pin output signals; sampled at the 90 % and 10 % level of the rising or falling edge; values guaranteed by
design.
tsk(o) output skew time - 3.4 - 4.5 ns
11.20 USB interface characteristics

Table 47. Dynamic characteristics: USB0 pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD, unless otherwise specified; 3.0 V ≤ VDD ≤ 3.6 V.
tr rise time 10 % to 90 % 4.0 20 ns
tf fall time 10 % to 90 % 4.0 20 ns
tFRFM differential rise and fall time matching tr / tf 90 111.11 %
VCRS output signal crossover voltage 1.3 2.0 V
tFEOPT source SE0 interval of EOP see Figure 37 160 175 ns
tFDEOP source jitter for differential transition see Figure 37 2 +5 ns
to SE0 transition
tJR1 receiver jitter to next transition 18.5 +18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns
tEOPR1 EOP width at receiver must reject as [1] 40 - ns
EOP; see
Figure 37
tEOPR2 EOP width at receiver must accept as [1] 82 - - ns
EOP; see
Figure 37
[1] Characterized but not implemented as production test. Guaranteed by design.

11.21
TPERIOD crossover point

extended
crossover point
differential
data lines
source EOP width: tFEOPT

differential data to
SE0/EOP skew
n TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 37. Differential data-to-EOP transition skew and EOP width
11.22 Ethernet AVB

Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply
with the IEEE standard 802.3.
Table 48. Dynamic characteristics: Ethernet

Tamb = −40 °C to 105 °C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
RMII mode
fclk clock frequency for ENET_RX_CLK [1] - - 50.0 MHz
clk clock duty cycle [1] 45.0 - 55.0 %
tsu data input set-up ENET_RXDn, ENET_RX_ER, ENET_RX- [1][2]
time _DV
CCLK  100 MHz 4.4 - - ns
CCLK > 100 MHz 4.4 - - ns
th data input hold time for ENET_RXDn, ENET_RX_ER, [1][2]
ENET_RX_DV
CCLK  100 MHz 1.3 - 0 ns
CCLK > 100 MHz 1.3 - 0 ns
tv(Q) data output valid for ENET_TXDn, ENET_TX_EN [1][2]
time CCLK  100 MHz 9.9 - 17.3 ns

CCLK > 100 MHz 9.9 - 17.3 ns
MII mode
fclk clock frequency for ENET_TX_CLK [1] - - 25.0 MHz
fclk clock frequency for ENET_RX_CLK [1] - - 25.0 MHz
tsu data input set-up for ENET_RXDn, ENET_RX_ER, [1][2]
time ENET_RX_DV
CCLK  100 MHz 4.7 - - ns
CCLK > 100 MHz 4.7 - - ns

Table 48. Dynamic characteristics: Ethernet

Tamb = −40 °C to 105 °C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
th data input hold time for ENET_RXDn, ENET_RX_ER, [1][2]
ENET_RX_DV
CCLK  100 MHz 1.2 - 0 ns
CCLK > 100 MHz 1.2 - 0 ns
tv(Q) data output valid for ENET_TXDn, ENET_TX_EN, [1][2]
time ENET_TX_ER
CCLK  100 MHz 10.0 - 18.2 ns
CCLK > 100 MHz 10.0 - 18.2 ns
[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
ENET_RX_CLK
tv(Q)
ENET_TX_EN
ENET_TXDn
tsu th
ENET_RXDn
ENET_RX_DV
aaa-025108
Fig 38. Ethernet RMII timing
ENET_RX_CLK
tsu th
ENET_RXDn
ENET_RX_DV
ENET_RX_ER
ENET_TX_CLK
tv(Q)
ENET_TX_EN
ENET_TXDn
aaa-025109
Fig 39. Ethernet MII timing

11.23 SD/MMC and SDIO

Table 49. Dynamic characteristics: SD/MMC and SDIO
Tamb = −40 °C to +105 °C, VDD = 2.7 V to 3.6 V; CL = 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY
register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns
for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.
fclk clock frequency on pin SD_CLK; data transfer mode - - 50 MHz
tsu(D) data input set-up time on pins SD_DATn as inputs
CCLK  100 MHz 14.4 - - ns
CCLK > 100 MHz 14.4 - - ns
on pins SD_CMD as inputs
CCLK  100 MHz 14.4 - - ns
CCLK > 100 MHz 14.4 - - ns
th(D) data input hold time on pins SD_DATn as inputs
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.5 - - ns
on pins SD_CMD as inputs
CCLK  100 MHz 1.5 - - ns
CCLK > 100 MHz 1.5 - - ns
tv(Q) data output valid time on pins SD_DATn as outputs
CCLK  100 MHz 1.9 - 3.5 ns
CCLK > 100 MHz 1.9 - 3.5 ns
on pins SD_CMD as outputs
CCLK  100 MHz 1.9 - 3.5 ns
CCLK > 100 MHz 1.9 - 3.5 ns
Tcy(clk)
SD_CLK
td(QV) th(Q)
SD_CMD (O)
SD_DATn (O)
tsu(D) th(D)
SD_CMD (I)
SD_DATn (I)
002aag204
Fig 40. SD/MMC and SDIO timing

11.24 LCD
Table 50. Dynamic characteristics: LCD
Tamb = −40 °C to 105 °C; VDD = 2.7 V to 3.6 V; CL = 30 pF. Simulated values.
fclk clock frequency on pin LCD_DCLK - - 50 MHz
tv(Q) data output valid time on all CCLK  100 MHz 0.9 - 1.6 ns
LCD output pins CCLK > 100 MHz 0.9 - 1.6 ns

12. Analog characteristics
12.1 BOD
Table 51. BOD static characteristics
Tamb = 25 °C; based on characterization; not tested in production.
Vth threshold voltage interrupt level 0
assertion 1.5 - 1.63 V
de-assertion 1.55 - 1.69 V
reset level 0
reset level 1
reset level 2
reset level 3

12.2 12-bit ADC characteristics

Table 52. 12-bit ADC static characteristics
Tamb = −40 °C to +105 °C; 1.71 V ≤ VDD ≤ 3.6 V; VSSA = VREFN = GND. ADC calibrated at Tamb = 25 °C.
VIA analog input [3] 0 - VDDA V

voltage
Cia analog input [4] - 5.0 - pF
capacitance
fclk(ADC) ADC clock - 80 MHz
frequency
fs sampling - 5.0 5.3 Msamples/s
frequency
ED differential linearity 2.0 V  VDDA  3.6 V [1][5] - 3.0 - LSB
error 2.0 V < VREFP  3.6 V
fclk(ADC) = 80 MHz
1.71 V  VDDA  2.0 V [1][5] - 4.5 - LSB
1.71 V  VREFP  2.0 V
fclk(ADC) = 80 MHz
[1][5] - - LSB
EL(adj) integral 2.0 V  VDDA  3.6 V [1][6] - 4.0 - LSB
non-linearity 2.0 V < VREFP  3.6 V
fclk(ADC) = 80 MHz
1.71 V  VDDA  2.0 V [1][6] - 7.5 - LSB
1.71 V  VREFP  2.0 V
fclk(ADC) = 80 MHz
[1][6] - - LSB
EO offset error calibration enabled [1][7] - 2.2 - mV
Verr(FS) full-scale error 2.0 V  VDDA  3.6 V [1][8] - 3.0 - LSB
voltage 2.0 V < VREFP  3.6 V
fclk(ADC) = 80 MHz
1.71 V  VDDA  2.0 V - 2.5 - LSB
1.71 V  VREFP  2.0 V
fclk(ADC) = 80 MHz
Zi input impedance fs = 5.0 Msamples/s [9][10] 17.0 - - k

voltages.
[3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.
[4] Cia represents the external capacitance on the analog input channel for sampling speeds of
5.0 Msamples/s. No parasitic capacitances included.
[5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 41.
[6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 41.
[7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 41.

[8] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 41.
[9] Tamb = 25 C; maximum sampling frequency fs = 5.0 Msamples/s and analog input capacitance Cia = 5 pF.
[10] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including
Cia and Cio: Zi  1 / (fs  Ci). See Table 20 for Cio. See Figure 42.
offset gain
error error
EO EG
4095
4094
4093
4092
4091
4090
(2)
7
code (1)
out
6
(5)
4
(4)
3
(3)
2
1 1 LSB
(ideal)
0
1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096
VIA (LSBideal)
offset error
EO VREFP - VREFN
1 LSB =
4096
aaa-016908
(1) Example of an actual transfer curve.

(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 41. 12-bit ADC characteristics

Table 53. ADC sampling times[1]

-40 °C ≤ Tamb <= 85 °C; 1.71 V ≤ VDDA ≤ 3.6 V; 1.71 V ≤ VDD ≤ 3.6 V
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit
ts sampling time Zo < 0.05 kΩ [3] 20 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 23 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 26 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 31 - - ns
0.5 kΩ <= Zo < 1 kΩ 47 - - ns
1 kΩ <= Zo < 5 kΩ 75 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 18 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 20 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 24 - - ns
0.5 kΩ <= Zo < 1 kΩ 38 - - ns
1 kΩ <= Zo < 5 kΩ 62 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 13 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 15 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 19 - - ns
0.5 kΩ <= Zo < 1 kΩ 30 - - ns
1 kΩ <= Zo < 5 kΩ 48 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 10 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 11 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 13 - - ns
0.5 kΩ <= Zo < 1 kΩ 22 - - ns
1 kΩ <= Zo < 5 kΩ 36 - - ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit
0.05 kΩ <= Zo < 0.1 kΩ 46 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 50 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 56 - - ns
0.5 kΩ <= Zo < 1 kΩ 74 - - ns
1 kΩ <= Zo < 5 kΩ 105 - - ns

Table 53. ADC sampling times[1] …continued

-40 °C ≤ Tamb <= 85 °C; 1.71 V ≤ VDDA ≤ 3.6 V; 1.71 V ≤ VDD ≤ 3.6 V
0.05 kΩ <= Zo < 0.1 kΩ 38 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 40 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 46 - - ns
0.5 kΩ <= Zo < 1 kΩ 61 - - ns
1 kΩ <= Zo < 5 kΩ 86 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 29 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 32 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 36 - - ns
0.5 kΩ <= Zo < 1 kΩ 48 - - ns
1 kΩ <= Zo < 5 kΩ 69 - - ns
0.05 kΩ <= Zo < 0.1 kΩ 22 - - ns
0.1 kΩ <= Zo < 0.2 kΩ 23 - - ns
0.2 kΩ <= Zo < 0.5 kΩ 26 - - ns
0.5 kΩ <= Zo < 1 kΩ 36 - - ns
1 kΩ <= Zo < 5 kΩ 51 - - ns
[1] Characterized through simulation. Not tested in production.

[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output
impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum
sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.
[3] Zo = analog source output impedance.
[4] For VDD  2.5 V, add one additional clock cycle to the values in Table 53.
12.2.1 ADC input impedance

Figure 42 shows the ADC input impedance. In this figure:
• ADCx represents slow ADC input channels 6 to 11.

• ADCy represents fast ADC input channels 0 to 5.
• R1 and Rsw are the switch-on resistance on the ADC input channel.
• If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through
Rsw to the sampling capacitor (Cia).
• If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through
R1 + Rsw to the sampling capacitor (Cia).
• Typical values, R1 = 487 , Rsw = 278 
• See Table 20 for Cio.
• See Table 52 for Cia.

ADC
R1
ADCx
Cio
Cia Rsw
DAC ADCy
Cio
aaa-017600
Fig 42. ADC input impedance
12.3 Temperature sensor
Table 54. Temperature sensor static and dynamic characteristics

VDD = VDDA = 1.71 V to 3.6 V
DTsen sensor Tamb = 40 C to +105 C [1] - 2.56 C
temperature
accuracy
EL linearity error Tamb = 40 C to +105 C - - 2.56 C
ts(pu) power-up to 99% of temperature [2] - 10.0 15.0 s
settling time sensor output value
[1] Absolute temperature accuracy.

[2] Based on simulation.

Table 55. Temperature sensor Linear-Least-Square (LLS) fit parameters

VDD = VDDA = 1.71 V to 3.6 V
Fit parameter Range Min Typ Max Unit
LLS slope Tamb = 40 C to +105 C [1] - 2.04 - mV/C
LLS intercept at 0 C Tamb = 40 C to +105 C [1] - 584.0 - mV
Value at 30 C [2] 520.3 - 532.7 mV
[1] Measured over typical samples.

[2] Measured for samples over process corners.
aaa-025693
800
Vo
(mV)
LLS fit
600
400
200
0
-40 -10 20 50 80 110
Temperature (°C)
VDD = VDDA 3.3 V; measured on matrix samples.

Fig 43. LLS fit of the temperature sensor output voltage

13. Application information
13.1 Start-up behavior

Figure 44 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the
default clock at Reset and provides a clean system clock shortly after the supply pins
reach operating voltage.
FRO
starts
FRO status
internal reset
VDD
valid threshold
= 1.71 V
ta μs tb μs
GND
supply ramp-up boot time

time
user code
tc μs
processor status
boot code
execution
finishes;
user code starts
aaa-024049
Fig 44. Start-up timing
Table 56. Typical start-up timing parameters

Parameter Description Value
ta FRO start time  20 s
tb Internal reset de-asserted 151 s

13.2 Standard I/O pin configuration

Figure 45 shows the possible pin modes for standard I/O pins:
• Digital output driver: enabled/disabled.

• Digital input: Pull-up enabled/disabled.
• Digital input: Pull-down enabled/disabled.
• Digital input: Repeater mode enabled/disabled.
• Z mode; High impedance (no cross-bar currents for floating inputs).
For initial device revision 0A (Boot ROM version 21.0), the default configuration for the
standard I/O pins is PU mode (input mode, pull-up enabled, pull-up resistor pulls up pin to
VDD). For future device revision 1B (Boot ROM version 21.1), the default configuration for
the standard I/O pins is Z mode (high impedance; pull-up or pull-down disabled). See the
Errata sheet LPC540xx/LPC54S0xx (IOCON.1) for more details. The weak MOS devices
provide a drive capability equivalent to pull-up and pull-down resistors. For future device
revision 1B (Boot ROM version 21.1), GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3,
PIO0_4, PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled
in IOCON register) and will be floating by default. If unused, it is recommended to
externally terminate this pins to prevent leakage.
VDD
ESD
enable output driver
data output from core PIN
slew rate bit SLEW
input buffer enable bit EZI
data input to core

GLITCH
FILTER
filter select bit ZIF
ESD
pull-up enable bit EPUN
pull-down enable bit EPD
analog I/O
VSS aaa-015595
The glitch filter rejects pulses of typical 12 ns width.

Fig 45. Standard I/O and RESET pin configuration

13.3 Connecting power, clocks, and debug functions

Figure 46 shows the basic board connections used to power the LPC540xx/LPC54S0xx
devices, connect the external crystal and the 32 kHz oscillator for the RTC, and provide
debug capabilities via the serial wire port.

3.3 V 3.3 V
SWD connector
(4) (6)
~10 kΩ - 100 kΩ
XTALIN
SWDIO/PIO0_12
1 2 C1 (1)
3.3 V
XTALOUT C2
DGND
~10 kΩ - 100 kΩ
SWCLK/PIO0_11
3 4
(6) RTCXIN
5 6 n.c. C3
(1)
n.c. 7 8 n.c. RTCXOUT C4

DGND
RESETN
9 10
VSS
(2)
VDD
3.3 V
DGND 0.1 μF 0.01 μF

DGND
VSSA
DGND
LPC
AGND (3)
VDDA
3.3 V
PIO0_4
0.1 μF 10 μF
PIO0_5
ISP select pins
PIO0_6 DGND
(3)
VREFP
ADCx 3.3 V
(5)
0.1 μF 0.1 μF 10 μF
VREFN
AGND AGND
(7)
VBAT
3.3 V
0.1 μF
AGND DGND
DGND
aaa-029082
(1) See Section 13.6 “XTAL oscillator” for the values of C1, C2, C3, and C4.
(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling
capacitors to each VDD pin.
(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDDA pins. The 10 μF bypass capacitor
filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.
(4) Uses the ARM 10-pin interface for SWD.
(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see
Ref. 3.
(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by
default on initial device revision 0A (Boot ROM version 21.0). For future device revision 1B (Boot ROM version 21.1), these pins
are in high Z mode (internal pull-up and pull-down disabled). See the Errata sheet LPC540xx/LPC54S0xx (IOCON.1) for more
details. For future device revision 1B (Boot ROM version 21.1), GPIO pins SWDIO/PIO0_12, SWCLK/PIO0_11, PIO0_2,
PIO0_3, PIO0_4, PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will
be floating by default. If unused, it is recommended to externally terminate this pins to prevent leakage.
(7) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used.
Fig 46. Power, clock, and debug connections

13.4 I/O power consumption

I/O pins are contributing to the overall dynamic and static power consumption of the part.
If pins are configured as digital inputs, a static current can flow depending on the voltage
level at the pin and the setting of the internal pull-up and pull-down resistors. This current
can be calculated using the parameters Rpu and Rpd given in Table 20 for a given input
voltage VI. For pins set to output, the current drive strength is given by parameters IOH and
IOL in Table 20, but for calculating the total static current, you also need to consider any
external loads connected to the pin.
I/O pins also contribute to the dynamic power consumption when the pins are switching
because the VDD supply provides the current to charge and discharge all internal and
external capacitive loads connected to the pin in addition to powering the I/O circuitry.
The contribution from the I/O switching current Isw can be calculated as follows for any
given switching frequency fsw if the external capacitive load (Cext) is known (see Table 20
for the internal I/O capacitance):
Isw = VDD x fsw x (Cio + Cext)

13.5 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2
need to be connected externally on RTCXIN and RTCXOUT. See Figure 47.
LPC
L
RTCXIN RTCXOUT
= CL CP
XTAL
RS
CX1 CX2
aaa-029083
Fig 47. RTC oscillator components
For best results, it is very critical to select a matching crystal for the on-chip oscillator.
Load capacitance (CL), series resistance (RS), and drive level (DL) are important
parameters to consider while choosing the crystal. After selecting the proper crystal, the
external load capacitor CX1 and CX2 values can also be generally determined by the
following expression:
CX1 = CX2 = 2CL  (CPad + CParasitic)
Where:
CL - Crystal load capacitance

CPad - Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).
CParasitic – Parasitic or stray capacitance of external circuit.
Although CParasitic can be ignored in general, the actual board layout and placement of
external components influences the optimal values of external load capacitors. Therefore,
it is recommended to fine tune the values of external load capacitors on actual hardware
board to get the accurate clock frequency. For fine tuning, output the RTC Clock to the
CLOCKOUT pin and optimize the values of external load capacitors for minimum
frequency deviation.

13.5.1 RTC Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to
the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must
not cross other signal lines.
• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal
usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through
the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.

13.6 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2
need to be connected externally on XTALIN and XTALOUT. See Figure 48.
LPCxxxx
XTALIN XTALOUT
= CL CP
XTAL
RS
CX1 CX2
aaa-025725
Fig 48. XTAL oscillator components
For best results, it is very critical to select a matching crystal for the on-chip oscillator.
Load capacitance (CL), series resistance (RS), and drive level (DL) are important
parameters to consider while choosing the crystal. After selecting the proper crystal, the
external load capacitor CX1 and CX2 values can also be generally determined by the
following expression:
CX1 = CX2 = 2CL  (CPad + CParasitic)
Where:
CL - Crystal load capacitance

CPad - Pad capacitance of the XTALIN and XTALOUT pins (~3 pF).
CParasitic – Parasitic or stray capacitance of external circuit.
Although CParasitic can be ignored in general, the actual board layout and placement of
external components influences the optimal values of external load capacitors. Therefore,
it is recommended to fine tune the values of external load capacitors on actual hardware
board to get the accurate clock frequency. For fine tuning, measure the clock on the
XTALOUT pin and optimize the values of external load capacitors for minimum frequency
deviation.

13.6.1 XTAL Printed Circuit Board (PCB) design guidelines

• Connect the crystal and external load capacitors on the PCB as close as possible to
the oscillator input and output pins of the chip.
• The length of traces in the oscillation circuit should be as short as possible and must
not cross other signal lines.
• Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal
usage, have a common ground plane.
• Loops must be made as small as possible to minimize the noise coupled in through
the PCB and to keep the parasitics as small as possible.
• Lay out the ground (GND) pattern under crystal unit.
• Do not lay out other signal lines under crystal unit for multi-layered PCB.
13.7 Suggested USB Full-speed interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 49) or
bus-powered device (see Figure 50).
On the LPC540xx/LPC54S0xx, the USB_VBUS pin is 5 V tolerant only when VDD is

applied and at operating voltage level. Therefore, if the USB_VBUS function is connected
to the USB connector and the device is self-powered, the USB_VBUS pin must be
protected for situations when VDD = 0 V.
If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be
connected directly to the VBUS pin on the USB connector.
For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,
precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum
allowable voltage on the USB_VBUS pin in this case.
One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin is
greater than 0.7 VDD to indicate a logic HIGH while below the 3.6 V allowable maximum
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDD = 3.6 V,
the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

LPCxxxx
VDD
R2
R3
R1
USB 1.5 kΩ
USB_VBUS
D+
USB_DP RS = 33 Ω USB-B
D-
connector
USB_DM RS = 33 Ω
VSS
aaa-023996
Fig 49. USB interface on a self-powered device where USB_VBUS = 5 V
The internal pull-up (1.5 k) can be enabled by setting the DCON bit in the
DEVCMDSTAT register to prevent the USB from timing out when there is a significant
delay between power-up and handling USB traffic. External circuitry is not required.
LPCxxxx
VDD
REGULATOR
USB USB_VBUS(1)
R1
1.5 kΩ USB_VBUS(2) VBUS
D+
USB_DP RS = 33 Ω USB-B
D-
connector
USB_DM RS = 33 Ω
VSS
aaa-023997
Two options exist for connecting VBUS to the USB_VBUS pin:

(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.
(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin
while the regulator is ramping up to supply VDD. Since the USB_VBUS pin is only 5 V tolerant when VDD is at operating level,
this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years
at Tamb = 45 °C and 8 years at Tamb = 55 °C assuming that USB_VBUS = 5 V is applied continuously while VDD = 0 V.
Fig 50. USB interface on a bus-powered device
13.8 USB1 High-speed VBUS threshold levels

The USB1 has the following characteristics for VBUS (see Table 59). The USB1_VBUS
can tolerate an input voltage of 5.5 V.

Table 57. USB1 High-speed VBUS threshold levels

Function Min Typ Max Unit
Votg_sess_valid 0.8 - 4.0 V
VBUS_valid 4.192 - 5.5 V
Vadp_probe 0.6  0.8 V
Vadp_sense 0.20  0.55 V

14. Package outline
LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
c
y
X
A
105
156
157 104
ZE
E HE
A A2 A1 (A 3)
wM
bp Lp
L
pin 1 index detail X
53
208
1 52
wM ZD v M A
e bp
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y ZD ZE
max.
o
0.15 1.45 0.27 0.20 28.1 28.1 30.15 30.15 0.75 1.43 1.43 7
mm 1.6 0.25 0.5 1 0.12 0.08 0.08 o
0.05 1.35 0.17 0.09 27.9 27.9 29.85 29.85 0.45 1.08 1.08 0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
00-02-06
SOT459-1 136E30 MS-026
03-02-20
Fig 51. LQFP208 package

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
c
y
X
A
75 51
76 50
ZE
E HE A A2 (A 3)
A1
w M
bp
Lp
pin 1 index L
100 detail X
26
1 25
ZD v M A
e w M
bp
D B
HD v M B
0 5 10 mm
scale

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1)
mm 1.6
0.15 1.45 0.27 0.20 14.1 14.1 16.25 16.25 0.75 1.15 1.15 7o
0.25 0.5 1 0.2 0.08 0.08 o
0.05 1.35 0.17 0.09 13.9 13.9 15.75 15.75 0.45 0.85 0.85 0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

ISSUE DATE
00-02-01
SOT407-1 136E20 MS-026
03-02-20
Fig 52. LQFP100 package

TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3
D B A
ball A1
index area
A2
E A
A1
detail X
e1
C
v M C A B
e 1/2 e b
w M C y1 C y
P
N
M
L
e
K
J
H
e2
G
F
E
1/2 e
D
C
B
A
ball A1 1 3 5 7 9 11 13
index area 2 4 6 8 10 12 14 X
0 5 10 mm
scale
UNIT A A1 A2 b D E e e1 e2 v w y y1
max 1.20 0.40 0.80 0.50 12.1 12.1

mm nom 1.06 0.35 0.71 0.45 12.0 12.0 0.8 10.4 10.4 0.15 0.05 0.12 0.1
min 0.95 0.30 0.65 0.40 11.9 11.9

ISSUE DATE
08-07-09
SOT570-3
10-04-15
Fig 53. TFBGA180 package

TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm SOT926-1
D B A
ball A1
index area
A2
E A
A1
detail X
e1
C
v M C A B
e 1/2 e b
w M C y1 C y
J
e
H
F
e2
E
D 1/2 e
C
ball A1
index area 1 2 3 4 5 6 7 8 9 10
0 2.5 5 mm
scale
UNIT A A1 A2 b D E e e1 e2 v w y y1
max
0.4 0.8 0.5 9.1 9.1
mm 1.2 0.8 7.2 7.2 0.15 0.05 0.08 0.1
0.3 0.65 0.4 8.9 8.9

ISSUE DATE
05-12-09
SOT926-1 --- --- ---
05-12-22
Fig 54. TFBGA100 package

15. Soldering
Footprint information for reflow soldering of LQFP208 package SOT459-1
Hx
Gx
P2 P1 (0.125)
Hy Gy By Ay
D2 (8 ) D1
Bx
Ax
Generic footprint pattern

Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
0.500 0.560 31.300 31.300 28.300 28.300 1.500 0.280 0.400 28.500 28.500 31.550 31.550
sot459-1_fr
Fig 55. Reflow soldering of the LQFP208 package

Footprint information for reflow soldering of LQFP100 package SOT407-1
Hx
Gx
P2 P1 (0.125)
Hy Gy By Ay
D2 (8 ) D1
Bx
Ax

solder land
occupied area
DIMENSIONS in mm
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550
sot407-1
Fig 56. Reflow soldering of the LQFP100 package

Footprint information for reflow soldering of TFBGA180 package SOT570-3
Hx
Hy
see detail X

solder land
solder paste deposit
solder land plus solder paste

SL
occupied area SP
SR
solder resist
detail X
DIMENSIONS in mm
P SL SP SR Hx Hy
0.80 0.400 0.400 0.550 12.575 12.575

sot570-3_fr
Fig 57. Reflow soldering of the TFBGA180 package

Footprint information for reflow soldering of TFBGA100 package SOT926-1
Hx
Hy
see detail X

solder land
solder paste deposit
solder land plus solder paste

SL
occupied area SP
SR
solder resist
detail X
DIMENSIONS in mm
P SL SP SR Hx Hy
0.80 0.330 0.400 0.480 9.400 9.400

sot926-1_fr
Fig 58. Reflow soldering of the TFBGA100 package

16. Abbreviations
Table 58. Abbreviations
Acronym Description
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
API Application Programming Interface
DMA Direct Memory Access
FRO oscillator Internal Free-Running Oscillator, tuned to the factory specified frequency
GPIO General Purpose Input/Output
FRO Free Running Oscillator
LSB Least Significant Bit
MCU MicroController Unit
PDM Pulse Density Modulation
PLL Phase-Locked Loop
SPI Serial Peripheral Interface
TCP/IP Transmission Control Protocol/Internet Protocol
TTL Transistor-Transistor Logic
USART Universal Asynchronous Receiver/Transmitter
17. References
[1] LPC540xx/LPC54S0xx. User manual UM11060.
[2] LPC540xx/LPC54S0xx. Errata sheet.
[3] Technical note ADC design guidelines:
http://www.nxp.com/documents/technical_note/TN00009.pdf

18. Revision history

Table 59. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC540xx/LPC54S0xx v.2.1 20200915 Product data sheet - v.2.0
Modifications: Updated Table 15 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”
Modifications: • Updates various information including Table 42 “Dynamic characteristics: SPIFI [1]”.
Modifications: • Added LPC54S0xx parts
Modifications: • Updated Table 4 “Pin description”: Added text to USB1_VBUS.
• Updated Table 12 “General operating conditions”: Added VDD for USB high-speed
operation only. Changed USB operation to: For USB full-speed operation only. Added
USB1 analog supply.
• Updated Section 7.12.2 “Deep-sleep mode”: Added text: In deep-sleep mode, the
system clock to the processor is disabled as in sleep mode. All analog blocks are
powered down by default but can be selected to keep running through the power API if
needed as wake-up sources. The main clock and all peripheral clocks are disabled by
default.
Modifications: • Updated Figure 13 “Typical CoreMark score ((iterations/s)/MHz) vs. Frequency (MHz)
from SRAMX”.
• Updated Table 4 “Pin description””: Description of VREFN and VSSA.
• Updated Table 5 “Termination of unused pins”: Added USB1_ID pin.
• Updated Table 13 “CoreMark score”, Typical values.
• Updated Table 3 “Device revision table”.
• Updated Table 4 “Pin description”: VREFN and VSSA.
• Updated Figure 4 “LPC540xx/LPC54S0xx Block diagram”.
• Updated Figure 9 “LPC540xx/LPC54S0xx Memory mapping” and Figure 10
“LPC540xx/LPC54S0xx APB Memory map”.
• Added LPC54016JET100 TFBGA100 device.
• Updated Table 22 “Dynamic characteristic: Typical wake-up times from low power
modes”: Changed twake at typical for deep-sleep mode to 150 s. Was 19 s.
• Updated Section 2 “Features and benefits”. Added text for full-speed USB crystal-less
software library: See Technical note TN00033 for more details.
LPC540xx v.1.5 20180227 Product data sheet - v.1.4

Table 59. Revision history …continued

Modifications: • Updated Table 6 “Pin states in different power modes”: Added table note 3: If VBAT>
VDD, the external reset pin must be floating to prevent high leakage.
• Updated Table 15 “Static characteristics: Power consumption in deep-sleep and deep
power-down modes”: 1.71 V £ VDD  2.2 V. Added table note: At hot temperature and
below 2.0 V, the supply current increases slightly because of reduction of available
RBB (reverse body bias) voltage.
power-down modes”: 1.71 V £ VDD  2.2 V.
• Updated Table 17 “Static characteristics: Power consumption in deep power-down
mode”: Added table note 3: If VBAT> VDD, the external reset pin must be floating to
prevent high leakage.
• Updated Figure 15 “Deep-sleep mode: Typical supply current IDD versus temperature
for different supply voltages VDD”: added remark: At hot temperature and below 2.0 V,
the supply current increases slightly because of reduction of available RBB (reverse
body bias) voltage.
• Added Section 11.14 “SPI interfaces (Flexcomm Interface 10)”.
Modifications: • Updated Figure 3 “LQFP100 package marking”.
Modifications: • Updated features in Section 7.14.8.2 “SPI serial I/O controller”: Maximum data rates of
48 Mbit/s in master mode for SPI functions (Flexcomm Interface 0-9) and 50 Mbit/s in
master mode for SPI functions (Flexcomm Interface 10).
• Updated Section 11.13 “SPI interfaces (Flexcomm Interface 0-9)”: The maximum
supported bit rate for SPI master mode is 48 Mbit/s. Was 71 Mbit/s in master mode.
• Updated footnote 2 of Table 5 “Termination of unused pins”.
power-down modes”: Changed deep-sleep conditions for Idd supply current, SRAMX
(64 KB) powered for 25 C and 105 C, was 32 KB.
power-down modes”: Changed deep-sleep conditions for Idd supply current, SRAMX
(64 KB) powered for 25 C and 105 C, was 32 KB.

Table 59. Revision history …continued

Modifications: • Added Figure 13 “CoreMark power consumption: typical mA/MHz vs. frequency (MHz)
SRAMX”, Figure 14 “Deep-sleep mode: Typical supply current IDD versus temperature
for different supply voltages VDD”, and Figure 15 “Deep power-down mode: Typical
supply current IDD versus temperature for different supply voltages VDD”.
• Updated Table 53 “Temperature sensor static and dynamic characteristics” and Table
54 “Temperature sensor Linear-Least-Square (LLS) fit parameters”.
• Updated Table 14 “Static characteristics: Power consumption in active and sleep
mode”: values for IDD Supply current CoreMark code executed from SRAMX.
power-down modes”: values for deep sleep and deep power-down modes.
power-down modes”: values for deep sleep and deep power-down modes.
• Updated Table 17 “Static characteristics: Power consumption in deep power-down
mode”: value for deep power-down mode.
• Updated table notes for Table 4 “Pin description”, Table 5 “Termination of unused
pins”, and Table 6 “Pin states in different power modes”.
• Updated text in Section 13.2 “Standard I/O pin configuration”.
• Added text to Table note 4 of Figure 43 “Power, clock, and debug connections”.
Modifications: • Removed Figure 12 through Figure 15.
LPC540xx v.1 20171128 Product data sheet - -

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21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 7.15.1 Full-speed USB Host/Device interface (USB0) . .
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 71
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 6 7.15.1.1 USB0 device controller. . . . . . . . . . . . . . . . . . 71
7.15.1.2 USB0 host controller . . . . . . . . . . . . . . . . . . . 72
3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 7
7.15.2 High-speed USB Host/Device interface (USB1) .
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 72
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.15.2.1 USB1 device controller. . . . . . . . . . . . . . . . . . 72
6 Pinning information . . . . . . . . . . . . . . . . . . . . . 12 7.15.2.2 USB1 host controller . . . . . . . . . . . . . . . . . . . 72
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.15.3 Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 14 7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.1 Termination of unused pins. . . . . . . . . . . . . . . 55 7.15.4 SPI Flash Interface (SPIFI) . . . . . . . . . . . . . . 73
6.2.2 Pin states in different power modes . . . . . . . . 56 7.15.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7 Functional description . . . . . . . . . . . . . . . . . . 57 7.15.5 CAN Flexible Data (CAN FD) interface . . . . . 74
7.1 Architectural overview. . . . . . . . . . . . . . . . . . . 57 7.15.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 57 7.15.6 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . . 74
7.3 ARM Cortex-M4 integrated Floating Point Unit 7.15.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.15.7 Smart card interface. . . . . . . . . . . . . . . . . . . . 74
7.4 Memory Protection Unit (MPU). . . . . . . . . . . . 57 7.15.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.5 Nested Vectored Interrupt Controller (NVIC) for 7.15.8 Flexcomm Interface serial communication. . . 74
Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.15.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.15.8.2 SPI serial I/O controller . . . . . . . . . . . . . . . . . 75
7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 58 7.15.8.3 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 75
7.6 System Tick timer (SysTick) . . . . . . . . . . . . . . 58 7.15.8.4 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.7 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 58 7.15.8.5 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . . 76
7.8 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.16 Digital peripheral . . . . . . . . . . . . . . . . . . . . . . 77
7.9 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 59 7.16.1 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 77
7.10 One-Time Programmable (OTP) memory. . . . 62 7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.16.2 SD/MMC card interface . . . . . . . . . . . . . . . . . 78
7.11 System control . . . . . . . . . . . . . . . . . . . . . . . . 63 7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.11.1 Clock sources . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.16.3 External memory controller . . . . . . . . . . . . . . 78
7.11.1.1 Free Running Oscillator (FRO) . . . . . . . . . . . . 63 7.16.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.11.1.2 Watchdog oscillator (WDOSC) . . . . . . . . . . . . 63 7.16.4 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 80
7.11.1.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 63 7.16.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.11.2 System PLL (PLL0). . . . . . . . . . . . . . . . . . . . . 63 7.17 Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 80
7.11.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . . 63 7.17.1 General-purpose 32-bit timers/external event
7.11.4 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . . 64 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.11.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . 65 7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.11.6 Brownout detection . . . . . . . . . . . . . . . . . . . . . 67 7.17.2 SCTimer/PWM . . . . . . . . . . . . . . . . . . . . . . . . 81
7.11.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.12 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.17.3 Windowed WatchDog Timer (WWDT) . . . . . . 82
7.12.1 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.17.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.12.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 67 7.17.4 Real Time Clock (RTC) timer . . . . . . . . . . . . . 82
7.12.3 Deep power-down mode. . . . . . . . . . . . . . . . . 67 7.17.5 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 82
7.13 General Purpose I/O (GPIO) . . . . . . . . . . . . . 70 7.17.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.17.6 Repetitive Interrupt Timer (RIT) . . . . . . . . . . . 83
7.14 Pin interrupt/pattern engine . . . . . . . . . . . . . . 70 7.17.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.18 12-bit Analog-to-Digital Converter (ADC) . . . . 83
7.15 Serial peripherals . . . . . . . . . . . . . . . . . . . . . . 71 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
continued >>

7.19 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13 Application information . . . . . . . . . . . . . . . . 148

7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.1 Start-up behavior . . . . . . . . . . . . . . . . . . . . . 148
7.20 Temperature sensor . . . . . . . . . . . . . . . . . . . . 84 13.2 Standard I/O pin configuration . . . . . . . . . . . 149
7.21 Security features. . . . . . . . . . . . . . . . . . . . . . . 84 13.3 Connecting power, clocks, and debug functions .
7.21.1 SHA-1 and SHA-2. . . . . . . . . . . . . . . . . . . . . . 84 150
7.21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.4 I/O power consumption . . . . . . . . . . . . . . . . 152
7.21.2 AES encryption/decryption . . . . . . . . . . . . . . . 85 13.5 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . 153
7.21.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.5.1 RTC Printed Circuit Board (PCB) design
7.21.3 PUF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.21.3.1 PUF keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 13.6 XTAL oscillator . . . . . . . . . . . . . . . . . . . . . . . 155
7.21.3.2 PUF controller features. . . . . . . . . . . . . . . . . . 85 13.6.1 XTAL Printed Circuit Board (PCB) design
7.22 Emulation and debugging . . . . . . . . . . . . . . . . 86 guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 87 13.7 Suggested USB Full-speed interface solutions . .
9 Thermal characteristics. . . . . . . . . . . . . . . . . . 90 156
13.8 USB1 High-speed VBUS threshold levels . . 157
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 91
10.1 General operating conditions . . . . . . . . . . . . . 91 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 159
10.2 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 91 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.3 Power consumption . . . . . . . . . . . . . . . . . . . . 93 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 167
10.4 Pin characteristics. . . . . . . . . . . . . . . . . . . . . . 99 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
10.4.1 Electrical pin characteristics . . . . . . . . . . . . . 102 18 Revision history . . . . . . . . . . . . . . . . . . . . . . 168
11 Dynamic characteristics . . . . . . . . . . . . . . . . 105 19 Legal information . . . . . . . . . . . . . . . . . . . . . 171
11.1 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 171
11.2 Wake-up process . . . . . . . . . . . . . . . . . . . . . 106 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.3 External memory interface . . . . . . . . . . . . . . 107 19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.4 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . 116 19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.5 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . 117
20 Contact information . . . . . . . . . . . . . . . . . . . 172
11.6 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . 117
11.7 FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
11.8 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 118
11.9 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 119
11.10 Watchdog oscillator . . . . . . . . . . . . . . . . . . . 120
11.11 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.12 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 123
11.13 SPI interfaces (Flexcomm Interface 0-9) . . . 126
11.14 SPI interfaces (Flexcomm Interface 10) . . . . 129
11.15 SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.16 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . 134
11.17 Smart card interface . . . . . . . . . . . . . . . . . . . 134
11.18 USART interface . . . . . . . . . . . . . . . . . . . . . . 135
11.19 SCTimer/PWM output timing . . . . . . . . . . . . 136
11.20 USB interface characteristics . . . . . . . . . . . . 136
11.22 Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . 137
11.23 SD/MMC and SDIO . . . . . . . . . . . . . . . . . . . 139
11.24 LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12 Analog characteristics . . . . . . . . . . . . . . . . . 141
12.1 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.2 12-bit ADC characteristics . . . . . . . . . . . . . . 142
12.2.1 ADC input impedance. . . . . . . . . . . . . . . . . . 145
12.3 Temperature sensor . . . . . . . . . . . . . . . . . . . 146
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2020. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 15 September 2020
Document identifier: LPC540xx/LPC54S0xx
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
NXP:
OM40007UL OM40006UL LPC54005JET100E LPC54016JBD100E LPC54005JBD100E LPC54018JET180E
LPC54018JBD208E LPC54016JET180E LPC54016JBD208E LPC54016JET100E LPC54S018JET180E
LPC54S016JBD100E LPC54S016JET100E LPC54S018JBD208E LPC54S016JET180E LPC54S005JBD100E
LPC54S005JET100E LPC54S016JBD208E LPC54S018JET180K LPC54016JBD208Y LPC54016JBD100Y
LPC54S016JBD100Y

LPC540xx/LPC54S0xx: 1. General Description

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LPC540xx/LPC54S0xx: 1. General Description

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LPC540xx/LPC54S0xx

32-bit ARM Cortex-M4 microcontroller; 360 kB SRAM;

2. Features and benefits

Product data sheet Rev. 2.1 — 15 September 2020 2 of 174

Product data sheet Rev. 2.1 — 15 September 2020 3 of 174

 DMIC subsystem includes a dual-channel PDM microphone interface with decimators,

Product data sheet Rev. 2.1 — 15 September 2020 4 of 174

Product data sheet Rev. 2.1 — 15 September 2020 5 of 174

Product data sheet Rev. 2.1 — 15 September 2020 6 of 174

3.1 Ordering options

EMC data bus width (bit)

Product data sheet Rev. 2.1 — 15 September 2020 7 of 174

Terminal 1 index area

Fig 3. LQFP100 package marking

The LPC540xx/LPC54S0xx TFBGA180 and TFBGA100 packages have the following

• First line: LPC540xx/LPC54S0xxJ

The LPC540xx/LPC54S0xx LQFP208 and LQFP100 packages have the following

• First line: LPC540xx/LPC54S0xxJ

Product data sheet Rev. 2.1 — 15 September 2020 8 of 174

– xR = Boot code version and device revision.

Table 3. Device revision table

Product data sheet Rev. 2.1 — 15 September 2020 9 of 174

Product data sheet Rev. 2.1 — 15 September 2020 10 of 174

JTAG test and

DEBUG INTERFACE GENERAL ETHERNET USB 2.0 CLOCK GENERATION,

BOOT ROM HS USB HS USB

SHA SLAVE FS USB HS USB AES256 12b ADC ADC

USB RAM POLYFUSE OTP TEMP

SPIFI EMC DMA LCD FS USB SCTimer/ FlexComms 0-4

CAN 0 CAN 1 ETHERNET HS USB CRC SDIO FlexComms 5-9

PERIPH INPUT MUX SELECTS 32-BIT TIMERS (T2)

2 x 32-BIT TIMERS (T0, 1) RIT

MULTI-RATE TIMER 2 x SMARTCARDS

OTP CONTROLLER RANDOM NUMBER GEN

Fig 4. LPC540xx/LPC54S0xx Block diagram

Product data sheet Rev. 2.1 — 15 September 2020 11 of 174

Transparent top view

Fig 5. TFBGA 180 Pin configuration

Transparent top view

Fig 6. TFBGA 100 Pin configuration

Product data sheet Rev. 2.1 — 15 September 2020 12 of 174

Fig 7. LQFP 208 Pin configuration

Fig 8. LQFP 100 Pin configuration

Product data sheet Rev. 2.1 — 15 September 2020 13 of 174

6.2 Pin description

Table 4. Pin description

Reset state[1] [9]

Product data sheet Rev. 2.1 — 15 September 2020 14 of 174

Table 4. Pin description …continued

Reset state[1] [9]

Product data sheet Rev. 2.1 — 15 September 2020 15 of 174

Table 4. Pin description …continued

Reset state[1] [9]

Product data sheet Rev. 2.1 — 15 September 2020 16 of 174

Table 4. Pin description …continued

Reset state[1] [9]

Product data sheet Rev. 2.1 — 15 September 2020 17 of 174

Table 4. Pin description …continued

Reset state[1] [9]