Digital Logic Design (EEEg4302)

Chapter 5: Combinational Logic

AASTU
Department of Electrical and
Electronics Engineering By Milkias H.

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Outline
• Chapter 5 : Combinational Logic
• Introduction
• Basic Combinational Logic Circuits
• Combinational Logic using NAND and NOR Gates
• Functions of Combinational Logic
• Implementing Combinational Logic
• Binary Adder and Subtractor
• Magnitude Comparator
• Decoder and Encoders
• Multiplexers and Demultiplexers

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 Introduction

• Logic circuit for digital systems can be combinational or sequential.

• A combinational circuit consists of logic gates whose outputs at anytime are
determined from only the present combination of inputs.
• A combinational circuit performs an operation that can be specified logically by a set
of Boolean functions.
• In contrast, sequential circuits employ storage elements in addition to logic gates.
• The outputs of sequential circuits are a function of the input and the state of the
storage elements.

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 Basic Combinational Logic Circuits

• As you know, SOP expressions are implemented with an AND gate for each
product term and one OR gate for summing all of the product terms.
• This SOP implementation is called AND-OR logic and is the basic form for realizing
standard Boolean functions.
• Here, we will see the AND-OR and the AND-OR-Invert; the Exclusive-OR and
Exclusive-NOR which are a form of AND-OR logic.

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 Basic Combinational Logic Circuits

AND-OR logic
• An AND-OR circuit directly implements an SOP expression, assuming the complements
(if any) of the variables are available.
Example : for a 4- input AND-OR logic circuit, the output X is HIGH (1) if both inputs A and
B are HIGH(1) or both input C and input D are HIGH(1).

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 Basic Combinational Logic Circuits

AND-OR-Invert logic
• When the output of an AND-OR circuit is complimented (inverted),it results AND-OR-
Invert circuit. Since AND-OR logic directly implements SOP expressions. POS
expressions can be implemented with AND-OR-Invert Logic.
Example : for a 4- input AND-OR-Invert logic circuit, the output X is LOW(0) if both
inputs A and B are HIGH(1) or both input C and input D are HIGH(1).

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 Basic Combinational Logic Circuits

Exclusive-OR logic
• Although, because of its importance Exclusive-OR is considered as a type of logic gate
with its own unique symbol. It is actually a combination of 2 AND gates, 1 OR gate and
2 inverters.
X = A𝐵 + 𝐴B X=A⨁B

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 Basic Combinational Logic Circuits

Exclusive- NOR logic

• Implemented by simply inverting the output of an exclusive-OR.

X = A𝐵 + 𝐴B = 𝐴𝐵 + AB X = A⨀B

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 Combinational Logic using NAND and NOR Gates
• NAND and NOR gates can be used to implement a logic function.
• The NAND gate also exhibits an equivalent operation called the negative-OR 𝑨𝑩 =𝑨 + 𝑩 .
• The NOR gate also exhibits an equivalent operation called the negative-AND 𝑨 + 𝑩 =𝑨𝑩.
• Use of the appropriate symbols to represent the equivalent operation makes the “reading”
a logic diagram easier (bubble to bubble).
Example 1: NAND Logic for X=AB+CD

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 Combinational Logic using NAND and NOR Gates

Example 2: NOR Logic for X=(A+B)(C+D)

Exercise: 1. Implement the expression X = (𝑨 + 𝑩 + 𝑪)𝑫𝑬 by using NAND logic.

2. Implement the expression X = 𝑨𝑩𝑪 + 𝑫 + 𝑬 by using NOR logic.

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 Functions of Combinational Logic
• When logic gates are connected together to produce a specified output for certain
specified combinations of input variables with no storage involved; the resulting
circuit is in the category of Combinational logic.
• In combinational logic , the output level is at all times dependent on the combination
of input levels.
• A combinational circuit consists of an interconnection of logic gates.
• Combinational logic gates react to the values of the signals at their inputs and
produce the value of the output signal, transforming binary information from the
given input data to a required output data.
• A block diagram of a combinational circuit is shown in figure below. The n input binary
variables come from an external source; the m output variables are produced by the
internal combinational logic circuit and go to an external destination.

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 Implementing Combinational Logic

Design Procedure
• The design of combinational circuits starts from the specification of the design objectives
and is converted to a set of Boolean functions from which the logic diagram can be
obtained.
• The procedure involves the following steps;
I. Determine the required number of inputs and outputs and assign a symbol to each.
II. Derive the truth table that defines the required relationship between inputs and
outputs.
III. Obtain the simplified Boolean functions for each output as a function of the input
variables.
IV. Draw the logic diagram and verify the correctness of the design.

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 Binary Adder and Subtractor

• Digital computers perform a variety of information-processing tasks. Among the

functions encountered are the various arithmetic operations.
• The most basic arithmetic operation is the addition of two binary digits.
• An understanding of the basic adder operation is fundamental to the study of digital
systems.
• This simple addition consists of four possible elementary operations:
0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10.
• The first three operations produce a sum of one digit but when both augend and
addend bits are equal to 1, the binary sum consists of two digits. The higher
significant bit of this result is called a carry.

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 Binary Adder and Subtractor

• When the augend and addend numbers contain more significant digits, the carry
obtained from the addition of two bits is added to the next higher order pair of
significant bits.
• A combinational circuit that performs the addition of two bits is called a half adder.
• One that performs the addition of three bits (two significant bits and a previous
carry) is a full adder. The names of the circuits comes from the fact that two Half
adders can be employed to implement a full adder.
• The basic difference between a full-adder and a half-adder is that the full-adder
accepts an input carry.

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 Binary Adder and Subtractor

Half Adder
• From the explanation of a half adder, we find that this circuit needs two binary inputs
and two binary outputs.
• The input variables designate the augend and addend bits; the output variables
produce the sum and carry.
• We assign symbols X and Y to the two inputs and S (for sum) and C (for carry) to the
outputs.
• The truth table for the half adder is listed in the following Table .

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Binary Adder and Subtractor

Half Adder

Implementation of Half Adder

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 Binary Adder and Subtractor

Full Adder
• A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs.
• Two of the input variables, denoted by X and Y represent the two significant bits to
be added.
• The third input Z, represents the carry (Ci )from the previous lower significant
position.
• Two outputs are necessary because the arithmetic sum of three binary digits ranges
in value from 0 to 3 and binary representation of 2 or 3 needs two bits.
• The two outputs are designated by the symbols S for sum and C for carry.

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 Binary Adder and Subtractor

Full Adder
• The truth table of the full adder is listed in the following Table.

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Binary Adder and Subtractor
Full Adder

Implementation of full adder in sum-of-products form

Implementation of a full adder with two half adders and an OR gate

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Binary Adder and Subtractor

Parallel Binary Adders

• Addition of n-bit binary numbers requires the use of a full adder and the process of
addition proceeds on a bit-by-bit basis right to left beginning with the least significant
bit.
• After the least significant bit, addition at each position adds not only the respective
bits of the words but must also consider a possible carry bit from addition at the
previous position.
• Addition of n-bit numbers requires a chain of n full adders or a chain of one-half
adder and n-1 full adders. In the former case, the input carry to the least significant
position is fixed at 0.
• For Example: 4-bit parallel adder

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Binary Adder and Subtractor

Parallel Binary Adders

Example: 4-bit parallel adder

• To demonstrate with a specific example, consider the two binary numbers A = 1011
and B = 0011. Their sum S = 1110 is formed with the four-bit adder as follows:

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Binary Adder and Subtractor

Binary Subtractor
• The subtraction of binary numbers can be done most conveniently by means of
complements.
• Remember that the subtraction A - B can be done by taking the 2’s complement of B
and adding it to A .
• The 2’s complement can be obtained by taking the 1’s complement and adding 1 to
the least significant pair of bits.
• The 1’s complement can be implemented with inverters and a 1 can be added to the
sum through the input carry.
• The addition and subtraction operations can be combined into one circuit with one
common binary adder by including an exclusive-OR gate with each full adder.

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Binary Adder and Subtractor
Binary Subtractor
• A four-bit Adder–Subtractor circuit is shown in the following Figure. The mode input
M controls the operation. When M = 0, the circuit is an adder and when M = 1, the
circuit becomes a Subtractor.
• Each exclusive-OR gate receives input M and one of the inputs of B . When M = 0, we
have B ⨁ 0 = B. The full adders receive the value of B , the input carry is 0, and the
circuit performs A plus B . When M = 1, we have B ⨁ 1 = B and C0 = 1.
• The B inputs are all complemented and a 1 is added through the input carry. The
circuit performs the operation A plus the 2’s complement of B. (The exclusive-OR
with output V is for detecting an overflow.)

Four-bit Adder–Subtractor
(with overflow detection)

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Magnitude Comparator
• The comparison of two numbers is an operation that determines whether one
number is greater than, less than, or equal to the other number.
• A magnitude comparator is a combinational circuit that compares two numbers A
and B and determines their relative magnitudes.
• The outcome of the comparison is specified by three binary variables that indicate
whether A >B, A = B or A < B.
• The circuit for comparing two n -bit numbers has 22n entries in the truth table and
becomes too bulky even with n = 3.
• Since a comparator circuit possesses a certain amount of regularity. Digital functions
that possess an inherent well-defined regularity can usually be designed by means of
an algorithm.
• The algorithm is a direct application of the procedure a person uses to compare the
relative magnitudes of two numbers.

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Magnitude Comparator
• Example: Consider two numbers, A and B with four digits each. Write the coefficients
of the numbers in descending order of significance:

• Each subscripted letter represents one of the digits in the number. The two numbers
are equal if all pairs of significant digits are equal: A3 = B3, A2 = B2, A1 = B1, and
A0 = B0.It can be expressed logically with an exclusive-NOR function.

• The equality of the two numbers A and B is displayed in a combinational circuit by an

output binary variable that we designate by the symbol A = B .

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Magnitude Comparator
• If the corresponding digit of A is 1 and that of B is 0, we conclude that A > B. If the
corresponding digit of A is 0 and that of B is 1, we have A < B. The sequential
comparison can be expressed logically by the two Boolean functions.

• The symbols (A > B) and (A < B) are binary output variables that are equal to 1 when
A > B and A < B, respectively.
• The unequal outputs can use the same gates that are needed to generate the equal
output.

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Magnitude Comparator

The logic diagram of the four-bit magnitude comparator

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Decoder
• Discrete quantities of information are represented in digital systems by binary codes.
• A binary code of n bits is capable of representing up to 2n distinct elements of coded
information.
• A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. If the n -bit coded information has
unused combinations, the decoder may have fewer than 2n outputs.
• Each combination of inputs will assert a unique output.
• The name decoder is also used in conjunction with other code converters such as a
BCD-to-seven-segment decoder.
• The decoders presented here are called n -to- m -line decoders, where m ≤ 2n . Their
purpose is to generate the 2n (or fewer) terms of n input variables.
• Decoder can be developed using AND logic gates.
n to m
Decoder
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 Decoder
Example: The three-to-eight-line (3 to 8) decoder circuit
• The three inputs are decoded into eight outputs, each representing one of the
product terms of the three input variables.

3 to 8
Decoder

The operation of the decoder may be clarified by the truth table listed in
the Table. For each possible input combination, there are seven outputs
that are equal to 0 and only one that is equal to 1. 29
Decoder
Decoder with an Enable Input
• A decoder with enable input can function as a Demultiplexer— a circuit that receives
information from a single line and directs it to one of 2n possible output lines.

2 to 4
Decoder

Enable

A two-to-four-line decoder with an enable input(Enable 0 or Active Low) constructed with NAND gates.

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Decoder
Decoder with an Enable Input
• In general, enable inputs are a convenient feature for interconnecting two or more
standard components for the purpose of combining them into a similar function with
more inputs and outputs.
• Decoders with enable inputs can be connected together to form a larger decoder
circuit.
• Example: Two 3-to-8-line decoders with enable inputs connected to form a 4-to-16-line
decoder.

4 to 16
Decoder

Enable

4 x 16 decoder constructed with two 3 x 8 decoders 31

Decoder
BCD-to-Decimal Decoder (Application)
4-line-to-10-line decoder.

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Decoder
BCD-to-7-Segement Decoder (Application)
4-line-to-7-line decoder.

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Encoder

• An encoder is a digital circuit that performs the inverse operation of a decoder.

• An encoder has 2n (or fewer) input lines and n output lines.
• The output lines as an aggregate generate the binary code corresponding to the input
value.
• An encoder can be implemented with OR gates whose inputs are determined directly
from the truth table.
• It accepts an active level on one of its inputs representing a digit, such as a decimal or
octal digit and converts it to a coded output, such as BCD or binary.
• The process of converting from familiar symbols or numbers to a coded format is
called encoding.

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Encoder

Example: Octal-to-Binary (8-to-3)Encoder(Application).

• It has eight inputs (one for each of the octal digits) and three outputs that generate
the corresponding binary number.

• Output z is equal to 1 when the input octal digit is 1, 3, 5or 7. Output y is 1 for octal
digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These conditions can be
expressed by the following Boolean output functions:

• The encoder can be implemented with three OR gates.

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Encoder

Example: Decimal-to-BCD Encoder(Application).

• It has Ten inputs (one for each of the Decimal digits) and four outputs that generate
the corresponding BCD.

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Multiplexer

• A multiplexer is a combinational circuit that selects binary information from one of

many input lines and directs it to a single output line.
• A multiplexer (MUX) is a data selection device that allows digital information from
several sources to be routed onto a single line for transmission over that lines to a
common destination.
• The selection of a particular input line is controlled by a set of selection lines.
Normally, there are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
• A multiplexer acts like an electronic switch that selects one of many sources.

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Multiplexer

Example 1: Two-to-one-line multiplexer [connects one of two 1-bit sources to a

common destination]

• The circuit has two data input lines (I0 & I1), one output line (Y) and one selection
line S . When S = 0, the upper AND gate is enabled and I0 has a path to the output.
When S = 1, the lower AND gate is enabled and I1 has a path to the output.
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Multiplexer

Example 1: A four-to-one-line multiplexer

• Each of the four inputs, I0 through I3, is applied to one input of an AND gate.
Selection lines S1 and S0 are decoded to select a particular AND gate.
• The outputs of the AND gates are applied to a single OR gate that provides the one-
line output.
• The function table lists the input that is passed to the output for each combination
of the binary selection values.

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Demultiplexer

• A Demultiplexer (DEMUX) basically reverse the multiplexing function.

• It takes digital information form one line and distributes it to a given number of
output lines.
• Data goes from one line to several lines.
• A multiplexer acts like an electronic switch that selects one of many sources.
• The demultiplexer is also known as a data distributer. As we have seen, decoders can
also be used as demultiplexers.
Example : one line to four line Demultiplexer.

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Last slide

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