Digital Electronics 1 1

Combinational Logic Circuits

Circuits made up of combinations of logic gates, with no feedback from the
outputs to inputs.

Three Methods of Simplification of Logic Circuits

Boolean Algebra Theorems
Mapping Technique (Veitch Diagram or Karnaugh Map(K-Map))
Tabulation Technique (Quine-McCluskey Method)

Sum-Of-Products (SOP) Form

Sum-of-products expressions consist of two or more AND terms (product)
that are ORed together.
Each AND term consists of one or more variables individually appearing in
either complemented or uncomplemented form.

Example:
1. 𝐴𝐵𝐶 + 𝐴𝐵𝐶
2. 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐶̅ 𝐷
̅+𝐷
3. ̅ ̅
𝐴𝐵 + 𝐶𝐷 + 𝐸𝐹 + 𝐺𝐾 + 𝐻𝐿

Note that in a sum-of-products expression, one inversion sign cannot cover

more than one variable in a term.
Example: we cannot have 𝐴𝐵𝐶 𝑜𝑟 𝑅𝑆𝑇

Product-Of-Sum (POS) Form

Product-of-sums expressions consist of two or more OR terms (sums) that
are ANDed together.
Each OR term contains one or more variables in complemented or
uncomplemented form.

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Digital Electronics 1 2

Example:
1.( A + B + C )( A + C )
2.( A + B )(C + D )F
3.( A + C )( B + D )( B + C )( A + D + E )

The methods of circuit simplification and design that we will be using are
based on the sum-of-products form, so we will not be doing much with the
product-of-sums form. It will, however, occur from time to time in some logic
circuits that have a particular structure.

ALGEBRAIC SIMPLIFICATION
The examples that follow will illustrate many of the ways in which the
Boolean theorems can be applied in trying to simplify an expression.
You should notice that these examples contain two essential steps:
1. The original expression is put into the sum-of-products form by
repeated application of DeMorgan's theorems and multiplication of
terms.
2. Once the original expression is in this form, the product terms are
checked for common factors, and factoring is performed wherever
possible. Hopefully, the factoring results in the elimination of one or
more terms.

Example 1:
Simplify the logic circuit shown.

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 3

Example 2:
Simplify the circuit using Boolean algebra.

Example 3:
Change each NAND gate in Exercise no.2 to a NOR gate, and simply the
circuit using Boolean algebra.

Designing Combinational Logic Circuits

When the desired output level of a logic circuit is given for all possible input
conditions, the results can be conveniently displayed in a truth table.
The Boolean expression for the required circuit can then be derived from the
truth table.
Once the output expression has been determined from the truth table in
sum-of-products from, it can easily be implemented using AND and OR
gates, and INVERTERs.

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 4

Example 1:
Design a logic circuit that has three inputs, A, B, and C, and whose output
will be HIGH only when a majority of the inputs are HIGH.

Solution:

Step 1: Set up the truth table.

A B C x
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Step 2: Write the AND term for each case where the output is a 1.
A B C x
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 ABC
1 0 0 0
1 0 1 1 A BC
1 1 0 1 AB C
1 1 1 1 ABC

Step 3: Write the sum-of-products expression for the output.

x = ABC + A BC + AB C + ABC

Step 4: Simplify the output expression.

This expression can be simplified in several ways.
Perhaps the quickest way is to realize that the last term ABC has two
variables in common with each of the other terms.
Thus, we can use the ABC term to factor with each of the other terms.
The expression is rewritten with the ABC term occurring three times.

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 5

x = ABC + ABC + A BC + ABC + AB C + ABC

x = ( A + A) BC + ( B + B ) AC + (C + C ) AB
x = BC + AC + AB

Step 5: Implement the circuit based on the final expression.

Example 2:
Design the logic circuit corresponding to the truth table shown.
Truth table
A B C x
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Example 3:
A manufacturing plant needs to have a horn sound to signal quitting time. The
horn should be activated when either of the following conditions is met.
1. It’s after 5 o’clock and all machines are shut down.
2. It’s Friday, the production run for the day is complete, and all
machines are shut down.
Design a logic circuit that will control the horn.
(Hint: Use four logic input variables to represent the various conditions; for
example, input A will be HIGH only when the time of the day is 5 o,clock or
later.)

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 6

MAP METHOD
The map method, first proposed by E.W. Vietch and slightly modified by M.
Karnaugh, is also known as the “Veitch Diagram” or the “Karnaugh
Map”.

KARNAUGH MAP METHOD

The Karnaugh map is a graphical device used to simplify a logic equation
or to convert a truth table to its corresponding logic circuit in a simple, orderly
process.
Although a Karnaugh map (henceforth abbreviated K map) can be used for
problems involving any number of input variables, its practical usefulness is
limited to six variables.

TWO-VARIABLE MAP
There are four minterms for two variables; hence consists of four squares,
one for each minterm.

Note:
Minterm (also known as standard product) is an AND term of the n variables.
Maxterm (also known as standard sum) is an OR term of the n variables.

m0 m1

m2 m3

B
B B A 0 1

A m0 m1 0 A B A B

A m2 m3 1 A B A B

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 7

EXAMPLE:

TRUTH TABLE
A B X
0 0 1 AB
0 1 0
1 0 0
1 1 1 AB

x = A B + AB

B
B B A 0 1

A 1 0 0 1 0

A 0 1 1 0 1

THREE-VARIABLE MAP

BC C
A 00 01 11 10 AB 0 1

0 m0 m1 m3 m2 00 m0 m1

1 m4 m5 m7 m6 01 m2 m3

11 m6 m7

10 m4 m5

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 8

EXAMPLE:
TRUTH TABLE
A B C X
0 0 0 1 A BC
0 0 1 1 A BC
0 1 0 1 AB C
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1 AB C
1 1 1 0

x = A BC + A BC + ABC + AB C

BC C
A 00 01 11 10 AB 0 1

0 1 1 0 1 00 1 1

1 0 0 0 1 01 1 0

11 1 0

10 0 0

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 9

FOUR-VARIABLE MAP

CD 00 01 11 10
AB

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 10

EXAMPLE:
TRUTH TABLE
A B C D X
0 0 0 0 0
0 0 0 1 1 A BC D
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1 ABC D
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1 AB C D
1 1 1 0 0
1 1 1 1 1 ABCD
x = A BC + A BC + ABC + AB C

CD
AB 00 01 11 10

00 0 1 0 0

01 0 1 0 0

11 0 1 1 0

10 0 0 0 0

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 11

LOOPING
The expression for output X can be simplified by properly combining those
squares in the K map which contain 1s.
The process for combining these 1s is called looping.

Looping Groups of Two (Pairs)

Looping a pair of adjacent 1s in a K map eliminates the variable that appears
in complemented and uncomplemented form.

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 12

Looping Groups of four (Quads)

Looping a quad of 1s eliminates the two variables that appear in both
complemented and uncomplemented form.

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Digital Electronics 1 13

Looping Groups of eigth (octets)

Looping an octet of 1s eliminates the three variables that appear in both
complemented and uncomplemented form.

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Digital Electronics 1 14

Complete Simplification Process

The procedure will first be outlined and then applied to several examples.
The steps below are followed in using the K-map method for simplifying a
Boolean expression:

Step 1:
Construct the K map and place 1s in those squares corresponding to the
1s in the truth table. Place 0s in the other squares.

Step 2:
Examine the map for adjacent 1s and loop those 1s which are not adjacent
to any other 1s. These are called isolated Is.

Step 3:
Next, look for those 1s which are adjacent to only one other 1. Loop any
pair containing such a 1.

Step 4:
Loop any octet even it contains some 1s that have already been looped.

Step 5:
Loop any quad that contains one or more 1s that have not already been
looped, making sure to use the minimum number of loops.

Step 6:
Loop any pairs necessary to include any 1s that have not yet been looped,
making sure to use the minimum number of loops.

Step 7:
Form the OR sum of all the terms generated by each loop.

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 15

Example:

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Digital Electronics 1 16

Example:
Use the K-map to simplify the expression y = ABC + BC + AB .

"Don’t Care" Conditions

Some logic circuits can be designed so that there are certain input
conditions for which there are no specified output levels, usually because
these input conditions will never occur.
In other words, there will be certain combinations of input levels where we
"don't care" whether the output is HIGH or LOW.

y=A

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 17

Problem:

Simplify the following expressions using K-map and implement the

simplified Boolean function with logic gates.
a. ) x = ABC + AC
b.)w = ABC + A BC + A
c .) x = A BC + ABC + ABC + A BC + A BC
d .) x = W Z + XZ + XY + W X Z
e .) y = BD + ABC + AB C + A BC
f .)z = A BC + BC D + BCD + AC D + A BC + ABC D
g .)z = WXY + YZ + X Y Z + XY

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Digital Electronics 1 18

Canonical and Standard Forms

MINTERMS MAXTERMS
x y z Term Designation Term Designation
0 0 0 x’y’z’ m0 x+y +z M0
0 0 1 x'y’z m1 x + y + z’ M1
0 1 0 x'yz’ m2 x + y’ + z M2
0 1 1 x'yz m3 x + y’ + z’ M3
1 0 0 xy'z’ m4 x' + y + z M4
1 0 1 xy'z m5 x' + y + z’ M5
1 1 0 xyz' m6 x' + y ‘ + z M6
1 1 1 xyz m7 x' + y’ + z’ M7
Minterm (also known as standard product) is an AND term of the n variables.
Maxterm ( also known as standard sum) is an OR term of the n variables.

Canonical Forms

Boolean functions expressed as a sum of minterms or product of maxterms.

Example:
x y z Function f1 Function f2
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum Of Minterms

f 1 = m1 + m4 + m7
f 2 = m3 + m5 + m6 + m7

Product Of Maxterms.

f1 = M0 . M2 . M3 . M5 . M6
f2 = M0 . M1 . M2 . M4

Prepared By: Engr. Mark Anthony C. Aseoche

Digital Electronics 1 19

It is sometimes convenient to express the Boolean function, when in its sum

of minterms, in the following short notation:

F1(x, y, z) = Σ ( 1, 4, 7 )
F2(x, y, z) = Σ ( 3, 5, 6, 7 )

The summation symbol Σ stands for ORing of terms; the numbers

following it are the minterms of the function.

For product of sum

F1(x, y, z) = π ( 0, 2, 3, 5,6 )
F2(x, y, z) = π ( 0, 1 ,2 ,4 )

The product symbol, π, denotes the ANDing of maxterms ; the numbers

are the maxterms of the function

Problem Set:
1. Obtain the simplified expressions in sum of products for the following Boolean
functions:
a. F (x, y, z) = Σ ( 2, 3, 6, 7 )
b. F(A, B, C, D) = Σ ( 7, 13, 14, 15 )
c. F(A, B, C, D) = Σ ( 4, 6, 7, 15 )
d. F (w, x, y, z) = Σ ( 2, 3, 12 ,13 ,14 ,15)

2. Obtain the simplified expressions in product of sums for the following Boolean
functions:
a. F1(x, y, z) = π ( 0, 1, 4, 5 )
b. F(A, B, C, D) = π ( 0, 1, 2, 3, 4, 10, 11 )
c. F1(w, x, y, z) = π ( 1, 3, 5, 7, 13, 15 )

3. Simply the Boolean function :

F (w, x, y, z) = Σ ( 1, 3, 7, 11, 15 )
and don’t care conditions :
d (w, x, y, z) = Σ ( 0, 2, 5 )

Prepared By: Engr. Mark Anthony C. Aseoche